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1. 发明授权

US06191974B1 Nonvolatile semiconductor memory 失效
标题翻译：非易失性半导体存储器
公开(公告)号：US06191974B1
公开(公告)日：2001-02-20
申请号：US09321092
申请日：1999-05-27
申请人： Yoichi Nishida , Tomonori Kataoka , Ikuo Fuchigami , Tomoo Kimura , Junji Michiyama , Satoshi Koutaka
发明人： Yoichi Nishida , Tomonori Kataoka , Ikuo Fuchigami , Tomoo Kimura , Junji Michiyama , Satoshi Koutaka
IPC分类号： G11C1604
CPC分类号： G11C16/32
摘要： There is provided a nonvolatile semiconductor memory which is capable of operating stably and performing high-speed access operation. A timing generation means 51 for generating timing signals which make a memory core unit 4 perform access operation uses first and second clocks of the same cycle and different phases. The timing generation means 51 generates timing signals for at least one first-half event among a plurality of read access events, according to the first clock, the phase of which precedes a phases of the second clock, and generates timing signals used for processing the remaining events, according to the second clock.
摘要翻译：提供了能够稳定运行并执行高速存取操作的非易失性半导体存储器。用于产生使存储器核心单元4执行访问操作的定时信号的定时产生装置51使用相同周期和不同相位的第一和第二时钟。定时产生装置51根据第一时钟产生多个读取访问事件中的至少一个前半个事件的定时信号，该第一时钟的相位在第二时钟的相位之前，并产生用于处理第二时钟的定时信号剩下的事件，按照第二个时钟。

2. 发明授权

US06172917B2 Semiconductor memory device and regulator 有权
标题翻译：半导体存储器件和调节器
公开(公告)号：US06172917B2
公开(公告)日：2001-01-09
申请号：US09309581
申请日：1999-05-11
申请人： Tomonori Kataoka , Yoichi Nishida , Ikuo Fuchigami , Tomoo Kimura , Junji Michiyama
发明人： Tomonori Kataoka , Yoichi Nishida , Ikuo Fuchigami , Tomoo Kimura , Junji Michiyama
IPC分类号： G11C700
CPC分类号： G11C16/3459 , G11C16/10 , G11C16/3454
摘要： A semiconductor memory device having nonvolatile memory cells arranged in matrix comprises and bit lines connected to drains of the memory cells. Latches provided for the respective bit lines or in the ratio of one latch to a number of bit lines, as are; transfer gates for electrically separating the respective latches from the bit lines. The device also having bit line voltage detection circuits for detecting voltages of the respective bit lines and latch reset circuits for inverting data stored in the respective latches in accordance with the outputs from the bit line voltage detection circuits. Therefore, data stored in each latch can be rewritten even by a very small memory cell current, resulting in stable program verify.
摘要翻译：具有排列成矩阵状的非易失性存储单元的半导体存储器件和连接到存储单元的漏极的位线。针对各个位线提供的锁存器或一个锁存器与多个位线的比率一样; 传输门，用于将各个锁存器与位线电分离。该装置还具有位线电压检测电路，用于根据位线电压检测电路的输出检测各位线的电压和锁存复位电路，用于反相存储在各个锁存器中的数据。因此，即使通过非常小的存储单元电流，存储在每个锁存器中的数据也可以被重写，从而导致稳定的程序验证。

3. 发明申请

US20080126906A1 Communication method and communication device 有权
标题翻译：通讯方式及通讯装置
公开(公告)号：US20080126906A1
公开(公告)日：2008-05-29
申请号：US11819290
申请日：2007-06-26
申请人： Tadanori Tezuka , Tsutomu Sekibe , Shunichi Kuromaru , Junji Michiyama , Hiroshi Nakamura , Masaaki Kondo , Takashi Nanya , Masashi Imai , Nassu Tomoyuki Bogdan
发明人： Tadanori Tezuka , Tsutomu Sekibe , Shunichi Kuromaru , Junji Michiyama , Hiroshi Nakamura , Masaaki Kondo , Takashi Nanya , Masashi Imai , Nassu Tomoyuki Bogdan
IPC分类号： G06F11/07 , H04L1/00
CPC分类号： H04L1/0025 , H04L51/063 , H04L67/32
摘要： A request change unit outputs a command as a request under control of a judgment control unit. A response condition determination unit determines a condition that is to be matched by a correct response which is to be returned from the other device-in-communication in reply to the command if the other device-in-communication operates in conformity with a protocol. A check unit checks a response received from the other device-in-communication in reply to the command, against the condition. If the received response does not match the condition but is correctable to match the condition as a result of the check, a response correction unit corrects the received response to match the condition under control of the judgment control unit.
摘要翻译：请求改变单元在判断控制单元的控制下输出作为请求的命令。响应条件确定单元如果其他设备在通信中的协议一致地操作，则确定要从其他设备在通信中返回的正确响应匹配的条件。检查单元根据该条件检查从其他通信设备接收的响应于该命令的响应。如果接收到的响应与条件不匹配，但是作为检查结果可以校正以匹配条件，则响应校正单元校正所接收的响应以与判断控制单元的控制下的条件相匹配。

4. 发明申请

US20050108307A1 Arithmetic unit 有权
公开(公告)号：US20050108307A1
公开(公告)日：2005-05-19
申请号：US10998012
申请日：2004-11-29
申请人： Shunichi Kuromaru , Koji Okamoto , Junji Michiyama
发明人： Shunichi Kuromaru , Koji Okamoto , Junji Michiyama
IPC分类号： G06F7/76 , G06F7/00 , H04B14/04
CPC分类号： G06F7/76
摘要： The present invention provides an arithmetic unit comprising an input register for storing externally input digital data as a P-bit digital data, an output register for storing a Q-bit digital data, and an output bit selecting means. The output bit selecting means is operable to receive the P-bit digital data which is output from the input register as a first input data, and the Q-bit digital data which is output from the output register as a second input data. The output big selecting means is further operable to select bits, values of which bits are to be output, among bits of the first input data and bits of the second input data, in accordance with a control data which is input from outside. The output bit selecting means is still further operable to output Q-bit digital data comprising the values of the selected bits to the output register. This arithmetic unit is suitable for being employed in an image processing system to perform the multiplexing processing or the demultiplexing processing for codes at high speeds.

5. 发明授权

US07676527B2 Processor 有权
标题翻译：处理器
公开(公告)号：US07676527B2
公开(公告)日：2010-03-09
申请号：US10998012
申请日：2004-11-29
申请人： Shunichi Kuromaru , Koji Okamoto , Junji Michiyama
发明人： Shunichi Kuromaru , Koji Okamoto , Junji Michiyama
IPC分类号： G06F7/00
CPC分类号： G06F7/76
摘要： The present invention provides an arithmetic unit comprising an input register for storing externally input digital data as a P-bit digital data, an output register for storing a Q-bit digital data, and an output bit selecting means. The output bit selecting means is operable to receive the P-bit digital data which is output from the input register as a first input data, and the Q-bit digital data which is output from the output register as a second input data. The output big selecting means is further operable to select bits, values of which bits are to be output, among bits of the first input data and bits of the second input data, in accordance with a control data which is input from outside. The output bit selecting means is still further operable to output Q-bit digital data comprising the values of the selected bits to the output register. This arithmetic unit is suitable for being employed in an image processing system to perform the multiplexing processing or the demultiplexing processing for codes at high speeds.
摘要翻译：本发明提供了一种运算单元，包括用于存储外部输入的数字数据作为P位数字数据的输入寄存器，用于存储Q位数字数据的输出寄存器和输出位选择装置。输出位选择装置可用于接收从输入寄存器输出的P位数字数据作为第一输入数据，并将从输出寄存器输出的Q位数字数据作为第二输入数据。输出大选择装置还可用于根据从外部输入的控制数据，在第一输入数据的位和第二输入数据的位中选择要输出哪些位的位。输出位选择装置还可以用于将包括所选位的值的Q位数字数据输出到输出寄存器。该算术单元适合于在图像处理系统中使用以高速执行多路复用处理或多路分解处理。

6. 发明授权

US5430675A An EEPROM Circuit, a memory device having the EEPROM circuit and an IC card having the EEPROM circuit 失效
标题翻译： EEPROM电路，具有EEPROM电路的存储器件和具有EEPROM电路的IC卡
公开(公告)号：US5430675A
公开(公告)日：1995-07-04
申请号：US136308
申请日：1993-10-13
申请人： Shinji Yajima , Junji Michiyama , Nobuyuki Ikeda
发明人： Shinji Yajima , Junji Michiyama , Nobuyuki Ikeda
IPC分类号： G11C16/04 , G11C16/10 , G11C13/00
CPC分类号： G11C16/0433 , G11C16/10
摘要： In an EEPROM, source electrodes S of memory cell transistors MT1 to MTn are grounded, via transistors MG1 to MGn. The source electrodes S are separated from each other so as to maintain the source electrode S of each of the memory cell transistors MT1 to MTn at an open state, even when a leak path is formed by the memory cell transistor MTi in the written state (low threshold voltage). In the EEPROM, an EPROM circuit in which the write operation can be continuously performed without the erase operation can be obtained. Further, an EEPROM circuit having the nonerasable region (the region which functions as the EPROM) and the erasable region (the region which functions as the EEPROM) can be also provided.
摘要翻译：在EEPROM中，存储单元晶体管MT1〜MTn的源极S通过晶体管MG1〜MGn接地。源电极S彼此分离，以便即使当存储单元晶体管MTi在写入状态下形成泄漏路径时，也将存储单元晶体管MT1至MTn的源电极S保持在打开状态（低阈值电压）。在EEPROM中，可以获得其中可以连续执行写入操作而不进行擦除操作的EPROM电路。此外，还可以提供具有不可擦除区域（用作EPROM的区域）和可擦除区域（用作EEPROM的区域）的EEPROM电路。

7. 发明授权

US08811470B2 Integrated circuit for video/audio processing 有权
标题翻译：用于视频/音频处理的集成电路
公开(公告)号：US08811470B2
公开(公告)日：2014-08-19
申请号：US10599494
申请日：2005-04-01
申请人： Kozo Kimura , Tokuzo Kiyohara , Hiroshi Mizuno , Junji Michiyama , Tomohiko Kitamura , Ryoji Yamaguchi , Manabu Kuroda , Nobuhiko Yamada , Hideyuki Ohgose , Akifumi Yamana
发明人： Kozo Kimura , Tokuzo Kiyohara , Hiroshi Mizuno , Junji Michiyama , Tomohiko Kitamura , Ryoji Yamaguchi , Manabu Kuroda , Nobuhiko Yamada , Hideyuki Ohgose , Akifumi Yamana
IPC分类号： H04N7/12
CPC分类号： G06F13/4027 , H04N5/775 , H04N5/781 , H04N5/85 , H04N5/907 , H04N9/7921 , H04N9/8042
摘要： An integrated circuit for video/audio processing in which design resources obtained by development of video/audio devices can also be used for other types of video/audio devices. The integrated circuit includes a microcomputer that includes a CPU, a stream input/output for inputting/outputting a video and audio stream to and from an external device, a media processor that executes the media processing including at least one compressing and decompressing the video and audio stream inputted to the stream input/output, an AV input/output that converts the video and audio stream subjected to the media processing by the media processor into video and audio signals and outputting these signals to the external device. A memory interface controls a data transfer between the microcomputer, the stream input/output, the media processor and the AV input/output and an external memory.
摘要翻译：用于视频/音频处理的集成电路，其中通过开发视频/音频设备获得的设计资源也可以用于其他类型的视频/音频设备。集成电路包括微型计算机，其包括CPU，用于向外部设备输入/输出视频和音频流的流输入/输出，执行媒体处理的媒体处理器，该媒体处理包括至少一个压缩和解压缩视频，以及输入到流输入/输出的音频流，将由媒体处理器进行媒体处理的视频和音频流转换成视频和音频信号并将这些信号输出到外部设备的AV输入/输出。存储器接口控制微机，流输入/输出，媒体处理器和AV输入/输出之间的数据传输以及外部存储器。

8. 发明授权

US06901419B2 Arithmetic unit 有权
标题翻译：算术单位
公开(公告)号：US06901419B2
公开(公告)日：2005-05-31
申请号：US10366355
申请日：2003-02-14
申请人： Shunichi Kuromaru , Koji Okamoto , Junji Michiyama
发明人： Shunichi Kuromaru , Koji Okamoto , Junji Michiyama
IPC分类号： G06F7/76 , G06F7/00
CPC分类号： G06F7/76
摘要： The present invention provides an arithmetic unit comprising an input register for storing externally input digital data as a P-bit digital data, an output register for storing a Q-bit digital data, and an output bit selecting means. The output bit selecting means is operable to receive the P-bit digital data which is output from the input register as a first input data, and the Q-bit digital data which is output from the output register as a second input data. The output big selecting means is further operable to select bits, values of which bits are to be output, among bits of the first input data and bits of the second input data, in accordance with a control data which is input from outside. The output bit selecting means is still further operable to output Q-bit digital data comprising the values of the selected bits to the output register. This arithmetic unit is suitable for being employed in an image processing system to perform the multiplexing processing or the demultiplexing processing for codes at high speeds.
摘要翻译：本发明提供了一种运算单元，包括用于存储外部输入的数字数据作为P位数字数据的输入寄存器，用于存储Q位数字数据的输出寄存器和输出位选择装置。输出位选择装置可用于接收从输入寄存器输出的P位数字数据作为第一输入数据，并将从输出寄存器输出的Q位数字数据作为第二输入数据。输出大选择装置还可用于根据从外部输入的控制数据，在第一输入数据的位和第二输入数据的位中选择要输出哪些位的位。输出位选择装置还可以用于将包括所选位的值的Q位数字数据输出到输出寄存器。该算术单元适合于在图像处理系统中使用以高速执行多路复用处理或多路分解处理。

9. 发明授权

US06535899B1 Arithmetic device 有权
标题翻译：算术设备
公开(公告)号：US06535899B1
公开(公告)日：2003-03-18
申请号：US09445059
申请日：2000-02-16
申请人： Shunichi Kuromaru , Koji Okamoto , Junji Michiyama
发明人： Shunichi Kuromaru , Koji Okamoto , Junji Michiyama
IPC分类号： G06F700
CPC分类号： G06F7/76
摘要： The present invention provides an arithmetic unit comprising an input register for storing externally input digital data as a P-bit digital data, an output register for storing a Q-bit digital data, and an output bit selecting means. The output bit selecting means is operable to receive the P-bit digital data which is output from the input register as a first input data, and the Q-bit digital data which is output from the output register as a second input data. The output big selecting means is further operable to select bits, values of which bits are to be output, among bits of the first input data and bits of the second input data, in accordance with a control data which is input from outside. The output bit selecting means is still further operable to output Q-bit digital data comprising the values of the selected bits to the output register. This arithmetic unit is suitable for being employed in an image processing system to perform the multiplexing processing or the demultiplexing processing for codes at high speeds.
摘要翻译：本发明提供了一种运算单元，包括用于存储外部输入的数字数据作为P位数字数据的输入寄存器，用于存储Q位数字数据的输出寄存器和输出位选择装置。输出位选择装置可用于接收从输入寄存器输出的P位数字数据作为第一输入数据，并将从输出寄存器输出的Q位数字数据作为第二输入数据。输出大选择装置还可用于根据从外部输入的控制数据，在第一输入数据的位和第二输入数据的位中选择要输出哪些位的位。输出位选择装置还可以用于将包括所选位的值的Q位数字数据输出到输出寄存器。该算术单元适合于在图像处理系统中使用以高速执行多路复用处理或多路分解处理。

10. 发明授权

US08074139B2 Communication method and communication device 有权
标题翻译：通讯方式及通讯装置
公开(公告)号：US08074139B2
公开(公告)日：2011-12-06
申请号：US11819290
申请日：2007-06-26
申请人： Tadanori Tezuka , Tsutomu Sekibe , Shunichi Kuromaru , Junji Michiyama , Hiroshi Nakamura , Masaaki Kondo , Takashi Nanya , Masashi Imai , Nassu Tomoyuki Bogdan
发明人： Tadanori Tezuka , Tsutomu Sekibe , Shunichi Kuromaru , Junji Michiyama , Hiroshi Nakamura , Masaaki Kondo , Takashi Nanya , Masashi Imai , Nassu Tomoyuki Bogdan
IPC分类号： H04L1/18
CPC分类号： H04L1/0025 , H04L51/063 , H04L67/32
摘要： A request change unit outputs a command as a request under control of a judgment control unit. A response condition determination unit determines a condition that is to be matched by a correct response which is to be returned from the other device-in-communication in reply to the command if the other device-in-communication operates in conformity with a protocol. A check unit checks a response received from the other device-in-communication in reply to the command, against the condition. If the received response does not match the condition but is correctable to match the condition as a result of the check, a response correction unit corrects the received response to match the condition under control of the judgment control unit.
摘要翻译：请求改变单元在判断控制单元的控制下输出作为请求的命令。响应条件确定单元如果其他设备在通信中的协议一致地操作，则确定要从其他设备在通信中返回的正确响应匹配的条件。检查单元根据该条件检查从其他通信设备接收的响应于该命令的响应。如果接收到的响应与条件不匹配，但是作为检查结果可以校正以匹配条件，则响应校正单元校正所接收的响应以与判断控制单元的控制下的条件相匹配。

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