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1. 发明授权

US06191974B1 Nonvolatile semiconductor memory 失效
标题翻译：非易失性半导体存储器
公开(公告)号：US06191974B1
公开(公告)日：2001-02-20
申请号：US09321092
申请日：1999-05-27
申请人： Yoichi Nishida , Tomonori Kataoka , Ikuo Fuchigami , Tomoo Kimura , Junji Michiyama , Satoshi Koutaka
发明人： Yoichi Nishida , Tomonori Kataoka , Ikuo Fuchigami , Tomoo Kimura , Junji Michiyama , Satoshi Koutaka
IPC分类号： G11C1604
CPC分类号： G11C16/32
摘要： There is provided a nonvolatile semiconductor memory which is capable of operating stably and performing high-speed access operation. A timing generation means 51 for generating timing signals which make a memory core unit 4 perform access operation uses first and second clocks of the same cycle and different phases. The timing generation means 51 generates timing signals for at least one first-half event among a plurality of read access events, according to the first clock, the phase of which precedes a phases of the second clock, and generates timing signals used for processing the remaining events, according to the second clock.
摘要翻译：提供了能够稳定运行并执行高速存取操作的非易失性半导体存储器。用于产生使存储器核心单元4执行访问操作的定时信号的定时产生装置51使用相同周期和不同相位的第一和第二时钟。定时产生装置51根据第一时钟产生多个读取访问事件中的至少一个前半个事件的定时信号，该第一时钟的相位在第二时钟的相位之前，并产生用于处理第二时钟的定时信号剩下的事件，按照第二个时钟。

2. 发明授权

US06172917B2 Semiconductor memory device and regulator 有权
标题翻译：半导体存储器件和调节器
公开(公告)号：US06172917B2
公开(公告)日：2001-01-09
申请号：US09309581
申请日：1999-05-11
申请人： Tomonori Kataoka , Yoichi Nishida , Ikuo Fuchigami , Tomoo Kimura , Junji Michiyama
发明人： Tomonori Kataoka , Yoichi Nishida , Ikuo Fuchigami , Tomoo Kimura , Junji Michiyama
IPC分类号： G11C700
CPC分类号： G11C16/3459 , G11C16/10 , G11C16/3454
摘要： A semiconductor memory device having nonvolatile memory cells arranged in matrix comprises and bit lines connected to drains of the memory cells. Latches provided for the respective bit lines or in the ratio of one latch to a number of bit lines, as are; transfer gates for electrically separating the respective latches from the bit lines. The device also having bit line voltage detection circuits for detecting voltages of the respective bit lines and latch reset circuits for inverting data stored in the respective latches in accordance with the outputs from the bit line voltage detection circuits. Therefore, data stored in each latch can be rewritten even by a very small memory cell current, resulting in stable program verify.
摘要翻译：具有排列成矩阵状的非易失性存储单元的半导体存储器件和连接到存储单元的漏极的位线。针对各个位线提供的锁存器或一个锁存器与多个位线的比率一样; 传输门，用于将各个锁存器与位线电分离。该装置还具有位线电压检测电路，用于根据位线电压检测电路的输出检测各位线的电压和锁存复位电路，用于反相存储在各个锁存器中的数据。因此，即使通过非常小的存储单元电流，存储在每个锁存器中的数据也可以被重写，从而导致稳定的程序验证。

3. 发明授权

US07117462B2 Circuit operation verifying method and apparatus 有权
标题翻译：电路运行验证方法和装置
公开(公告)号：US07117462B2
公开(公告)日：2006-10-03
申请号：US09964515
申请日：2001-09-28
申请人： Tomoo Kimura , Tomonori Kataoka , Yoichi Nishida , Ikuo Fuchigami , Ken Kawai , Yasuhiro Ishiyama
发明人： Tomoo Kimura , Tomonori Kataoka , Yoichi Nishida , Ikuo Fuchigami , Ken Kawai , Yasuhiro Ishiyama
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： In the circuit operation verifying method, initialization includes inputting circuit diagram data (a net list), specification information on respective circuit elements, and input data representing waveforms with time of voltages or currents used for operation simulation, and storing the circuit diagram data to memory. Operation of a semiconductor circuit to be verified is simulated using the circuit diagram data and the input data, and momentary voltage/current values at input terminals and the like of the circuit elements are stored in the memory. During the operation simulation, whether or not the circuit elements satisfy their voltage/current specifications and time specifications are concurrently verified based on the voltage/current values stored in the memory.
摘要翻译：在电路操作验证方法中，初始化包括输入电路图数据（网表），各个电路元件的指定信息和表示用于操作模拟的电压或电流的时间的波形的输入数据，以及将电路图数据存储到存储器。使用电路图数据和输入数据来模拟要验证的半导体电路的操作，并且电路元件的输入端等处的瞬时电压/电流值被存储在存储器中。在操作模拟期间，电路元件是否满足其电压/电流规范，并且基于存储在存储器中的电压/电流值同时验证时间规格。

4. 发明授权

US06219286B1 Semiconductor memory having reduced time for writing defective information 有权
标题翻译：半导体存储器具有减少写入缺陷信息的时间
公开(公告)号：US06219286B1
公开(公告)日：2001-04-17
申请号：US09586992
申请日：2000-06-05
申请人： Ikuo Fuchigami , Tomonori Kataoka , Youichi Nishida , Tomoo Kimura , Ken Kawai
发明人： Ikuo Fuchigami , Tomonori Kataoka , Youichi Nishida , Tomoo Kimura , Ken Kawai
IPC分类号： G11C700
CPC分类号： G11C29/848
摘要： The present invention provides a semiconductor memory which can reduce the area of a circuit for replacing defective memory cells with redundant memory cells as well as reduce the time for writing defect information. The semiconductor memory of the present invention comprises a memory cell array 1 comprising (n+1) (n is a positive integer) word lines, a register unit 4 holding an encoded defect address for specifying a defective word line, a defect address decoder 31 for decoding the defect address from the register unit 4 to specify the defective word line, selection means S1˜Sn for selecting, for the i-th (1≦i≦n) output signal line of a row decoder 2, one of the i-th and i+1-th word lines and connecting the selected word line to the i-th output signal line, and control means C1˜Cn each controlling corresponding one of the selection means S1˜Sn on the basis of an output of the defect address decoder 31 so as to select, for the output signal line of the row decoder 2, one of the word lines except the defective word line in accordance with the arrangement order.
摘要翻译：本发明提供一种半导体存储器，其可以减少用于用冗余存储器单元替换有缺陷的存储单元的电路的面积，并且减少写入缺陷信息的时间。本发明的半导体存储器包括存储单元阵列1，其包括（n + 1）（n是正整数）字线，保持用于指定缺陷字线的编码缺陷地址的寄存器单元4，缺陷地址解码器31 为了从寄存器单元4解码缺陷地址以指定缺陷字线，对于行解码器2的第i（1 <= i <= n）个输出信号线，选择装置S1〜Sn选择第i个和第i个第1个字线并将选择的字线连接到第i个输出信号线，以及控制装置C1〜Cn，每个控制装置C1〜Cn根据输出对于行解码器2的输出信号线，根据排列顺序选择除缺陷字线以外的字线之一。

5. 发明授权

US06469937B2 Current sense amplifier circuit 有权
公开(公告)号：US06469937B2
公开(公告)日：2002-10-22
申请号：US10040788
申请日：2002-01-09
申请人： Ikuo Fuchigami , Tomonori Kataoka , Youichi Nishida , Tomoo Kimura , Jyunji Michiyama , Satoshi Kohtaka
发明人： Ikuo Fuchigami , Tomonori Kataoka , Youichi Nishida , Tomoo Kimura , Jyunji Michiyama , Satoshi Kohtaka
IPC分类号： G11C1606
CPC分类号： G11C11/5642 , G11C7/06 , G11C7/062 , G11C7/067 , G11C11/56 , G11C11/5621 , G11C16/28 , G11C2207/063 , G11C2211/5634
摘要： A current sense amplifier circuit is provided with a reference current generator for generating a reference current according to the characteristics of a memory cell, and a current comparator, and the current comparator compares the memory cell current with the reference current. Thereby, the range of the operating power supply voltage is increased. Further, a current sense amplifier circuit is provided with plural sets of reference current generators and current comparators, and the reference current generators generate reference currents of different amounts corresponding to plural states the memory cell can take, and the current comparators compare the respective reference currents with the memory cell current. Therefore, it is possible to detect the current in the memory cell that is set in multiple states.

6. 发明授权

US06351416B2 Current sense amplifier circuit 失效
公开(公告)号：US06351416B2
公开(公告)日：2002-02-26
申请号：US09796806
申请日：2001-03-02
申请人： Ikuo Fuchigami , Tomonori Kataoka , Youichi Nishida , Tomoo Kimura , Jyunji Michiyama , Satoshi Kohtaka
发明人： Ikuo Fuchigami , Tomonori Kataoka , Youichi Nishida , Tomoo Kimura , Jyunji Michiyama , Satoshi Kohtaka
IPC分类号： G11C1606
CPC分类号： G11C11/5642 , G11C7/06 , G11C7/062 , G11C7/067 , G11C11/56 , G11C11/5621 , G11C16/28 , G11C2207/063 , G11C2211/5634
摘要： A current sense amplifier circuit is provided with a reference current generator for generating a reference current according to the characteristics of a memory cell, and a current comparator, and the current comparator compares the memory cell current with the reference current. Thereby, the range of the operating power supply voltage is increased. Further, a current sense amplifier circuit is provided with plural sets of reference current generators and current comparators, and the reference current generators generate reference currents of different amounts corresponding to plural states the memory cell can take, and the current comparators compare the respective reference currents with the memory cell current. Therefore, it is possible to detect the current in the memory cell that is set in multiple states.

7. 发明授权

US06208124B1 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US06208124B1
公开(公告)日：2001-03-27
申请号：US09586993
申请日：2000-06-05
申请人： Ikuo Fuchigami , Tomonori Kataoka , Youichi Nishida , Tomoo Kimura
发明人： Ikuo Fuchigami , Tomonori Kataoka , Youichi Nishida , Tomoo Kimura
IPC分类号： G05F140
CPC分类号： G05F1/565 , Y10T307/25
摘要： A semiconductor integrated circuit includes a booster for boosting a power supply voltage, and outputting the boosted voltage; an output circuit being supplied with the boosted voltage, and generating an output voltage from the boosted voltage; a reference voltage generator being supplied with the power supply voltage, and generating a reference voltage from the power supply voltage; a voltage divider being supplied with the output voltage from the output circuit, and dividing the output voltage with a predetermined voltage ratio; and a differential amplifier being supplied with the reference voltage and the divided voltage, and controlling the output circuit by supplying the output circuit with a voltage obtained by performing differential amplification on the reference voltage and the divided voltage according to the power supply voltage, thereby maintaining the output voltage from the output circuit at a predetermined voltage. In this circuit, since the reference voltage generator and the differential amplifier are operated with the power supply voltage, it is not necessary to supply the boosted voltage to them, whereby the output current from the booster is reduced. Therefore, undesired reduction in the boosted voltage due to an increase in the output current is suppressed. As the result, the capacitance used in the booster is reduced, and the area of the semiconductor integrated circuit is reduced.
摘要翻译：半导体集成电路包括用于升压电源电压并输出升压电压的升压器; 输出电路被提供升压电压，并从升压电压产生输出电压; 参考电压发生器被提供有电源电压，并从电源电压产生参考电压; 分压器从输出电路提供输出电压，并以预定的电压比划分输出电压; 并且差分放大器被提供有参考电压和分压，并且通过向输出电路提供根据电源电压对参考电压和分压进行差分放大而获得的电压来控制输出电路，从而保持在预定电压下来自输出电路的输出电压。在该电路中，由于参考电压发生器和差分放大器以电源电压工作，所以不需要向其提供升压电压，从而降低了来自升压器的输出电流。因此，抑制了由于输出电流的增加引起的升压电压的不希望的降低。结果，减小了增强器中使用的电容，并且减小了半导体集成电路的面积。

8. 发明申请

US20050088324A1 Device for arithmetic decoding/encoding, and device using the same 审中-公开
标题翻译：用于算术解码/编码的装置，以及使用它的装置
公开(公告)号：US20050088324A1
公开(公告)日：2005-04-28
申请号：US10968068
申请日：2004-10-20
申请人： Ikuo Fuchigami , Tomonori Kataoka , Hiroaki Toida , Hideshi Nishida
发明人： Ikuo Fuchigami , Tomonori Kataoka , Hiroaki Toida , Hideshi Nishida
IPC分类号： G06T9/00 , H03M7/40 , H04N19/00 , H04N19/102 , H04N19/13 , H04N19/134 , H04N19/169 , H04N19/196 , H04N19/436 , H04N19/91 , H03M7/00
CPC分类号： H03M7/4006 , H04N19/42 , H04N19/436 , H04N19/91
摘要： An arithmetic decoding device comprises an adaptive arithmetic decoding unit, a context calculating unit, and a decoding control unit. The adaptive arithmetic decoding unit includes an arithmetic decoding unit, a symbol appearing probability control unit, and a probability state storing unit. When a variable-length encoded code (VLC) is inputted, the context calculating unit generates a context number from a classification and a decoded bit number of a syntax element of the inputted code, and outputs the context number to the adaptive arithmetic decoding unit. The adaptive arithmetic decoding unit renews a symbol appearing probability based on the frequency of appearance of the symbol, thereby arithmetic-decoding the inputted code (VLC), and feeding output data (OD). The decoding control unit controls the whole arithmetic decoding device.
摘要翻译：算术解码装置包括自适应算术解码单元，上下文计算单元和解码控制单元。自适应算术解码单元包括算术解码单元，符号出现概率控制单元和概率状态存储单元。当输入可变长度编码代码（VLC）时，上下文计算单元根据输入代码的语法元素的分类和解码比特数生成上下文编号，并将上下文编号输出到自适应算术解码单元。自适应算术解码单元基于符号的出现频率更新符号出现概率，从而对输入的代码（VLC）进行算术解码，并提供输出数据（OD）。解码控制单元控制整个算术解码装置。

9. 发明授权

US07133658B2 Method and apparatus for image processing 有权
标题翻译：图像处理方法和装置
公开(公告)号：US07133658B2
公开(公告)日：2006-11-07
申请号：US10698435
申请日：2003-11-03
申请人： Kazuyuki Imagawa , Katsuhiro Iwasa , Takaaki Nishi , Eiji Fukumiya , Hideaki Matsuo , Tomonori Kataoka , Satoshi Kajita , Ikuo Fuchigami
发明人： Kazuyuki Imagawa , Katsuhiro Iwasa , Takaaki Nishi , Eiji Fukumiya , Hideaki Matsuo , Tomonori Kataoka , Satoshi Kajita , Ikuo Fuchigami
IPC分类号： H04Q7/20
CPC分类号： G06T11/60
摘要： The position of a body part area for a personal image in an input image is detected. According to the position of the detected body part area, the position of the origin of a coordinate system for an ornament image is defined. Based on the position of the defined origin, an ornament-arranged input image is outputted. When the personal image moves in the input image, the ornament image also moves by following the movement of the personal image. Even when both the personal image and ornament image move, the ornament image can be made not to interfere with the personal image. Therefore, the personal image can be clearly displayed. Moreover, the input image can be made to look more interesting by synchronizing the movement of the ornament image with the movement of the personal image.
摘要翻译：检测输入图像中的个人图像的身体部位面积的位置。根据检测到的身体部位的位置，定义装饰图像的坐标系的原点的位置。基于定义的原点的位置，输出装饰布置的输入图像。当个人图像在输入图像中移动时，装饰图像也随着个人图像的移动而移动。即使个人图像和装饰图像都移动，装饰图像也可以不影响个人图像。因此，可以清楚地显示个人图像。此外，通过使装饰图像的移动与个人图像的移动同步，可以使输入图像看起来更有趣。

10. 发明授权

US10230991B2 Signal-processing apparatus including a second processor that, after receiving an instruction from a first processor, independantly controls a second data processing unit without further instrcuction from the first processor 有权
公开(公告)号：US10230991B2
公开(公告)日：2019-03-12
申请号：US12179873
申请日：2008-07-25
申请人： Tomonori Kataoka , Hideshi Nishida , Kouzou Kimura , Nobuo Higaki , Tokuzo Kiyohara
发明人： Tomonori Kataoka , Hideshi Nishida , Kouzou Kimura , Nobuo Higaki , Tokuzo Kiyohara
IPC分类号： G06F9/38 , H04N19/86 , H04N19/61 , H04N19/44 , H04N19/42 , H04N19/436 , H04N19/523
摘要： A signal-processing apparatus includes an instruction-parallel processor, a first data-parallel processor, a second data-parallel processor, and a motion detection unit, a de-blocking filtering unit and a variable-length coding/decoding unit which are dedicated hardware. With this structure, during signal processing of an image compression and decompression algorithm needing a large amount of processing, the load is distributed between software and hardware, so that the signal-processing apparatus can realize high processing capability and flexibility.

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