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1. 发明授权

US07117462B2 Circuit operation verifying method and apparatus 有权
标题翻译：电路运行验证方法和装置
公开(公告)号：US07117462B2
公开(公告)日：2006-10-03
申请号：US09964515
申请日：2001-09-28
申请人： Tomoo Kimura , Tomonori Kataoka , Yoichi Nishida , Ikuo Fuchigami , Ken Kawai , Yasuhiro Ishiyama
发明人： Tomoo Kimura , Tomonori Kataoka , Yoichi Nishida , Ikuo Fuchigami , Ken Kawai , Yasuhiro Ishiyama
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： In the circuit operation verifying method, initialization includes inputting circuit diagram data (a net list), specification information on respective circuit elements, and input data representing waveforms with time of voltages or currents used for operation simulation, and storing the circuit diagram data to memory. Operation of a semiconductor circuit to be verified is simulated using the circuit diagram data and the input data, and momentary voltage/current values at input terminals and the like of the circuit elements are stored in the memory. During the operation simulation, whether or not the circuit elements satisfy their voltage/current specifications and time specifications are concurrently verified based on the voltage/current values stored in the memory.
摘要翻译：在电路操作验证方法中，初始化包括输入电路图数据（网表），各个电路元件的指定信息和表示用于操作模拟的电压或电流的时间的波形的输入数据，以及将电路图数据存储到存储器。使用电路图数据和输入数据来模拟要验证的半导体电路的操作，并且电路元件的输入端等处的瞬时电压/电流值被存储在存储器中。在操作模拟期间，电路元件是否满足其电压/电流规范，并且基于存储在存储器中的电压/电流值同时验证时间规格。

2. 发明申请

US20060176100A1 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US20060176100A1
公开(公告)日：2006-08-10
申请号：US11302372
申请日：2005-12-14
申请人： Tomoo Kimura
发明人： Tomoo Kimura
IPC分类号： H03K3/01
CPC分类号： G06F1/3203 , H03K19/0008
摘要： A semiconductor integrated circuit including: a circuit block including a MOS transistor that includes a bias input terminal, a source, and a substrate, in which the bias voltage is applied to the MOS transistor at a position of at least one of the source and the substrate through the bias input terminal; a setting unit operable to set up applying timing and releasing timing at which the bias voltage is applied to and released from the MOS transistor; and a bias voltage-applying unit operable to apply the bias voltage to the MOS transistor at the applying timing and the releasing timing. In the semiconductor integrated circuit, the setting unit sets up, as the releasing timing, timing prior to activation timing by a predetermined time period. An operation-requesting signal, to be sent out to the circuit block by the setting unit, is activated at the moment of the activation timing.
摘要翻译：一种半导体集成电路，包括：包括MOS晶体管的电路块，所述MOS晶体管包括偏置输入端子，源极和基板，其中所述偏置电压施加到所述MOS晶体管的至少一个源极和基板通过偏置输入端; 设置单元，用于设置施加定时并释放偏置电压施加到MOS晶体管并从MOS晶体管释放的定时; 以及偏压施加单元，其可操作以在施加定时和释放定时将偏置电压施加到MOS晶体管。在半导体集成电路中，设置单元将激活定时之前的定时设置为释放定时预定时间段。在激活定时的时候激活由设定单元发送到电路块的操作请求信号。

3. 发明申请

US20050125642A1 Dynamically reconfigurable logic circuit device, interrupt control method, and semi-conductor integrated circuit 审中-公开
标题翻译：动态可重构逻辑电路器件，中断控制方法和半导体集成电路
公开(公告)号：US20050125642A1
公开(公告)日：2005-06-09
申请号：US11002059
申请日：2004-12-03
申请人： Tomoo Kimura
发明人： Tomoo Kimura
IPC分类号： G06F15/177 , G06F15/00 , G06F15/80 , H03K17/00 , H03K19/177
CPC分类号： G06F15/7867 , G06F15/177
摘要： A dynamically reconfigurable logic circuit device includes a plurality of dynamically reconfigurable processor units (DRPU) arranged in array, and a plurality of dynamically connecting units (DCU). The dynamically connecting units interconnect inputs and outputs of the dynamically reconfigurable processor units. Each of the dynamically reconfigurable processor units includes a plurality of arithmetic processing configurations, a plurality of input data storage units, and a plurality of output data storage units. The arithmetic processing configurations, input data storage units, and output data storage units are both selected and set up in accordance with an interrupting signal from an interrupt controller. Similarly, the interconnection of the dynamically reconfigurable processor units through the dynamically connecting units is performed in accordance with the interrupting signal. The above structure is operable to change input data as well as the arithmetic processing configurations upon the issuance of a request for interrupt from a CPU, and to change the entire logic circuit configuration. As a result, time-division multiplexing is achievable.
摘要翻译：动态可重构逻辑电路装置包括排列成阵列的多个动态可重构处理器单元（DRPU）和多个动态连接单元（DCU）。动态连接单元互连动态可重配置处理器单元的输入和输出。每个动态可重构处理器单元包括多个算术处理配置，多个输入数据存储单元和多个输出数据存储单元。算术处理配置，输入数据存储单元和输出数据存储单元都是根据来自中断控制器的中断信号来选择和设置的。类似地，根据中断信号执行通过动态连接单元的动态可重配置处理器单元的互连。上述结构可用于在从CPU发出中断请求时改变输入数据以及算术处理配置，并且改变整个逻辑电路配置。结果，可以实现时分复用。

4. 发明授权

US06191974B1 Nonvolatile semiconductor memory 失效
标题翻译：非易失性半导体存储器
公开(公告)号：US06191974B1
公开(公告)日：2001-02-20
申请号：US09321092
申请日：1999-05-27
申请人： Yoichi Nishida , Tomonori Kataoka , Ikuo Fuchigami , Tomoo Kimura , Junji Michiyama , Satoshi Koutaka
发明人： Yoichi Nishida , Tomonori Kataoka , Ikuo Fuchigami , Tomoo Kimura , Junji Michiyama , Satoshi Koutaka
IPC分类号： G11C1604
CPC分类号： G11C16/32
摘要： There is provided a nonvolatile semiconductor memory which is capable of operating stably and performing high-speed access operation. A timing generation means 51 for generating timing signals which make a memory core unit 4 perform access operation uses first and second clocks of the same cycle and different phases. The timing generation means 51 generates timing signals for at least one first-half event among a plurality of read access events, according to the first clock, the phase of which precedes a phases of the second clock, and generates timing signals used for processing the remaining events, according to the second clock.
摘要翻译：提供了能够稳定运行并执行高速存取操作的非易失性半导体存储器。用于产生使存储器核心单元4执行访问操作的定时信号的定时产生装置51使用相同周期和不同相位的第一和第二时钟。定时产生装置51根据第一时钟产生多个读取访问事件中的至少一个前半个事件的定时信号，该第一时钟的相位在第二时钟的相位之前，并产生用于处理第二时钟的定时信号剩下的事件，按照第二个时钟。

5. 发明申请

US20100157093A1 IMAGING DEVICE, INTEGRATED CIRCUIT, AND IMAGING METHOD 有权
标题翻译：成像装置，集成电路和成像方法
公开(公告)号：US20100157093A1
公开(公告)日：2010-06-24
申请号：US12663948
申请日：2008-10-23
申请人： Ryuji Fuchikami , Ikuo Fuchigami , Tomoo Kimura
发明人： Ryuji Fuchikami , Ikuo Fuchigami , Tomoo Kimura
IPC分类号： H04N9/12 , H04N7/12
CPC分类号： H04N5/2357 , H04N19/105 , H04N19/172 , H04N19/436 , H04N19/51 , H04N19/573 , H04N19/61 , H04N19/85
摘要： A frame brightness detecting unit 15 detects a frame brightness value of each of a plurality of image frames. A flicker spectrum detecting unit 16 detects, from the frame brightness values of 512 frames, spectrum values at frequencies, such as 100 Hz, 200 Hz, and 300 Hz. A brightness estimating unit 17 estimates a brightens value of a light source from the spectrum values. An encoding unit 18 uses a reciprocal of the estimated brightens value to determine a reference frame. The encoding unit 18 also uses the reciprocal in an evaluation function for motion vector estimation. The image frame is encoded using the motion vector.
摘要翻译：帧亮度检测单元15检测多个图像帧中的每一个的帧亮度值。闪烁频谱检测单元16从512帧的帧亮度值检测频率如100Hz，200Hz和300Hz的频谱值。亮度估计单元17从光谱值估计光源的增亮值。编码单元18使用估计亮度值的倒数来确定参考帧。编码单元18还在用于运动矢量估计的评估函数中使用倒数。使用运动矢量对图像帧进行编码。

6. 发明申请

US20100131791A1 SIGNAL PROCESSING APPARATUS AND SIGNAL PROCESSING SYSTEM 审中-公开
标题翻译：信号处理装置和信号处理系统
公开(公告)号：US20100131791A1
公开(公告)日：2010-05-27
申请号：US12595994
申请日：2008-04-16
申请人： Tomoo Kimura
发明人： Tomoo Kimura
IPC分类号： G06F1/28 , G06F1/08
CPC分类号： G06F1/3203 , G06F1/08 , G06F1/324 , G06F1/3296 , G06F9/5094 , Y02D10/126 , Y02D10/172 , Y02D10/22
摘要： A signal processing apparatus includes a signal processor a processing amount predictor for predicting a processing amount in the signal processor based on the signal data and outputting a processing amount prediction value, a processing amount observer for observing a processing amount of the signal processing executed by the signal processor and outputting a process completion value, and a control value decision section for deciding a voltage of the power and a frequency of the clock, which are supplied to the signal processor, based on the processing amount prediction value, the process completion value, and elapsed information indicating an elapsed time from a start of the signal processing. The power supplier supplies the power whose voltage is decided by the control value decision section to the signal processor, and the clock supplier supplies the clock whose frequency is decided by the control value decision section to the signal processor.
摘要翻译：一种信号处理装置，包括信号处理器，处理量预测器，用于根据信号数据预测信号处理器中的处理量，并输出处理量预测值;处理量观察器，用于观察由所述信号处理执行的信号处理的处理量信号处理器并输出处理完成值;以及控制值决定部，用于基于处理量预测值，处理完成值，确定提供给信号处理器的功率的电压和时钟的频率，以及表示从信号处理开始起经过的时间的经过信息。电源将由控制值决定部决定的电力供给信号处理器，时钟供给器将频率由控制值决定部决定的时钟供给信号处理部。

7. 发明授权

US08818127B2 Image processing apparatus and image processing method 有权
标题翻译：图像处理装置和图像处理方法
公开(公告)号：US08818127B2
公开(公告)日：2014-08-26
申请号：US13819766
申请日：2012-03-23
申请人： Keisuke Hayata , Hiroto Tomita , Tomoo Kimura
发明人： Keisuke Hayata , Hiroto Tomita , Tomoo Kimura
IPC分类号： G06K9/40 , H04N5/232 , G06T5/00 , H04N13/00 , G06T5/50 , G06K9/36 , H04N13/02 , H04N5/235
CPC分类号： G06T5/50 , G06T5/002 , G06T2207/10012 , G06T2207/20192 , G06T2207/20221 , H04N5/23229 , H04N5/2355 , H04N13/00 , H04N13/239
摘要： The picture quality of captured images can be improved with the degradation of clearness of image-captured object boundaries suppressed. An image processing apparatus (100) comprises: an image/distance acquiring unit (200) that acquires corresponding pixel pairs between left-eye and right-eye images, its depth information and its matching scores; a weight information calculating unit (300) that determines, for each of the pixel pairs, a weight of each of the pixels in a certain area including, as pixels of interest, the pixel pair on the basis of the depth information and the matching scores; and a pixel value superimposing unit (400) that applies, for each of the pixel pairs, the weight to the pixel values in the aforementioned certain area, thereby performing a smoothing process in at least one of the two images and that superimposes the two images using the values obtained by the smoothing process.
摘要翻译：捕获的图像的图像质量可以随着图像捕获对象边界的清晰度的降低而得到改善。一种图像处理装置（100）包括：图像/距离获取单元（200），其获取左眼图像和右眼图像之间的对应像素对，其深度信息及其匹配分数; 权重信息计算单元，对于每个所述像素对，基于所述深度信息和所述匹配分数，确定所述像素对中的每个所述像素的权重，所述特定区域包括作为所述像素的像素 ; 以及对于每个像素对对上述某个区域中的像素值应用权重的像素值叠加单元（400），从而在两个图像中的至少一个中执行平滑处理，并且将两个图像使用通过平滑处理获得的值。

8. 发明授权

US08780990B2 Imaging device for motion vector estimation using images captured at a high frame rate with blur detection and method and integrated circuit performing the same 失效
标题翻译：使用具有模糊检测的高帧速率拍摄的图像进行运动矢量估计的成像装置和执行相同方法的集成电路
公开(公告)号：US08780990B2
公开(公告)日：2014-07-15
申请号：US13140069
申请日：2009-11-12
申请人： Ryuji Fuchikami , Kenji Shimizu , Tomoo Kimura
发明人： Ryuji Fuchikami , Kenji Shimizu , Tomoo Kimura
IPC分类号： H04N7/12 , H04N5/272 , H04N7/18
CPC分类号： H04N7/12 , H04N5/272 , H04N7/0127 , H04N7/014 , H04N7/188 , H04N19/132 , H04N19/513 , H04N19/577 , H04N19/587
摘要： An imaging device includes a frame rate conversion unit synthesizing images captured at a second frame rate higher than a first frame rate to convert the images into a synthesized image having the first frame and a motion estimation unit performing motion estimation between consecutive frames of the images captured at the second frame. The imaging device also includes a motion vector synthesis unit synthesizing motion vectors having the second frame rate, to generate a synthesized motion vector of a target macroblock in the synthesized image, a motion blur amount determination unit counting, in an area surrounding the target macroblock, the number of macroblocks having the same synthesized motion vector as the target macroblock and comparing a value derived from the number of counted macroblocks with a threshold value, and a motion vector selection unit selecting the synthesized motion vector when the derived value determined to exceed the threshold value.
摘要翻译：一种成像装置包括帧速率转换单元，合成以高于第一帧速率的第二帧速率拍摄的图像，以将图像转换成具有第一帧的合成图像，以及运动估计单元，在拍摄的图像的连续帧之间执行运动估计在第二帧。成像装置还包括合成具有第二帧速率的运动矢量的运动矢量合成单元，以生成合成图像中的目标宏块的合成运动矢量;运动模糊量确定单元，计算在目标宏块周围的区域，具有与目标宏块相同的合成运动矢量的宏块的数量，并将从所计数的宏块的数量导出的值与阈值进行比较;以及运动矢量选择单元，当所导出的值被确定为超过阈值时，选择合成的运动矢量值。

9. 发明授权

US08493405B2 Image control device and image display system for generating an image to be displayed from received imaged data, generating display information based on the received image data and outputting the image and the display information to a display 有权
标题翻译：图像控制装置和图像显示系统，用于从接收到的成像数据生成要显示的图像，基于接收的图像数据生成显示信息，并将图像和显示信息输出到显示器
公开(公告)号：US08493405B2
公开(公告)日：2013-07-23
申请号：US11802188
申请日：2007-05-21
申请人： Tomoo Kimura , Ryouta Hata
发明人： Tomoo Kimura , Ryouta Hata
IPC分类号： G09G5/00 , G06T11/60 , G06T15/30 , G06T11/40
CPC分类号： G06T11/60 , G06T11/40 , G06T15/30 , G09G3/3648 , G09G5/397 , G09G2320/0247 , G09G2330/021 , G09G2330/08 , G09G2340/02 , H04N19/42 , H04N19/423 , H04N19/44 , H04N19/89 , H04N19/91
摘要： An image control device, which achieves energy saving effects without degradation of an image to be displayed, even if image data includes a fault, is configured to decode received image data into an image, generate display information based on the received image data, and output a decoded image and display information. The image control device receives image data, detects errors from the image data. For each error detected, the image control device specifies a fault image region containing an error from an entire image region of the image data, and inhibits use of the fault image region for generating display information that defines an image display condition according to which the display device performs the image display.
摘要翻译：即使图像数据包括故障，即使图像数据包括故障也能够实现节能效果而不降低要显示的图像的图像控制装置被配置为将接收到的图像数据解码为图像，基于接收到的图像数据生成显示信息，并且输出解码图像和显示信息。图像控制装置接收图像数据，从图像数据检测错误。对于检测到的每个错误，图像控制装置从图像数据的整个图像区域指定包含错误的故障图像区域，并且禁止使用故障图像区域来产生定义图像显示条件的显示信息，设备执行图像显示。

10. 发明授权

US08144213B2 Imaging device, integrated circuit, and imaging method for encoding image frames based on detected flicker of a light source 有权
标题翻译：基于检测到的光源的闪烁来对图像帧进行编码的成像装置，集成电路和成像方法
公开(公告)号：US08144213B2
公开(公告)日：2012-03-27
申请号：US12663948
申请日：2008-10-23
申请人： Ryuji Fuchikami , Ikuo Fuchigami , Tomoo Kimura
发明人： Ryuji Fuchikami , Ikuo Fuchigami , Tomoo Kimura
IPC分类号： H04N9/73
CPC分类号： H04N5/2357 , H04N19/105 , H04N19/172 , H04N19/436 , H04N19/51 , H04N19/573 , H04N19/61 , H04N19/85
摘要： A frame brightness detecting unit 15 detects a frame brightness value of each of a plurality of image frames. A flicker spectrum detecting unit 16 detects, from the frame brightness values of 512 frames, spectrum values at frequencies, such as 100 Hz, 200 Hz, and 300 Hz. A brightness estimating unit 17 estimates a brightens value of a light source from the spectrum values. An encoding unit 18 uses a reciprocal of the estimated brightens value to determine a reference frame. The encoding unit 18 also uses the reciprocal in an evaluation function for motion vector estimation. The image frame is encoded using the motion vector.
摘要翻译：帧亮度检测单元15检测多个图像帧中的每一个的帧亮度值。闪烁频谱检测单元16从512帧的帧亮度值检测频率如100Hz，200Hz和300Hz的频谱值。亮度估计单元17从光谱值估计光源的增亮值。编码单元18使用估计亮度值的倒数来确定参考帧。编码单元18还在用于运动矢量估计的评估函数中使用倒数。使用运动矢量对图像帧进行编码。

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