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1. 发明授权

US06957317B2 Apparatus and method for facilitating memory data access with generic read/write patterns 失效
标题翻译：用于利用通用读/写模式促进存储器数据访问的装置和方法
公开(公告)号：US06957317B2
公开(公告)日：2005-10-18
申请号：US10268186
申请日：2002-10-10
申请人： Yen-Kuang Chen , Eric Debes , Matthew J. Holliman , Minerva M. Yeung
发明人： Yen-Kuang Chen , Eric Debes , Matthew J. Holliman , Minerva M. Yeung
IPC分类号： G06F12/08 , G06T1/60 , G06T9/00 , G09G5/393 , G06F12/00
CPC分类号： G06F12/0875 , G06F12/0877 , G06T1/60 , G06T9/00 , G09G5/393 , G09G2360/121
摘要： An apparatus and method facilitating memory data access with generic read/write patterns are described. In one embodiment, the method includes the detection, in response to a load instruction, of a cache hit/cache miss of data requested by the load instruction within a re-tiling (RT) cache. When a cache miss is detected, a block of data is loaded into the RT cache according to the load instruction. This block of data will contain the data requested by the load instruction. Once loaded, a non-horizontally sequential access of the data requested by the load instruction is performed from the RT cache. Finally, the data accessed from the RT cache may be stored into a destination data storage device according to the load instruction.
摘要翻译：描述了利用通用读/写模式促进存储器数据访问的装置和方法。在一个实施例中，该方法包括响应于加载指令，检测在重新平铺（RT）高速缓存内由加载指令请求的数据的高速缓存命中/高速缓存未命中。当检测到高速缓存未命中时，根据加载指令将一块数据加载到RT缓存中。该数据块将包含加载指令请求的数据。一旦加载，从RT缓存执行加载指令请求的数据的非水平顺序访问。最后，从RT缓存访问的数据可以根据加载指令存储到目的地数据存储装置中。

2. 发明授权

US07143264B2 Apparatus and method for performing data access in accordance with memory access patterns 有权
标题翻译：根据存储器访问模式执行数据访问的装置和方法
公开(公告)号：US07143264B2
公开(公告)日：2006-11-28
申请号：US10268166
申请日：2002-10-10
申请人： Eric Debes , Yen-Kuang Chen , Matthew J. Holliman , Minerva M. Yeung
发明人： Eric Debes , Yen-Kuang Chen , Matthew J. Holliman , Minerva M. Yeung
IPC分类号： G06F12/00
CPC分类号： G06F12/0875 , G06F12/0848 , G06F12/0897 , G06T1/60 , G09G5/393
摘要： An apparatus and method for performing data access in accordance with memory access patterns are described. In one embodiment, the method includes the determination, in response to a memory access instruction, of a memory access pattern of data requested by the memory access instruction. Once the memory access pattern is determined, the data requested by the memory access instruction is accessed according to the determined memory access pattern. Finally, once the data is accessed, the data is processed according to the memory access instruction. Accordingly, in this embodiment of the present invention, data is accessed according to memory access patterns including zig-zag patterns scan, Zerotree scan, bit plane extraction, fine granularity scalability or the like.
摘要翻译：描述了根据存储器访问模式执行数据访问的装置和方法。在一个实施例中，该方法包括响应于存储器访问指令确定由存储器访问指令请求的数据的存储器访问模式。一旦确定了存储器访问模式，则根据所确定的存储器访问模式访问由存储器访问指令请求的数据。最后，访问数据后，根据存储器访问指令对数据进行处理。因此，在本发明的这个实施例中，根据存储器访问模式访问数据，包括锯齿形图案扫描，Zerotree扫描，位平面提取，细粒度可伸缩性等。

3. 发明授权

US07162607B2 Apparatus and method for a data storage device with a plurality of randomly located data 有权
标题翻译：一种具有多个随机位置数据的数据存储装置的装置和方法
公开(公告)号：US07162607B2
公开(公告)日：2007-01-09
申请号：US09945422
申请日：2001-08-31
申请人： William W. Macy , Eric Debes , Igor V. Kozintsev , Minerva M. Yeung
发明人： William W. Macy , Eric Debes , Igor V. Kozintsev , Minerva M. Yeung
IPC分类号： G06F9/345
CPC分类号： G06F9/30043 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F9/3013 , G06F9/345 , G06F12/1408
摘要： An apparatus and method for loading a data storage device with a plurality of randomly located data are described. The method includes loading, in response to execution of a multiple data load instruction, data within a destination data storage device wherein one or more data elements from the data are randomly located within a memory device. In one embodiment, addresses of the data elements are contained within a data storage device and indicated as index addresses. In addition, the data elements are stored n one or more data storage areas of a memory device, which include look-up tables, data arrays or the like. In addition, data elements within the destination data storage device, as well as address indexes within the address data storage device may be organized in response to execution of a data shuffle instruction according to a data processing operation instruction.
摘要翻译：描述了一种用于加载具有多个随机定位的数据的数据存储装置的装置和方法。该方法包括响应于多个数据加载指令的执行而加载目的地数据存储设备中的数据，其中来自数据的一个或多个数据元素随机地位于存储器设备内。在一个实施例中，数据元素的地址被包含在数据存储设备内并且被指示为索引地址。此外，数据元素存储在包括查找表，数据阵列等的存储器件的一个或多个数据存储区域中。此外，可以响应于根据数据处理操作指令执行数据混洗指令来组织目的地数据存储设备内的数据元素以及地址数据存储设备内的地址索引。

4. 发明授权

US07085795B2 Apparatus and method for efficient filtering and convolution of content data 有权
标题翻译：用于有效过滤和卷积内容数据的装置和方法
公开(公告)号：US07085795B2
公开(公告)日：2006-08-01
申请号：US09952891
申请日：2001-10-29
申请人： Eric Debes , William W. Macy , Minerva M. Yeung
发明人： Eric Debes , William W. Macy , Minerva M. Yeung
IPC分类号： G06F17/15
CPC分类号： G06F17/15 , G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F9/3885 , G06F17/147
摘要： An apparatus and method for efficient filtering and convolution of content data are described. The method includes organizing, in response to executing a data shuffle instruction, a selected portion of data within a destination data storage device. The portion of data is organized according to an arrangement of coefficients within a coefficient data storage device. Once organized, a plurality of summed-product pairs are generated in response to executing a multiply-accumulate instruction. The plurality of product pairs are formed by multiplying data within the destination data storage device and coefficients within the coefficient data storage device. Once generated, adjacent summed-product pairs are added in response to executing an adjacent-add instruction. The adjacent summed-product pairs are added within the destination data storage device to form one or more data processing operation results. Once the one or more data processing operation results are formed, the results are stored within a memory device.
摘要翻译：描述了一种用于高效过滤和卷积内容数据的装置和方法。该方法包括响应于执行数据随机播放指令，组织目的地数据存储设备内的所选数据部分。根据系数数据存储装置内的系数排列来组织数据的部分。一旦被组织，响应于执行乘法累积指令而产生多个累加产物对。通过将目的地数据存储装置内的数据与系数数据存储装置内的系数相乘来形成多个乘积对。一旦生成，响应于执行相邻加法指令而添加相邻求和产物对。在目的地数据存储装置内添加相邻的相加乘积对以形成一个或多个数据处理运算结果。一旦形成了一个或多个数据处理操作结果，结果被存储在存储器件中。

5. 发明授权

US07392275B2 Method and apparatus for performing efficient transformations with horizontal addition and subtraction 有权
标题翻译：用水平加法和减法进行有效转换的方法和装置
公开(公告)号：US07392275B2
公开(公告)日：2008-06-24
申请号：US10611326
申请日：2003-06-30
申请人： William W. Macy , Eric Debes , Minerva Yeung , Yen-Kuang Chen , Patrice Roussel
发明人： William W. Macy , Eric Debes , Minerva Yeung , Yen-Kuang Chen , Patrice Roussel
IPC分类号： G06F17/15
CPC分类号： G06F9/3885 , G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F17/147 , G06F17/15
摘要： A method and apparatus for including in a processor instructions for performing horizontal intra-add operations on packed data. One embodiment of the processor is coupled to a memory. The memory has stored therein at least a first packed data. The processor performs operations on data elements in the first packed data to generate a plurality of data elements in a second packed data in response to receiving an instruction. At least two of the plurality of data elements in the second packed data store the results of an intra-add operation, at least one of these results coming from the operation on data elements of the first packed data. One embodiment of a software method utilizes horizontal intra-add instructions for performing butterfly computations as may be employed, for example, in Walsh-Hadamard transforms or in Fast-Fourier Transforms.
摘要翻译：一种用于在处理器中包括用于对打包数据执行水平加载操作的指令的方法和装置。处理器的一个实施例耦合到存储器。存储器至少存储有第一打包数据。处理器对第一打包数据中的数据元素执行操作，以响应于接收到指令而在第二打包数据中生成多个数据元素。第二打包数据中的多个数据元素中的至少两个存储加入内操作的结果，这些结果中的至少一个来自对第一打包数据的数据元素的操作。软件方法的一个实施例利用例如在沃尔什 - 哈达玛（Walsh-Hadamard）变换或快速傅里叶变换中可以采用的用于执行蝶形运算的水平内插指令。

6. 发明申请

US20050108312A1 Bitstream buffer manipulation with a SIMD merge instruction 有权
标题翻译：使用SIMD合并指令进行位流缓冲操作
公开(公告)号：US20050108312A1
公开(公告)日：2005-05-19
申请号：US10612542
申请日：2003-07-01
申请人： Yen-Kuang Chen , William Macy , Matthew Holliman , Eric Debes , Minerva Young
发明人： Yen-Kuang Chen , William Macy , Matthew Holliman , Eric Debes , Minerva Young
IPC分类号： G06F9/30 , G06F9/302 , G06F9/308 , G06F9/315 , G06F9/38 , G06F17/14 , G06F7/38
CPC分类号： G06F9/30145 , G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F9/30112 , G06F9/3013 , G06F9/3816 , G06F9/3885 , G06F15/8007 , G06F17/147 , G06F17/15
摘要： Method, apparatus, and program means for performing bitstream buffer manipulation with a SIMD merge instruction. The method of one embodiment comprises determining whether any unprocessed data bits for a partial variable length symbol exist in a first data block is made. A shift merge operation is performed to merge the unprocessed data bits from the first data block with a second data block. A merged data block is formed. A merged variable length symbol comprised of the unprocessed data bits and a plurality of data bits from the second data block is extracted from the merged data block.
摘要翻译：用于使用SIMD合并指令执行比特流缓冲器操作的方法，装置和程序装置。一个实施例的方法包括确定在第一数据块中是否存在用于部分可变长度符号的任何未处理的数据比特。执行移位合并操作以将来自第一数据块的未处理数据位与第二数据块合并。形成合并的数据块。从合并的数据块中提取由未处理的数据位和来自第二数据块的多个数据位组成的合并的可变长度符号。

7. 发明授权

US06781589B2 Apparatus and method for extracting and loading data to/from a buffer 有权
标题翻译：用于从缓冲器提取数据并从缓冲器加载数据的装置和方法
公开(公告)号：US06781589B2
公开(公告)日：2004-08-24
申请号：US09948333
申请日：2001-09-06
申请人： William W. Macy , Matthew Holliman , Eric Debes , Yen-Kuang Chen
发明人： William W. Macy , Matthew Holliman , Eric Debes , Yen-Kuang Chen
IPC分类号： G06F1300
CPC分类号： G06F5/065
摘要： An apparatus and method for extracting and loading data to/from a buffer are described. The method includes the selection of data from a data buffer in response to execution of a data access instruction. The data buffer includes a plurality of data storage devices, one or more of which initially contain the selected data. Accordingly, the plurality of data storage devices form a single address space that is addressable at a bit-level. When the selected data spans from a source data storage device to a next data storage device of the data buffer, a portion of the selected data from source data storage device is concatenated with a remaining portion of the selected data from the next data storage device to form the selected data as a contiguous unit. Finally, once the selected data is formed, the selected data is stored within a destination data storage device.
摘要翻译：描述了一种用于提取和从缓冲器加载数据的装置和方法。该方法包括响应于数据访问指令的执行从数据缓冲器中选择数据。数据缓冲器包括多个数据存储设备，其中一个或多个初始地包含所选择的数据。因此，多个数据存储装置形成在位层可寻址的单个地址空间。当所选择的数据从源数据存储装置跨越到数据缓冲器的下一个数据存储装置时，来自源数据存储装置的所选数据的一部分与来自下一数据存储装置的所选数据的剩余部分相连，将所选数据形成为连续单位。最后，一旦形成所选择的数据，所选择的数据被存储在目的地数据存储装置中。

8. 发明申请

US20130007417A1 PROCESSOR TO EXECUTE SHIFT RIGHT MERGE INSTRUCTIONS 有权
标题翻译：处理器执行移动权限指令
公开(公告)号：US20130007417A1
公开(公告)日：2013-01-03
申请号：US13602546
申请日：2012-09-04
申请人： Julien Sebot , William W. Macy , Eric Debes , Huy V. Nguyen
发明人： Julien Sebot , William W. Macy , Eric Debes , Huy V. Nguyen
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F9/30112 , G06F9/3013 , G06F9/3816 , G06F9/3885 , G06F15/8007 , G06F17/147 , G06F17/15
摘要： Method, apparatus, and program means for performing bitstream buffer manipulation with a SIMD merge instruction. The method of one embodiment comprises determining whether any unprocessed data bits for a partial variable length symbol exist in a first data block is made. A shift merge operation is performed to merge the unprocessed data bits from the first data block with a second data block. A merged data block is formed. A merged variable length symbol comprised of the unprocessed data bits and a plurality of data bits from the second data block is extracted from the merged data block.
摘要翻译：用于使用SIMD合并指令执行比特流缓冲器操作的方法，装置和程序装置。一个实施例的方法包括确定在第一数据块中是否存在用于部分可变长度符号的任何未处理的数据比特。执行移位合并操作以将来自第一数据块的未处理数据位与第二数据块合并。形成合并的数据块。从合并的数据块中提取由未处理的数据位和来自第二数据块的多个数据位组成的合并的可变长度符号。

9. 发明授权

US07343389B2 Apparatus and method for SIMD modular multiplication 失效
标题翻译： SIMD模数乘法的装置和方法
公开(公告)号：US07343389B2
公开(公告)日：2008-03-11
申请号：US10137560
申请日：2002-05-02
申请人： William W. Macy , Hong Jiang , Eric Debes , Igor V. Kozintsev
发明人： William W. Macy , Hong Jiang , Eric Debes , Igor V. Kozintsev
IPC分类号： G06F7/38
CPC分类号： G06F7/722 , G06F2207/3828
摘要： An apparatus and method for single instruction multiple data (SIMD) modular multiplication are described. In one embodiment, the method includes selection of modular multiplication method available from an operating environment. Once the multiplication method is selected, a data access pattern for processing of data is selected. Finally, the selected modular multiplication method is executed in order to process data according to the selected data access pattern. In a further embodiment, a SIMD modular multiplication instruction is provided in order to enable simultaneous modular multiplication of multiplicand and multiplier operands, which may be vertically or horizontally accessed from memory, as indicated by a selected data access pattern. Alternatively, modular multiplication is implemented utilizing a SIMD byte shuffle operation, which enables modular multiplication of a constant multiplicand value to varying data multiplier values.
摘要翻译：描述了用于单指令多数据（SIMD）模乘的装置和方法。在一个实施例中，该方法包括选择可从操作环境获得的模乘法。一旦选择了乘法，则选择用于处理数据的数据访问模式。最后，执行所选择的乘法方法，以便根据所选择的数据访问模式处理数据。在进一步的实施例中，提供SIMD模乘相乘指令，以便能够同时对乘法器和乘法器操作数进行模乘，其可以从存储器垂直或水平访问，如所选数据访问模式所示。或者，使用SIMD字节洗牌操作实现模乘法，其使得恒定被乘数值与变化的数据乘数值的模乘相乘。

10. 发明申请

US20080052428A1 Turbo station for computing systems 审中-公开
标题翻译：用于计算系统的Turbo站
公开(公告)号：US20080052428A1
公开(公告)日：2008-02-28
申请号：US11502170
申请日：2006-08-10
申请人： Jeffrey Liang , Greg Kaine , Eric Debes , Ramon C. Cancel , Allen Huang , Patrick K. Leung , Luis Vargas
发明人： Jeffrey Liang , Greg Kaine , Eric Debes , Ramon C. Cancel , Allen Huang , Patrick K. Leung , Luis Vargas
IPC分类号： G06F13/38
CPC分类号： G06T1/20 , G06F1/206 , G06F3/14 , G06F13/385 , G09G5/363 , G09G2360/06
摘要： In one embodiment, a system comprises a portable computing device comprising a first graphics controller and a first communication interface, and a turbo station comprising a second communication interface to manage communication with the portable computing device, and at least one auxiliary computing component coupled to the communication interface and configured to process cooperatively with the first graphics controller in the portable computing device.
摘要翻译：在一个实施例中，系统包括包括第一图形控制器和第一通信接口的便携式计算设备，以及包括用于管理与便携式计算设备的通信的第二通信接口的turbo站，以及耦合到该第一通信接口的至少一个辅助计算组件通信接口并且被配置为与便携式计算设备中的第一图形控制器协同地处理。

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