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1. 发明授权

US07392275B2 Method and apparatus for performing efficient transformations with horizontal addition and subtraction 有权
标题翻译：用水平加法和减法进行有效转换的方法和装置
公开(公告)号：US07392275B2
公开(公告)日：2008-06-24
申请号：US10611326
申请日：2003-06-30
申请人： William W. Macy , Eric Debes , Minerva Yeung , Yen-Kuang Chen , Patrice Roussel
发明人： William W. Macy , Eric Debes , Minerva Yeung , Yen-Kuang Chen , Patrice Roussel
IPC分类号： G06F17/15
CPC分类号： G06F9/3885 , G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F17/147 , G06F17/15
摘要： A method and apparatus for including in a processor instructions for performing horizontal intra-add operations on packed data. One embodiment of the processor is coupled to a memory. The memory has stored therein at least a first packed data. The processor performs operations on data elements in the first packed data to generate a plurality of data elements in a second packed data in response to receiving an instruction. At least two of the plurality of data elements in the second packed data store the results of an intra-add operation, at least one of these results coming from the operation on data elements of the first packed data. One embodiment of a software method utilizes horizontal intra-add instructions for performing butterfly computations as may be employed, for example, in Walsh-Hadamard transforms or in Fast-Fourier Transforms.
摘要翻译：一种用于在处理器中包括用于对打包数据执行水平加载操作的指令的方法和装置。处理器的一个实施例耦合到存储器。存储器至少存储有第一打包数据。处理器对第一打包数据中的数据元素执行操作，以响应于接收到指令而在第二打包数据中生成多个数据元素。第二打包数据中的多个数据元素中的至少两个存储加入内操作的结果，这些结果中的至少一个来自对第一打包数据的数据元素的操作。软件方法的一个实施例利用例如在沃尔什 - 哈达玛（Walsh-Hadamard）变换或快速傅里叶变换中可以采用的用于执行蝶形运算的水平内插指令。

2. 发明授权

US06781589B2 Apparatus and method for extracting and loading data to/from a buffer 有权
标题翻译：用于从缓冲器提取数据并从缓冲器加载数据的装置和方法
公开(公告)号：US06781589B2
公开(公告)日：2004-08-24
申请号：US09948333
申请日：2001-09-06
申请人： William W. Macy , Matthew Holliman , Eric Debes , Yen-Kuang Chen
发明人： William W. Macy , Matthew Holliman , Eric Debes , Yen-Kuang Chen
IPC分类号： G06F1300
CPC分类号： G06F5/065
摘要： An apparatus and method for extracting and loading data to/from a buffer are described. The method includes the selection of data from a data buffer in response to execution of a data access instruction. The data buffer includes a plurality of data storage devices, one or more of which initially contain the selected data. Accordingly, the plurality of data storage devices form a single address space that is addressable at a bit-level. When the selected data spans from a source data storage device to a next data storage device of the data buffer, a portion of the selected data from source data storage device is concatenated with a remaining portion of the selected data from the next data storage device to form the selected data as a contiguous unit. Finally, once the selected data is formed, the selected data is stored within a destination data storage device.
摘要翻译：描述了一种用于提取和从缓冲器加载数据的装置和方法。该方法包括响应于数据访问指令的执行从数据缓冲器中选择数据。数据缓冲器包括多个数据存储设备，其中一个或多个初始地包含所选择的数据。因此，多个数据存储装置形成在位层可寻址的单个地址空间。当所选择的数据从源数据存储装置跨越到数据缓冲器的下一个数据存储装置时，来自源数据存储装置的所选数据的一部分与来自下一数据存储装置的所选数据的剩余部分相连，将所选数据形成为连续单位。最后，一旦形成所选择的数据，所选择的数据被存储在目的地数据存储装置中。

3. 发明授权

US07395302B2 Method and apparatus for performing horizontal addition and subtraction 有权
标题翻译：执行水平加法和减法的方法和装置
公开(公告)号：US07395302B2
公开(公告)日：2008-07-01
申请号：US10610784
申请日：2003-06-30
申请人： William W. Macy , Eric Debes , Mark J. Buxton , Patrice Roussel , Julien Sebot , Huy V. Nguyen
发明人： William W. Macy , Eric Debes , Mark J. Buxton , Patrice Roussel , Julien Sebot , Huy V. Nguyen
IPC分类号： G06F7/50
CPC分类号： G06F9/3001 , G06F9/30018 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/3885 , G06F17/142 , G06F17/147
摘要： A method and apparatus for including in a processor instructions for performing horizontal intra-add operations on packed data. One embodiment of the processor is coupled to a memory. The memory has stored therein at least a first packed data. The processor performs operations on data elements in the first packed data to generate a plurality of data elements in a second packed data in response to receiving an instruction. At least two of the plurality of data elements in the second packed data store the results of an intra-add operation, at least one of these results coming from the operation on data elements of the first packed data. One embodiment of a software method utilizes horizontal intra-add instructions for performing butterfly computations as may be employed, for example, in Walsh-Hadamard transforms or in Fast-Fourier Transforms.
摘要翻译：一种用于在处理器中包括用于对打包数据执行水平加载操作的指令的方法和装置。处理器的一个实施例耦合到存储器。存储器至少存储有第一打包数据。处理器对第一打包数据中的数据元素执行操作，以响应于接收到指令而在第二打包数据中生成多个数据元素。第二打包数据中的多个数据元素中的至少两个存储加入内操作的结果，这些结果中的至少一个来自对第一打包数据的数据元素的操作。软件方法的一个实施例利用例如在沃尔什 - 哈达玛（Walsh-Hadamard）变换或快速傅里叶变换中可以采用的用于执行蝶形运算的水平内插指令。

4. 发明授权

US06798364B2 Method and apparatus for variable length coding 有权
标题翻译：用于可变长度编码的方法和装置
公开(公告)号：US06798364B2
公开(公告)日：2004-09-28
申请号：US10068050
申请日：2002-02-05
申请人： Yen-Kuang Chen , Matthew J. Holliman , Herbert Hum , Per H. Hammarlund , Thomas Huff , William W. Macy
发明人： Yen-Kuang Chen , Matthew J. Holliman , Herbert Hum , Per H. Hammarlund , Thomas Huff , William W. Macy
IPC分类号： H03M740
CPC分类号： H03M7/46 , G11B20/1426 , H03M5/145 , H03M7/40 , H04N19/13 , H04N19/29 , H04N19/34 , H04N19/36 , H04N19/63
摘要： A method and apparatus for variable length coding is described. A method comprises receiving a group of data having a group of set values, identifying a group of positions of the group of set values within the group of data without branching, for each of the group of positions, encoding a run of non-set values preceding each of the group of positions.
摘要翻译：描述了用于可变长度编码的方法和装置。一种方法包括：接收一组具有一组设定值的数据，识别所述数据组内的所述组中的组的位置组，而不分支，对于所述一组位置中的每一个，编码非设定值的运行在每组职位之前。

5. 发明申请

US20100011042A1 Method and Apparatus for Efficient Integer Transform 有权
标题翻译：高效整数变换的方法和装置
公开(公告)号：US20100011042A1
公开(公告)日：2010-01-14
申请号：US12560225
申请日：2009-09-15
申请人： Eric Debes , William W. Macy , Jonathan J. Tyler
发明人： Eric Debes , William W. Macy , Jonathan J. Tyler
IPC分类号： G06F17/14 , G06F7/44 , G06F7/42
CPC分类号： G06F9/3885 , G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F17/147 , G06F17/15
摘要： A method and apparatus for including in a processor instructions for performing integer transforms including multiply-add operations and horizontal-add operations on packed data. In one embodiment, a processor is coupled to a memory that stores a first packed byte data and a second packed byte data. The processor performs operations on said first packed byte data and said second packed byte data to generate a third packed data in response to receiving a multiply-add instruction. A plurality of the 16-bit data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed byte data. The processor adds together at least a first and a second 16-bit data element of the third packed data in response to receiving an horizontal-add instruction to generate a 16-bit result as one of a plurality of data elements of a fourth packed data.
摘要翻译：一种用于在处理器中包括用于执行整数变换的指令的方法和装置，包括对打包数据的乘法运算和水平加法运算。在一个实施例中，处理器耦合到存储第一打包字节数据和第二打包字节数据的存储器。处理器对所述第一打包字节数据和所述第二打包字节数据执行操作，以响应于接收到加法指令而产生第三打包数据。该第三打包数据中的多个16位数据元素存储对第一和第二打包字节数据中的数据元素执行加法运算的结果。处理器响应于接收到水平加法指令而将第三打包数据的至少第一和第二16位数据元素加在一起，以生成作为第四打包数据的多个数据元素之一的16位结果。

6. 发明授权

US07272622B2 Method and apparatus for parallel shift right merge of data 有权
标题翻译：并行移动数据合并的方法和装置
公开(公告)号：US07272622B2
公开(公告)日：2007-09-18
申请号：US10280511
申请日：2002-10-25
申请人： Julien Sebot , William W. Macy , Eric Debes , Huy V. Nguyen
发明人： Julien Sebot , William W. Macy , Eric Debes , Huy V. Nguyen
IPC分类号： G06F5/01
CPC分类号： G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F9/30112 , G06F9/3013 , G06F9/3885 , G06F17/147 , G06F17/15
摘要： A method for a parallel shift right merge of data. The method of one embodiment comprises receiving a shift count of M. A first operand having a first set of L data elements is shifted left by ‘L−M’ data elements. A second operand having a second set of L data elements is shifted right by M data elements. The shifted first set is merged with the shifted second set to generate a resultant having L data elements.
摘要翻译：并行移位数据的合并方法。一个实施例的方法包括接收M的移位计数。具有第一组L个数据元素的第一操作数左移“L-M”数据元素。具有第二组L个数据元素的第二操作数被M个数据元素右移。移位的第一集合与移位的第二集合合并以产生具有L个数据元素的合成。

7. 发明申请

US20130007417A1 PROCESSOR TO EXECUTE SHIFT RIGHT MERGE INSTRUCTIONS 有权
标题翻译：处理器执行移动权限指令
公开(公告)号：US20130007417A1
公开(公告)日：2013-01-03
申请号：US13602546
申请日：2012-09-04
申请人： Julien Sebot , William W. Macy , Eric Debes , Huy V. Nguyen
发明人： Julien Sebot , William W. Macy , Eric Debes , Huy V. Nguyen
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F9/30112 , G06F9/3013 , G06F9/3816 , G06F9/3885 , G06F15/8007 , G06F17/147 , G06F17/15
摘要： Method, apparatus, and program means for performing bitstream buffer manipulation with a SIMD merge instruction. The method of one embodiment comprises determining whether any unprocessed data bits for a partial variable length symbol exist in a first data block is made. A shift merge operation is performed to merge the unprocessed data bits from the first data block with a second data block. A merged data block is formed. A merged variable length symbol comprised of the unprocessed data bits and a plurality of data bits from the second data block is extracted from the merged data block.
摘要翻译：用于使用SIMD合并指令执行比特流缓冲器操作的方法，装置和程序装置。一个实施例的方法包括确定在第一数据块中是否存在用于部分可变长度符号的任何未处理的数据比特。执行移位合并操作以将来自第一数据块的未处理数据位与第二数据块合并。形成合并的数据块。从合并的数据块中提取由未处理的数据位和来自第二数据块的多个数据位组成的合并的可变长度符号。

8. 发明授权

US07343389B2 Apparatus and method for SIMD modular multiplication 失效
标题翻译： SIMD模数乘法的装置和方法
公开(公告)号：US07343389B2
公开(公告)日：2008-03-11
申请号：US10137560
申请日：2002-05-02
申请人： William W. Macy , Hong Jiang , Eric Debes , Igor V. Kozintsev
发明人： William W. Macy , Hong Jiang , Eric Debes , Igor V. Kozintsev
IPC分类号： G06F7/38
CPC分类号： G06F7/722 , G06F2207/3828
摘要： An apparatus and method for single instruction multiple data (SIMD) modular multiplication are described. In one embodiment, the method includes selection of modular multiplication method available from an operating environment. Once the multiplication method is selected, a data access pattern for processing of data is selected. Finally, the selected modular multiplication method is executed in order to process data according to the selected data access pattern. In a further embodiment, a SIMD modular multiplication instruction is provided in order to enable simultaneous modular multiplication of multiplicand and multiplier operands, which may be vertically or horizontally accessed from memory, as indicated by a selected data access pattern. Alternatively, modular multiplication is implemented utilizing a SIMD byte shuffle operation, which enables modular multiplication of a constant multiplicand value to varying data multiplier values.
摘要翻译：描述了用于单指令多数据（SIMD）模乘的装置和方法。在一个实施例中，该方法包括选择可从操作环境获得的模乘法。一旦选择了乘法，则选择用于处理数据的数据访问模式。最后，执行所选择的乘法方法，以便根据所选择的数据访问模式处理数据。在进一步的实施例中，提供SIMD模乘相乘指令，以便能够同时对乘法器和乘法器操作数进行模乘，其可以从存储器垂直或水平访问，如所选数据访问模式所示。或者，使用SIMD字节洗牌操作实现模乘法，其使得恒定被乘数值与变化的数据乘数值的模乘相乘。

9. 发明授权

US07162607B2 Apparatus and method for a data storage device with a plurality of randomly located data 有权
标题翻译：一种具有多个随机位置数据的数据存储装置的装置和方法
公开(公告)号：US07162607B2
公开(公告)日：2007-01-09
申请号：US09945422
申请日：2001-08-31
申请人： William W. Macy , Eric Debes , Igor V. Kozintsev , Minerva M. Yeung
发明人： William W. Macy , Eric Debes , Igor V. Kozintsev , Minerva M. Yeung
IPC分类号： G06F9/345
CPC分类号： G06F9/30043 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F9/3013 , G06F9/345 , G06F12/1408
摘要： An apparatus and method for loading a data storage device with a plurality of randomly located data are described. The method includes loading, in response to execution of a multiple data load instruction, data within a destination data storage device wherein one or more data elements from the data are randomly located within a memory device. In one embodiment, addresses of the data elements are contained within a data storage device and indicated as index addresses. In addition, the data elements are stored n one or more data storage areas of a memory device, which include look-up tables, data arrays or the like. In addition, data elements within the destination data storage device, as well as address indexes within the address data storage device may be organized in response to execution of a data shuffle instruction according to a data processing operation instruction.
摘要翻译：描述了一种用于加载具有多个随机定位的数据的数据存储装置的装置和方法。该方法包括响应于多个数据加载指令的执行而加载目的地数据存储设备中的数据，其中来自数据的一个或多个数据元素随机地位于存储器设备内。在一个实施例中，数据元素的地址被包含在数据存储设备内并且被指示为索引地址。此外，数据元素存储在包括查找表，数据阵列等的存储器件的一个或多个数据存储区域中。此外，可以响应于根据数据处理操作指令执行数据混洗指令来组织目的地数据存储设备内的数据元素以及地址数据存储设备内的地址索引。

10. 发明授权

US08782377B2 Processor to execute shift right merge instructions 有权
公开(公告)号：US08782377B2
公开(公告)日：2014-07-15
申请号：US13477544
申请日：2012-05-22
申请人： Julien Sebot , William W. Macy , Eric Debes , Huy V. Nguyen
发明人： Julien Sebot , William W. Macy , Eric Debes , Huy V. Nguyen
IPC分类号： G06F9/30 , G06F9/44 , G06F15/00
CPC分类号： G06F9/30145 , G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F9/30112 , G06F9/3013 , G06F9/3816 , G06F9/3885 , G06F15/8007 , G06F17/147 , G06F17/15
摘要： Method, apparatus, and program means for performing bitstream buffer manipulation with a SIMD merge instruction. The method of one embodiment comprises determining whether any unprocessed data bits for a partial variable length symbol exist in a first data block is made. A shift merge operation is performed to merge the unprocessed data bits from the first data block with a second data block. A merged data block is formed. A merged variable length symbol comprised of the unprocessed data bits and a plurality of data bits from the second data block is extracted from the merged data block.

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