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1. 发明申请

US20050108312A1 Bitstream buffer manipulation with a SIMD merge instruction 有权
标题翻译：使用SIMD合并指令进行位流缓冲操作
公开(公告)号：US20050108312A1
公开(公告)日：2005-05-19
申请号：US10612542
申请日：2003-07-01
申请人： Yen-Kuang Chen , William Macy , Matthew Holliman , Eric Debes , Minerva Young
发明人： Yen-Kuang Chen , William Macy , Matthew Holliman , Eric Debes , Minerva Young
IPC分类号： G06F9/30 , G06F9/302 , G06F9/308 , G06F9/315 , G06F9/38 , G06F17/14 , G06F7/38
CPC分类号： G06F9/30145 , G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F9/30112 , G06F9/3013 , G06F9/3816 , G06F9/3885 , G06F15/8007 , G06F17/147 , G06F17/15
摘要： Method, apparatus, and program means for performing bitstream buffer manipulation with a SIMD merge instruction. The method of one embodiment comprises determining whether any unprocessed data bits for a partial variable length symbol exist in a first data block is made. A shift merge operation is performed to merge the unprocessed data bits from the first data block with a second data block. A merged data block is formed. A merged variable length symbol comprised of the unprocessed data bits and a plurality of data bits from the second data block is extracted from the merged data block.
摘要翻译：用于使用SIMD合并指令执行比特流缓冲器操作的方法，装置和程序装置。一个实施例的方法包括确定在第一数据块中是否存在用于部分可变长度符号的任何未处理的数据比特。执行移位合并操作以将来自第一数据块的未处理数据位与第二数据块合并。形成合并的数据块。从合并的数据块中提取由未处理的数据位和来自第二数据块的多个数据位组成的合并的可变长度符号。

2. 发明授权

US06781589B2 Apparatus and method for extracting and loading data to/from a buffer 有权
标题翻译：用于从缓冲器提取数据并从缓冲器加载数据的装置和方法
公开(公告)号：US06781589B2
公开(公告)日：2004-08-24
申请号：US09948333
申请日：2001-09-06
申请人： William W. Macy , Matthew Holliman , Eric Debes , Yen-Kuang Chen
发明人： William W. Macy , Matthew Holliman , Eric Debes , Yen-Kuang Chen
IPC分类号： G06F1300
CPC分类号： G06F5/065
摘要： An apparatus and method for extracting and loading data to/from a buffer are described. The method includes the selection of data from a data buffer in response to execution of a data access instruction. The data buffer includes a plurality of data storage devices, one or more of which initially contain the selected data. Accordingly, the plurality of data storage devices form a single address space that is addressable at a bit-level. When the selected data spans from a source data storage device to a next data storage device of the data buffer, a portion of the selected data from source data storage device is concatenated with a remaining portion of the selected data from the next data storage device to form the selected data as a contiguous unit. Finally, once the selected data is formed, the selected data is stored within a destination data storage device.
摘要翻译：描述了一种用于提取和从缓冲器加载数据的装置和方法。该方法包括响应于数据访问指令的执行从数据缓冲器中选择数据。数据缓冲器包括多个数据存储设备，其中一个或多个初始地包含所选择的数据。因此，多个数据存储装置形成在位层可寻址的单个地址空间。当所选择的数据从源数据存储装置跨越到数据缓冲器的下一个数据存储装置时，来自源数据存储装置的所选数据的一部分与来自下一数据存储装置的所选数据的剩余部分相连，将所选数据形成为连续单位。最后，一旦形成所选择的数据，所选择的数据被存储在目的地数据存储装置中。

3. 发明申请

US20110035426A1 Bitstream Buffer Manipulation with a SIMD Merge Instruction 有权
标题翻译：使用SIMD合并指令进行位流缓冲操作
公开(公告)号：US20110035426A1
公开(公告)日：2011-02-10
申请号：US12907843
申请日：2010-10-19
申请人： Yen-Kuang Chen , William W. Macy, JR. , Matthew Holliman , Eric L. Debes , Minerva M. Yeung
发明人： Yen-Kuang Chen , William W. Macy, JR. , Matthew Holliman , Eric L. Debes , Minerva M. Yeung
IPC分类号： G06F15/00
CPC分类号： G06F9/30145 , G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F9/30112 , G06F9/3013 , G06F9/3816 , G06F9/3885 , G06F15/8007 , G06F17/147 , G06F17/15
摘要： Method, apparatus, and program means for performing bitstream buffer manipulation with a SIMD merge instruction. The method of one embodiment comprises determining whether any unprocessed data bits for a partial variable length symbol exist in a first data block is made. A shift merge operation is performed to merge the unprocessed data bits from the first data block with a second data block. A merged data block is formed. A merged variable length symbol comprised of the unprocessed data bits and a plurality of data bits from the second data block is extracted from the merged data block.
摘要翻译：用于使用SIMD合并指令执行比特流缓冲器操作的方法，装置和程序装置。一个实施例的方法包括确定在第一数据块中是否存在用于部分可变长度符号的任何未处理的数据比特。执行移位合并操作以将来自第一数据块的未处理数据位与第二数据块合并。形成合并的数据块。从合并的数据块中提取由未处理的数据位和来自第二数据块的多个数据位组成的合并的可变长度符号。

4. 发明授权

US07818356B2 Bitstream buffer manipulation with a SIMD merge instruction 有权
标题翻译：使用SIMD合并指令进行位流缓冲操作
公开(公告)号：US07818356B2
公开(公告)日：2010-10-19
申请号：US10612542
申请日：2003-07-01
申请人： Yen-Kuang Chen , William W. Macy, Jr. , Matthew Holliman , Eric L. Debes , Minerva M. Young
发明人： Yen-Kuang Chen , William W. Macy, Jr. , Matthew Holliman , Eric L. Debes , Minerva M. Young
IPC分类号： G06F5/01
CPC分类号： G06F9/30145 , G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F9/30112 , G06F9/3013 , G06F9/3816 , G06F9/3885 , G06F15/8007 , G06F17/147 , G06F17/15
摘要： Method, apparatus, and program means for performing bitstream buffer manipulation with a SIMD merge instruction. The method of one embodiment comprises determining whether any unprocessed data bits for a partial variable length symbol exist in a first data block is made. A shift merge operation is performed to merge the unprocessed data bits from the first data block with a second data block. A merged data block is formed. A merged variable length symbol comprised of the unprocessed data bits and a plurality of data bits from the second data block is extracted from the merged data block.
摘要翻译：用于使用SIMD合并指令执行比特流缓冲器操作的方法，装置和程序装置。一个实施例的方法包括确定在第一数据块中是否存在用于部分可变长度符号的任何未处理的数据比特。执行移位合并操作以将来自第一数据块的未处理数据位与第二数据块合并。形成合并的数据块。从合并的数据块中提取由未处理的数据位和来自第二数据块的多个数据位组成的合并的可变长度符号。

5. 发明授权

US06816949B2 Method and apparatus for cache management 失效
标题翻译：缓存管理方法和装置
公开(公告)号：US06816949B2
公开(公告)日：2004-11-09
申请号：US10040007
申请日：2002-01-03
申请人： Rainer W. Lienhart , Yen-Kuang Chen , Matthew Holliman , Minerva M. Yeung
发明人： Rainer W. Lienhart , Yen-Kuang Chen , Matthew Holliman , Minerva M. Yeung
IPC分类号： G06F1212
CPC分类号： G06F12/0802 , G06F12/122 , G06F2212/401
摘要： A cache management operation. In one embodiment, a first recall value for a first unit of data is generated, a second recall value for a second unit of data is generated, and the first and second recall values are compared. The unit of data having the higher recall value is stored in a first section of a storage device. The unit of data having the lower recall value is stored in a second section of a storage device. A greater amount of compression is performed on the unit of data having the lower recall value.
摘要翻译：缓存管理操作。在一个实施例中，生成第一数据单元的第一回调值，生成第二数据单元的第二回调值，并比较第一和第二回调值。具有较高回忆值的数据单元被存储在存储设备的第一部分中。具有较低重调用值的数据单元被存储在存储装置的第二部分中。对具有较低回忆值的数据单元执行更大量的压缩。

6. 发明授权

US08510355B2 Bitstream buffer manipulation with a SIMD merge instruction 有权
公开(公告)号：US08510355B2
公开(公告)日：2013-08-13
申请号：US12907843
申请日：2010-10-19
申请人： Yen-Kuang Chen , William W. Macy, Jr. , Matthew Holliman , Eric L. Debes , Minerva M. Yeung
发明人： Yen-Kuang Chen , William W. Macy, Jr. , Matthew Holliman , Eric L. Debes , Minerva M. Yeung
IPC分类号： G06F5/01
CPC分类号： G06F9/30145 , G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F9/30112 , G06F9/3013 , G06F9/3816 , G06F9/3885 , G06F15/8007 , G06F17/147 , G06F17/15
摘要： Method, apparatus, and program means for performing bitstream buffer manipulation with a SIMD merge instruction. The method of one embodiment comprises determining whether any unprocessed data bits for a partial variable length symbol exist in a first data block is made. A shift merge operation is performed to merge the unprocessed data bits from the first data block with a second data block. A merged data block is formed. A merged variable length symbol comprised of the unprocessed data bits and a plurality of data bits from the second data block is extracted from the merged data block.

7. 发明申请

US20130138917A1 Bitstream Buffer Manipulation With A SIMD Merge Instruction 有权
公开(公告)号：US20130138917A1
公开(公告)日：2013-05-30
申请号：US13752916
申请日：2013-01-29
申请人： Yen-Kueng Chen , William W. Macy, JR. , Matthew Holliman , Eric L. Debes , Minerva M. Yeung
发明人： Yen-Kueng Chen , William W. Macy, JR. , Matthew Holliman , Eric L. Debes , Minerva M. Yeung
IPC分类号： G06F15/80
CPC分类号： G06F9/30145 , G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F9/30112 , G06F9/3013 , G06F9/3816 , G06F9/3885 , G06F15/8007 , G06F17/147 , G06F17/15
摘要： Method, apparatus, and program means for performing bitstream buffer manipulation with a SIMD merge instruction. The method of one embodiment comprises determining whether any unprocessed data bits for a partial variable length symbol exist in a first data block is made. A shift merge operation is performed to merge the unprocessed data bits from the first data block with a second data block. A merged data block is formed. A merged variable length symbol comprised of the unprocessed data bits and a plurality of data bits from the second data block is extracted from the merged data block.

8. 发明申请

US20130145125A1 Bitstream Buffer Manipulation With A SIMD Merge Instruction 有权
公开(公告)号：US20130145125A1
公开(公告)日：2013-06-06
申请号：US13752987
申请日：2013-01-29
申请人： Yen-Kueng Chen , William W. Macy, JR. , Matthew Holliman , Eric L. Debes , Minerva M. Yeung
发明人： Yen-Kueng Chen , William W. Macy, JR. , Matthew Holliman , Eric L. Debes , Minerva M. Yeung
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F9/30112 , G06F9/3013 , G06F9/3816 , G06F9/3885 , G06F15/8007 , G06F17/147 , G06F17/15
摘要： Method, apparatus, and program means for performing bitstream buffer manipulation with a SIMD merge instruction. The method of one embodiment comprises determining whether any unprocessed data bits for a partial variable length symbol exist in a first data block is made. A shift merge operation is performed to merge the unprocessed data bits from the first data block with a second data block. A merged data block is formed. A merged variable length symbol comprised of the unprocessed data bits and a plurality of data bits from the second data block is extracted from the merged data block.

9. 发明申请

US20130145120A1 Bitstream Buffer Manipulation With A SIMD Merge Instruction 有权
公开(公告)号：US20130145120A1
公开(公告)日：2013-06-06
申请号：US13752953
申请日：2013-01-29
申请人： Yen-Kueng Chen , William W. Macy, Jr. , Matthew Holliman , Eric L. Debes , Minerva M. Yeung
发明人： Yen-Kueng Chen , William W. Macy, Jr. , Matthew Holliman , Eric L. Debes , Minerva M. Yeung
IPC分类号： G06F15/80
CPC分类号： G06F9/30145 , G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F9/30112 , G06F9/3013 , G06F9/3816 , G06F9/3885 , G06F15/8007 , G06F17/147 , G06F17/15
摘要： Method, apparatus, and program means for performing bitstream buffer manipulation with a SIMD merge instruction. The method of one embodiment comprises determining whether any unprocessed data bits for a partial variable length symbol exist in a first data block is made. A shift merge operation is performed to merge the unprocessed data bits from the first data block with a second data block. A merged data block is formed. A merged variable length symbol comprised of the unprocessed data bits and a plurality of data bits from the second data block is extracted from the merged data block.

10. 发明申请

US20130124824A1 Bitstream Buffer Manipulation With A SIMD Merge Instruction 有权
公开(公告)号：US20130124824A1
公开(公告)日：2013-05-16
申请号：US13727742
申请日：2012-12-27
申请人： Yen-Kueng Chen , William W. Macy , Matthew Holliman , Eric L. Debes , Minerva M. Yeung
发明人： Yen-Kueng Chen , William W. Macy , Matthew Holliman , Eric L. Debes , Minerva M. Yeung
IPC分类号： G06F15/80
CPC分类号： G06F9/30145 , G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F9/30112 , G06F9/3013 , G06F9/3816 , G06F9/3885 , G06F15/8007 , G06F17/147 , G06F17/15
摘要： Method, apparatus, and program means for performing bitstream buffer manipulation with a SIMD merge instruction. The method of one embodiment comprises determining whether any unprocessed data bits for a partial variable length symbol exist in a first data block is made. A shift merge operation is performed to merge the unprocessed data bits from the first data block with a second data block. A merged data block is formed. A merged variable length symbol comprised of the unprocessed data bits and a plurality of data bits from the second data block is extracted from the merged data block.

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