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    • 1. 发明申请
      US20110102121A1 SHEET TRANSFORMER FOR DC/DC CONVERTER 审中-公开
    • SHEET TRANSFORMER FOR DC/DC CONVERTER
    • 用于DC / DC转换器的板式变压器
    • US20110102121A1
    • 2011-05-05
    • US13000756
    • 2009-07-02
    • Yasunori Otsuka , Takashi Osawa , Fumihiro Minami
    • Yasunori Otsuka , Takashi Osawa , Fumihiro Minami
    • H01F27/29 , H01F5/00
    • H01F27/2804 , H01F27/06 , H01F27/266 , H01F2027/065 , H01F2027/2857
    • A sheet transformer includes a first core having central and lateral legs penetrating a coil on a circuit board, a plate-shaped second core positioned on an end of the first core, the cores being assembled into an integral piece and an air gap being formed between the central leg and the second core, and a fixing member for fixing the cores with respect to the coil. The fixing member has holder portions having claw portions for holding the lateral legs of the first core from a side of the second core respectively, a first spring portion extending from a side of the second core toward the circuit board, for bringing inner plane portions of the legs of the first core into contact with the coil, and a second spring portion for pressing positions of the second core which are opposite to the lateral legs.
    • 片状变压器包括具有穿过电路板上的线圈的中心和外侧腿的第一铁心，位于第一铁心端部的板状第二铁心，铁芯组装成整体件， 中心腿和第二芯，以及用于相对于线圈固定芯的固定构件。 所述固定部件具有保持部，所述保持部具有用于分别从所述第二芯侧保持所述第一芯的侧支脚的爪部，所述第一弹簧部从所述第二芯侧朝向所述电路基板延伸， 所述第一芯体的所述腿与所述线圈接触;以及第二弹簧部分，用于按压与所述侧腿相对的所述第二芯部的位置。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 4. 发明授权
      US5557779A Method for distributing a clock signal within a semiconductor integrated circuit by minimizing clock skew 失效
    • Method for distributing a clock signal within a semiconductor integrated circuit by minimizing clock skew
    • 通过最小化时钟偏移来在半导体集成电路内分配时钟信号的方法
    • US5557779A
    • 1996-09-17
    • US417232
    • 1995-04-05
    • Fumihiro Minami
    • Fumihiro Minami
    • H01L21/82 , G06F1/10 , G06F17/50 , H01L27/02 , G06F15/00
    • H01L27/0207 , G06F1/10 , G06F17/5077 , G06F2217/62
    • A control-signal distributing method used in a wiring-pattern network such that a control signal is supplied from root driver cells via repeating buffer cells to terminal cells. The method comprises the steps of: grouping the terminal cells into clusters containing at least one of the terminal cells, forming a binary-tree-shaped wiring pattern path where the root driver cells are root nodes and the clusters are leaf nodes, inserting the repeating buffer cells into the wiring pattern path at which delay time required for control signal transmission in the binary-tree-shaped path is minimized, calculating first delay amounts in a signal path defined from a branch node at a low level of the binary-tree-shaped path to the leaf nodes, setting physical positions of the branch nodes such that a difference among the calculated first delay amounts is minimized, separating the overlapped terminal cells from each other on the binary-tree-shaped path by updating previous information about a circuit connection when the repeating buffer cells are inserted and by correcting arrangement information about terminal cell positions adjacent to the buffer cells, determining a final wiring-pattern path within each of the clusters based upon the corrected arrangement information, calculating second delay amounts in the clusters based on the finally determined wiring-pattern path, determining respective branch node positions based on the second delay amounts, and determining a final wiring-pattern path among the branch nodes.
    • 一种在布线图案网络中使用的控制信号分配方法，使得从根驱动器单元经由重复缓冲器单元向终端单元提供控制信号。 该方法包括以下步骤：将终端小区分组成包含至少一个终端小区的簇，形成二进制树形布线模式路径，其中根驱动单元是根节点，簇是叶节点，插入重复 在二叉树形路径中的控制信号传输所需的延迟时间最小化的布线图案路径中，计算从二进制树形路径的低电平处的分支节点定义的信号路径中的第一延迟量， 设置叶节点的形状路径，设置分支节点的物理位置，使得计算的第一延迟量之间的差异最小化，通过更新关于电路的先前信息在二叉树形路径上将重叠的终端单元彼此分开 连接，并且通过校正与缓冲单元相邻的终端单元位置的布置信息，确定fina 基于校正的布置信息，在每个簇内的布线图案路径，基于最终确定的布线图案路径计算簇中的第二延迟量，基于第二延迟量确定各个分支节点位置，以及确定最终 分支节点之间的布线图案路径。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 5. 发明授权
      US5410491A Method for distributing a clock signal within a semiconductor integrated circuit by minimizing clock skew 失效
    • Method for distributing a clock signal within a semiconductor integrated circuit by minimizing clock skew
    • 通过最小化时钟偏移来在半导体集成电路内分配时钟信号的方法
    • US5410491A
    • 1995-04-25
    • US896618
    • 1992-06-10
    • Fumihiro Minami
    • Fumihiro Minami
    • H01L21/82 , G06F1/10 , G06F17/50 , H01L27/02 , G06F15/46
    • H01L27/0207 , G06F1/10 , G06F17/5077 , G06F2217/62
    • A clock-signal distributing method used in a wiring-pattern network such that a clock signal is supplied from root driver cells via repeating buffer cells to terminal cells. The method comprises the steps of: grouping the terminal cells into clusters containing at least one of the terminal cells, forming a binary-tree-shaped wiring pattern path where the root driver cells are root nodes and the clusters are leaf nodes, inserting the repeating buffer cells into the wiring pattern path at which delay time required for clock signal transmission in the binary-tree-shaped path is minimized, calculating first delay amounts in a signal path defined from a branch node at a low level of the binary-tree-shaped path to the leaf nodes, setting physical positions of the branch nodes such that a difference among the calculated first delay amounts is minimized, separating the overlapped terminal cells from each other on the binary-tree-shaped path by updating previous information about a circuit connection when the repeating buffer cells are inserted and by correcting arrangement information about terminal cell positions adjacent to the buffer cells, determining a final wiring-pattern path within each of the clusters based upon the corrected arrangement information, calculating second delay amounts in the clusters based on the finally determined wiring-pattern path, determining respective branch node positions based on the second delay amounts, and determining a final wiring-pattern path among the branch nodes.
    • 在布线图形网络中使用的时钟信号分配方法，使得时钟信号从根驱动器单元通过重复缓冲器单元提供给终端单元。 该方法包括以下步骤：将终端小区分组成包含至少一个终端小区的簇，形成二进制树形布线模式路径，其中根驱动单元是根节点，簇是叶节点，插入重复 将二进制树形路径中的时钟信号传输所需的延迟时间最小化的布线图案路径中的缓冲单元计算到从二叉树形路径的低级别的分支节点定义的信号路径中的第一延迟量， 设置叶节点的形状路径，设置分支节点的物理位置，使得计算的第一延迟量之间的差异最小化，通过更新关于电路的先前信息在二叉树形路径上将重叠的终端单元彼此分开 并且通过校正与缓冲单元相邻的终端单元位置的布置信息，确定最终的结果 基于校正的布置信息，在每个簇内的布线图形路径，基于最终确定的布线图案路径计算簇中的第二延迟量，基于第二延迟量确定相应的分支节点位置，以及确定最终布线 分支节点之间的模式路径。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 6. 发明授权
      US5124273A Automatic wiring method for semiconductor integrated circuit devices 失效
    • Automatic wiring method for semiconductor integrated circuit devices
    • 半导体集成电路器件的自动布线方法
    • US5124273A
    • 1992-06-23
    • US691613
    • 1991-02-27
    • Fumihiro Minami
    • Fumihiro Minami
    • G06F17/50
    • G06F17/5077
    • A computer-assisted automatic wiring method is presented for logic LSI substrates wherein channel boundary terminals are defined on the boundary line of the first and second channels forming a T-shaped crossing region between the function blocks arranged on a substrate after global wiring process. These channel boundary terminals are roughly divided into the first and second terminal groups there may remain channel boundary terminals which do not belong to any one of the groups. The first terminal group includes terminals intersecting wirings which tend to run along the first direction in the second channel, which corresponds to a top bar of the letter "T". The second terminal group includes terminals intersecting wirings which have tend to run along the second direction opposite to the first direction in said second channel. A pair of channel boundary terminals is sequentially selected from the first and second groups. Typically, the same wiring track is assigned to two wirings associated with the selected each pair of terminals in the second channel.
    • 提出了一种用于逻辑LSI基板的计算机辅助自动布线方法，其中通道边界端子限定在第一和第二通道的边界线上，在全局布线处理之后在布置在基板上的功能块之间形成T形交叉区域。 这些信道边界终端大致分为第一和第二终端组，可以保留不属于任一组的信道边界终端。 第一端子组包括在第二通道中沿着第一方向行进的布线相交的端子，其对应于字母“T”的顶部栏。 第二端子组包括沿着与所述第二通道中的第一方向相反的第二方向延伸的布线相交的端子。 从第一组和第二组顺序选择一对通道边界终端。 通常，将相同的接线轨迹分配给与第二通道中所选择的每对端子相关联的两个布线。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
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