专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06813756B2 Method of automatic layout design for LSI, mask set and semiconductor integrated circuit manufactured by automatic layout design method, and recording medium storing automatic layout design program 失效
标题翻译：通过自动布局设计方法制造的LSI，掩模组和半导体集成电路的自动布局设计方法以及存储自动布局设计程序的记录介质
公开(公告)号：US06813756B2
公开(公告)日：2004-11-02
申请号：US10279403
申请日：2002-10-24
申请人： Mutsunori Igarashi , Masami Murakata , Takashi Mitsuhashi , Masaaki Yamada , Fumihiro Minami , Takashi Ishioka
发明人： Mutsunori Igarashi , Masami Murakata , Takashi Mitsuhashi , Masaaki Yamada , Fumihiro Minami , Takashi Ishioka
IPC分类号： G06F1750
CPC分类号： H01L23/528 , G06F1/10 , G06F17/5077 , H01L2924/0002 , H01L2924/00
摘要： With an automatic layout method, a first line having a first line width is generated in a prescribed direction. A second line having a second line width and extending at an oblique angle with respect to the first line is generated, so that the second line terminates at an end portion of the first line with an overlapped area. One or more VIA patterns are read out of a database according to the shape of the overlapped area. The VIA patterns are placed in the overlapped area, so that one of the VIA patterns is located at the intersection of the center lines of the first and second lines. The VIA pattern is a combination of parallelograms, including squares and rectangles.
摘要翻译：利用自动布局方法，在规定的方向上产生具有第一线宽的第一线。产生具有第二线宽并相对于第一线以倾斜角延伸的第二线，使得第二线终止于第一线的端部处，具有重叠区域。根据重叠区域的形状，从数据库读出一个或多个VIA图案。 VIA图案被放置在重叠区域中，使得VIA图案之一位于第一和第二行的中心线的交叉处。 VIA模式是平行四边形的组合，包括正方形和矩形。

2. 发明授权

US06546540B1 Method of automatic layout design for LSI, mask set and semiconductor integrated circuit manufactured by automatic layout design method, and recording medium storing automatic layout design program 失效
标题翻译：通过自动布局设计方法制造的LSI，掩模组和半导体集成电路的自动布局设计方法以及存储自动布局设计程序的记录介质
公开(公告)号：US06546540B1
公开(公告)日：2003-04-08
申请号：US09713050
申请日：2000-11-15
申请人： Mutsunori Igarashi , Masami Murakata , Takashi Mitsuhashi , Masaaki Yamada , Fumihiro Minami , Takashi Ishioka
发明人： Mutsunori Igarashi , Masami Murakata , Takashi Mitsuhashi , Masaaki Yamada , Fumihiro Minami , Takashi Ishioka
IPC分类号： G06F1750
CPC分类号： H01L23/528 , G06F1/10 , G06F17/5077 , H01L2924/0002 , H01L2924/00
摘要： With an automatic layout method, a first line having a firs line width is generated in a prescribed direction. A second line having a second line width and extending at an oblique angle with respect to the first line is generated, so that the second line terminates at an end portion of the first line with an overlapped area. One or more VIA patterns are read out of a database according to the shape of the overlapped area. The VIA patterns are placed in the overlapped area, so that one of the VIA patterns is located at the intersection of the center lines of the first and second lines. The VIA pattern is a combination of parallelograms, including squares and rectangles.
摘要翻译：利用自动布局方法，在规定的方向上产生具有第一线宽的第一线。产生具有第二线宽并相对于第一线以倾斜角延伸的第二线，使得第二线终止于第一线的端部处，具有重叠区域。根据重叠区域的形状，从数据库读出一个或多个VIA图案。 VIA图案被放置在重叠区域中，使得VIA图案之一位于第一和第二行的中心线的交叉处。 VIA模式是平行四边形的组合，包括正方形和矩形。

3. 发明授权

US06436804B1 Semiconductor integrated circuit device, semiconductor integrated circuit wiring method, and cell arranging method 有权
公开(公告)号：US06436804B1
公开(公告)日：2002-08-20
申请号：US09810579
申请日：2001-03-19
申请人： Mutsunori Igarashi , Takashi Mitsuhashi , Masami Murakata , Masaaki Yamada , Fumihiro Minami , Toshihiro Akiyama , Takahiro Aoki
发明人： Mutsunori Igarashi , Takashi Mitsuhashi , Masami Murakata , Masaaki Yamada , Fumihiro Minami , Toshihiro Akiyama , Takahiro Aoki
IPC分类号： H01L2144
摘要： There are disclosed a semiconductor integrated circuit device, a semiconductor integrated circuit wiring method and a cell arranging method, which can reduce delay in a semiconductor integrated circuit and improve noise resistibility, achieve facility of wiring design, and reduce production cost. The present invention forms an X-Y reference wiring grid using wirings of a total of M (M≧2) layers in which an n-th (n≧2) layer wiring intersects orthogonally with a (n−1)-th layer wiring, and forms an oblique wiring grid which intersects with the reference wiring layer to have an angle of 45 degree or 135 degree is formed by a (m+1)-th layer wiring and a (m+2)-th layer wiring which are intersected orthogonally with each other, such that the(m+1)-th layer wiring and(m+2)-th layer wiring in the oblique wiring grid has a wiring pitch of {square root over (2)} times of that of wiring in the reference wiring grid, and also wiring widths of {square root over (2)} times of that of wiring in the reference wiring layer.

4. 发明授权

US06645842B2 Semiconductor integrated circuit device, semiconductor integrated circuit wiring method, and cell arranging method 失效
标题翻译：半导体集成电路器件，半导体集成电路布线方法和电池布置方法
公开(公告)号：US06645842B2
公开(公告)日：2003-11-11
申请号：US10196928
申请日：2002-07-18
申请人： Mutsunori Igarashi , Takashi Mitsuhashi , Masami Murakata , Masaaki Yamada , Fumihiro Minami , Toshihiro Akiyama , Takahiro Aoki
发明人： Mutsunori Igarashi , Takashi Mitsuhashi , Masami Murakata , Masaaki Yamada , Fumihiro Minami , Toshihiro Akiyama , Takahiro Aoki
IPC分类号： H01L2144
CPC分类号： H01L23/5286 , H01L23/5222 , H01L23/528 , H01L27/0203 , H01L27/10882 , H01L2924/0002 , H01L2924/00
摘要： There are disclosed a semiconductor integrated circuit device, a semiconductor integrated circuit wiring method and a cell arranging method, which can reduce delay in a semiconductor integrated circuit and improve noise resistibility, achieve facility of wiring design, and reduce production cost. The present invention forms an X-Y reference wiring grid using wirings of a total of M (M≧2) layers in which an n-th (n≧2) layer wiring intersects orthogonally with a (n−1)-th layer wiring, and forms an oblique wiring grid which intersects with the reference wiring layer to have an angle of 45 degree or 135 degree is formed by a (m+1)-th layer wiring and a (m+2)-th layer wiring which are intersected orthogonally with each other, such that the (m+1)-th layer wiring and (m+2)-th layer wiring in the oblique wiring grid has a wiring pitch of {square root over ( )}2 times of that of wiring in the reference wiring grid, and also wiring widths of {square root over ( )}2 times of that of wiring in the reference wiring layer.
摘要翻译：公开了半导体集成电路器件，半导体集成电路布线方法和单元布置方法，其可以减少半导体集成电路的延迟并提高抗噪声性，实现布线设计，降低生产成本。本发明形式使用总共M（M> = 2）层的布线的XY参考布线栅格，其中第n（n> = 2）层布线与第（n-1）层布线正交地相交，并形成通过第（m + 1）层布线和（m + 2）层布线与每个正交相交的第（m + 2）层布线形成与参考布线层相交的具有45度或135度角的倾斜布线栅格另外，斜交线栅格中的第（m + 1）层布线和第（m + 2）层布线具有{平方根以上的布线间距（参考布线栅中的布线的2倍），以及{平方根的布线宽度（参考中的布线的2倍）连接布线层。

5. 发明授权

US06262487B1 Semiconductor integrated circuit device, semiconductor integrated circuit wiring method, and cell arranging method 失效
标题翻译：半导体集成电路器件，半导体集成电路布线方法和电池布置方法
公开(公告)号：US06262487B1
公开(公告)日：2001-07-17
申请号：US09338593
申请日：1999-06-23
申请人： Mutsunori Igarashi , Takashi Mitsuhashi , Masami Murakata , Masaaki Yamada , Fumihiro Minami , Toshihiro Akiyama , Takahiro Aoki
发明人： Mutsunori Igarashi , Takashi Mitsuhashi , Masami Murakata , Masaaki Yamada , Fumihiro Minami , Toshihiro Akiyama , Takahiro Aoki
IPC分类号： H01L2348
CPC分类号： H01L23/5286 , H01L23/5222 , H01L23/528 , H01L27/0203 , H01L27/10882 , H01L2924/0002 , H01L2924/00
摘要： There are disclosed a semiconductor integrated circuit device, a semiconductor integrated circuit wiring method and a cell arranging method, which can reduce delay in a semiconductor integrated circuit and improve noise resistibility., achieve facility of wiring design, and reduce production cost. The present invention forms a X-Y reference wiring grid using wirings of a total of M (M≧2) layers in which an n-th (n≧2) layer wiring intersects orthogonally with a (n−1)-th layer wiring, and forms an oblique wiring grid which intersects with the reference wiring layer to have an angle of 45 degree or 135 degree is formed by a (m+1)-th layer wiring and a (m+2)-th layer wiring which are intersected orthogonally with each other, such that the(m+1)-th layer wiring and(m+2)-th layer wiring in the oblique wiring grid has a wiring pitch of {square root over (2)} times of that of wiring in the reference wiring grid, and also wiring widths of {square root over (2)} times of that of wiring in the reference wiring layer.
摘要翻译：公开了半导体集成电路器件，半导体集成电路布线方法和单元布置方法，其可以减少半导体集成电路的延迟并提高抗噪声性，实现布线设计的设计，并降低生产成本。本发明使用其中n（n> = 2）层布线与第（n-1）层布线正交相交的总共M（M> = 2）层的布线形成XY参考布线栅格，并形成通过与第（m + 1）层布线和第（m + 2）层布线正交地相交的第（m + 2）层布线，形成与参考布线层相交的具有45度或135度角的斜线布线，使得斜线栅格中的第（m + 1）层布线和第（m + 2）层布线在布线中的布线间距大于（2）}倍的布线间距参考线路，以及线路布线的{平方根超过（2）}倍的布线宽度布线层。

6. 发明授权

US07075336B2 Method for distributing clock signals to flip-flop circuits 失效
公开(公告)号：US07075336B2
公开(公告)日：2006-07-11
申请号：US10184425
申请日：2002-06-28
申请人： Naohito Kojima , Fumihiro Minami , Masami Murakata , Takashi Ishioka
发明人： Naohito Kojima , Fumihiro Minami , Masami Murakata , Takashi Ishioka
IPC分类号： H03K19/00 , H03K19/096 , G06F9/45 , G06F17/50 , G06F1/12
CPC分类号： G06F17/5045 , G06F1/10
摘要： A method for distributing clocks to flip-flop circuits which constitute a logic circuit includes obtaining a timing slack of a first minimum delay time with respect to a minimum delay constraint time and a timing slack of a first maximum delay time with respect to a maximum delay constraint time for a clock in an input path to a flip-flop circuit, obtaining a timing slack of a second minimum delay time with respect to a minimum delay constraint time and a timing slack of a second maximum delay time with respect to a maximum delay constraint time for a clock in an output path from all the flip-flop circuits which receive the clocks from a clock terminal directly and obtaining a delay value which maximizes a minimum value of each of the first and second minimum delay time and maximum delay time of timing slacks.

7. 发明授权

US5801960A Layout method of wiring pattern for semiconductor integrated circuit 失效
标题翻译：半导体集成电路接线图布局方法
公开(公告)号：US5801960A
公开(公告)日：1998-09-01
申请号：US963311
申请日：1997-11-03
申请人： Midori Takano , Fumihiro Minami , Mutsunori Igarashi
发明人： Midori Takano , Fumihiro Minami , Mutsunori Igarashi
IPC分类号： H01L21/82 , G06F17/50
CPC分类号： G06F17/5077
摘要： A layout method of designing a wiring pattern on a semiconductor integrated circuit chip according to the present invention comprises three steps of omitting a part of or all of a wiring pattern within cells for a plurality of circuit elements for layout results of these predetermined circuit elements to prepare wiring obstruction data (step 1); deciding a specific wiring path connecting between the cells with reference to the prepared wiring obstruction data (step 2); and repositioning of the cell to correct the layout with no design rule violation and no short between this specific wiring path and the wiring pattern within cells (step 3). The pattern layout is performed so that the specific wiring path is wired in the shortest length of wiring path without making a snaking wire path and also uncomplete wiring does not happen to occur.
摘要翻译：根据本发明的在半导体集成电路芯片上设计布线图案的布置方法包括以下三个步骤：省略用于多个电路元件的单元内的布线图案的一部分或全部，用于将这些预定电路元件的布局结果准备接线障碍物数据（步骤1）; 参照准备好的布线障碍物数据确定连接单元之间的具体布线路径（步骤2）; 并且重新定位单元以校正布局，而没有设计规则违反，并且在该特定布线路径和单元内的布线图案之间没有短路（步骤3）。执行图案布局，使得特定布线路径布线在布线路径的最短长度中，而不会产生蛇线路，并且也不会发生不完全布线。

8. 发明申请

US20140340923A1 LIGHT SOURCE FOR HEADLIGHT AND HEADLIGHT 有权
标题翻译：头灯和头灯的光源
公开(公告)号：US20140340923A1
公开(公告)日：2014-11-20
申请号：US14365889
申请日：2012-03-06
申请人： Fumihiro Minami , Javier Escobar , Takashi Ohsawa
发明人： Fumihiro Minami , Javier Escobar , Takashi Ohsawa
IPC分类号： F21S8/10 , F21K99/00
CPC分类号： F21S41/20 , F21S41/14 , F21S41/147 , F21S41/16 , F21S41/255 , F21S41/285 , F21S41/321 , F21S41/36 , F21S41/365 , F21S41/43 , F21S41/60 , F21S41/663 , F21S45/47
摘要： In an LED2 having a directionality in an emission direction of emitted light, light emitted from a light emitting surface of the LED 2 is refracted by a semi-cylindrical concave lens 3 to be enlarged in the circumference direction of an optical axis of a headlight 1; thus, even when the LED2 is applied to a headlight that is constituted by optical members that are similar to optical members that are compatible with conventional light sources having no directionality, such as an incandescent lamp, a discharge lamp and the like, it can be used as a light source for headlight that is capable of illuminating the right and left directions ahead of a vehicle with a sufficient brightness.
摘要翻译：在具有发射光的发射方向的方向性的LED2中，从LED2的发光面发射的光被半圆柱形凹透镜3折射，以在头灯1的光轴的圆周方向上扩大 ; 因此，即使将LED2应用于由与诸如白炽灯，放电灯等的不具有方向性的常规光源兼容的光学部件相似的光学部件构成的前照灯，也可以是用作能够以足够的亮度照亮车辆前方左右方向的头灯的光源。

9. 发明授权

US5557779A Method for distributing a clock signal within a semiconductor integrated circuit by minimizing clock skew 失效
标题翻译：通过最小化时钟偏移来在半导体集成电路内分配时钟信号的方法
公开(公告)号：US5557779A
公开(公告)日：1996-09-17
申请号：US417232
申请日：1995-04-05
申请人： Fumihiro Minami
发明人： Fumihiro Minami
IPC分类号： H01L21/82 , G06F1/10 , G06F17/50 , H01L27/02 , G06F15/00
CPC分类号： H01L27/0207 , G06F1/10 , G06F17/5077 , G06F2217/62
摘要： A control-signal distributing method used in a wiring-pattern network such that a control signal is supplied from root driver cells via repeating buffer cells to terminal cells. The method comprises the steps of: grouping the terminal cells into clusters containing at least one of the terminal cells, forming a binary-tree-shaped wiring pattern path where the root driver cells are root nodes and the clusters are leaf nodes, inserting the repeating buffer cells into the wiring pattern path at which delay time required for control signal transmission in the binary-tree-shaped path is minimized, calculating first delay amounts in a signal path defined from a branch node at a low level of the binary-tree-shaped path to the leaf nodes, setting physical positions of the branch nodes such that a difference among the calculated first delay amounts is minimized, separating the overlapped terminal cells from each other on the binary-tree-shaped path by updating previous information about a circuit connection when the repeating buffer cells are inserted and by correcting arrangement information about terminal cell positions adjacent to the buffer cells, determining a final wiring-pattern path within each of the clusters based upon the corrected arrangement information, calculating second delay amounts in the clusters based on the finally determined wiring-pattern path, determining respective branch node positions based on the second delay amounts, and determining a final wiring-pattern path among the branch nodes.
摘要翻译：一种在布线图案网络中使用的控制信号分配方法，使得从根驱动器单元经由重复缓冲器单元向终端单元提供控制信号。该方法包括以下步骤：将终端小区分组成包含至少一个终端小区的簇，形成二进制树形布线模式路径，其中根驱动单元是根节点，簇是叶节点，插入重复在二叉树形路径中的控制信号传输所需的延迟时间最小化的布线图案路径中，计算从二进制树形路径的低电平处的分支节点定义的信号路径中的第一延迟量，设置叶节点的形状路径，设置分支节点的物理位置，使得计算的第一延迟量之间的差异最小化，通过更新关于电路的先前信息在二叉树形路径上将重叠的终端单元彼此分开连接，并且通过校正与缓冲单元相邻的终端单元位置的布置信息，确定fina 基于校正的布置信息，在每个簇内的布线图案路径，基于最终确定的布线图案路径计算簇中的第二延迟量，基于第二延迟量确定各个分支节点位置，以及确定最终分支节点之间的布线图案路径。

10. 发明授权

US5410491A Method for distributing a clock signal within a semiconductor integrated circuit by minimizing clock skew 失效
标题翻译：通过最小化时钟偏移来在半导体集成电路内分配时钟信号的方法
公开(公告)号：US5410491A
公开(公告)日：1995-04-25
申请号：US896618
申请日：1992-06-10
申请人： Fumihiro Minami
发明人： Fumihiro Minami
IPC分类号： H01L21/82 , G06F1/10 , G06F17/50 , H01L27/02 , G06F15/46
CPC分类号： H01L27/0207 , G06F1/10 , G06F17/5077 , G06F2217/62
摘要： A clock-signal distributing method used in a wiring-pattern network such that a clock signal is supplied from root driver cells via repeating buffer cells to terminal cells. The method comprises the steps of: grouping the terminal cells into clusters containing at least one of the terminal cells, forming a binary-tree-shaped wiring pattern path where the root driver cells are root nodes and the clusters are leaf nodes, inserting the repeating buffer cells into the wiring pattern path at which delay time required for clock signal transmission in the binary-tree-shaped path is minimized, calculating first delay amounts in a signal path defined from a branch node at a low level of the binary-tree-shaped path to the leaf nodes, setting physical positions of the branch nodes such that a difference among the calculated first delay amounts is minimized, separating the overlapped terminal cells from each other on the binary-tree-shaped path by updating previous information about a circuit connection when the repeating buffer cells are inserted and by correcting arrangement information about terminal cell positions adjacent to the buffer cells, determining a final wiring-pattern path within each of the clusters based upon the corrected arrangement information, calculating second delay amounts in the clusters based on the finally determined wiring-pattern path, determining respective branch node positions based on the second delay amounts, and determining a final wiring-pattern path among the branch nodes.
摘要翻译：在布线图形网络中使用的时钟信号分配方法，使得时钟信号从根驱动器单元通过重复缓冲器单元提供给终端单元。该方法包括以下步骤：将终端小区分组成包含至少一个终端小区的簇，形成二进制树形布线模式路径，其中根驱动单元是根节点，簇是叶节点，插入重复将二进制树形路径中的时钟信号传输所需的延迟时间最小化的布线图案路径中的缓冲单元计算到从二叉树形路径的低级别的分支节点定义的信号路径中的第一延迟量，设置叶节点的形状路径，设置分支节点的物理位置，使得计算的第一延迟量之间的差异最小化，通过更新关于电路的先前信息在二叉树形路径上将重叠的终端单元彼此分开并且通过校正与缓冲单元相邻的终端单元位置的布置信息，确定最终的结果基于校正的布置信息，在每个簇内的布线图形路径，基于最终确定的布线图案路径计算簇中的第二延迟量，基于第二延迟量确定相应的分支节点位置，以及确定最终布线分支节点之间的模式路径。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式