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1. 发明授权

US08314455B2 Non-volatile semiconductor storage device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08314455B2
公开(公告)日：2012-11-20
申请号：US13156727
申请日：2011-06-09
申请人： Yasuhiro Shiino , Atsuhiro Sato , Takeshi Kamigaichi , Fumitaka Arai
发明人： Yasuhiro Shiino , Atsuhiro Sato , Takeshi Kamigaichi , Fumitaka Arai
IPC分类号： H01L29/792
CPC分类号： H01L27/11578 , H01L27/11573 , H01L27/11582
摘要： A non-volatile semiconductor storage device includes: a memory cell area in which a plurality of electrically rewritable memory cells are formed; and a peripheral circuit area in which transistors that configure peripheral circuits to control the memory cells are formed. The memory cell area has formed therein: a semiconductor layer formed to extend in a vertical direction to a semiconductor substrate; a plurality of conductive layers extending in a parallel direction to, and laminated in a vertical direction to the semiconductor substrate; and a property-varying layer formed between the semiconductor layer and the conductive layers and having properties varying depending on a voltage applied to the conductive layers. The peripheral circuit area has formed therein a plurality of dummy wiring layers that are formed on the same plane as each of the plurality of conductive layers and that are electrically separated from the conductive layers.
摘要翻译：非易失性半导体存储装置包括：形成有多个电可重写存储单元的存储单元区域; 以及外围电路区域，其中形成配置外围电路以控制存储单元的晶体管。在其中形成存储单元区域：形成为在垂直方向上延伸到半导体衬底的半导体层; 多个导电层，沿着与半导体基板的垂直方向平行的方向延伸并层叠; 以及形成在所述半导体层和所述导电层之间的性质变化层，并且具有根据施加到所述导电层的电压而变化的特性。外围电路区域中形成有多个虚拟布线层，其形成在与多个导电层中的每一个相同的平面上，并且与导电层电分离。

2. 发明授权

US07977733B2 Non-volatile semiconductor storage device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US07977733B2
公开(公告)日：2011-07-12
申请号：US12394929
申请日：2009-02-27
申请人： Yasuhiro Shiino , Atsuhiro Sato , Takeshi Kamigaichi , Fumitaka Arai
发明人： Yasuhiro Shiino , Atsuhiro Sato , Takeshi Kamigaichi , Fumitaka Arai
IPC分类号： H01L29/792
CPC分类号： H01L27/11578 , H01L27/11573 , H01L27/11582
摘要： A non-volatile semiconductor storage device includes: a memory cell area in which a plurality of electrically rewritable memory cells are formed; and a peripheral circuit area in which transistors that configure peripheral circuits to control the memory cells are formed. The memory cell area has formed therein: a semiconductor layer formed to extend in a vertical direction to a semiconductor substrate; a plurality of conductive layers extending in a parallel direction to, and laminated in a vertical direction to the semiconductor substrate; and a property-varying layer formed between the semiconductor layer and the conductive layers and having properties varying depending on a voltage applied to the conductive layers. The peripheral circuit area has formed therein a plurality of dummy wiring layers that are formed on the same plane as each of the plurality of conductive layers and that are electrically separated from the conductive layers.
摘要翻译：非易失性半导体存储装置包括：形成有多个电可重写存储单元的存储单元区域; 以及外围电路区域，其中形成配置外围电路以控制存储单元的晶体管。在其中形成存储单元区域：形成为在垂直方向上延伸到半导体衬底的半导体层; 多个导电层，沿着与半导体基板的垂直方向平行的方向延伸并层叠; 以及形成在所述半导体层和所述导电层之间的性质变化层，并且具有根据施加到所述导电层的电压而变化的特性。外围电路区域中形成有多个虚拟布线层，其形成在与多个导电层中的每一个相同的平面上，并且与导电层电分离。

3. 发明申请

US20090230450A1 NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：非挥发性半导体存储器件
公开(公告)号：US20090230450A1
公开(公告)日：2009-09-17
申请号：US12394929
申请日：2009-02-27
申请人： Yasuhiro Shiino , Atsuhiro Sato , Takeshi Kamigaichi , Fumitaka Arai
发明人： Yasuhiro Shiino , Atsuhiro Sato , Takeshi Kamigaichi , Fumitaka Arai
IPC分类号： H01L29/788 , H01L21/20
CPC分类号： H01L27/11578 , H01L27/11573 , H01L27/11582
摘要： A non-volatile semiconductor storage device includes: a memory cell area in which a plurality of electrically rewritable memory cells are formed; and a peripheral circuit area in which transistors that configure peripheral circuits to control the memory cells are formed. The memory cell area has formed therein: a semiconductor layer formed to extend in a vertical direction to a semiconductor substrate; a plurality of conductive layers extending in a parallel direction to, and laminated in a vertical direction to the semiconductor substrate; and a property-varying layer formed between the semiconductor layer and the conductive layers and having properties varying depending on a voltage applied to the conductive layers. The peripheral circuit area has formed therein a plurality of dummy wiring layers that are formed on the same plane as each of the plurality of conductive layers and that are electrically separated from the conductive layers.
摘要翻译：非易失性半导体存储装置包括：形成有多个电可重写存储单元的存储单元区域; 以及外围电路区域，其中形成配置外围电路以控制存储单元的晶体管。在其中形成存储单元区域：形成为在垂直方向上延伸到半导体衬底的半导体层; 多个导电层，沿着与半导体基板的垂直方向平行的方向延伸并层叠; 以及形成在所述半导体层和所述导电层之间的性质变化层，并且具有根据施加到所述导电层的电压而变化的特性。外围电路区域中形成有多个虚拟布线层，其形成在与多个导电层中的每一个相同的平面上，并且与导电层电分离。

4. 发明申请

US20100246255A1 NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR CONTROLLING THE SAME 失效
标题翻译：非易失性半导体存储装置及其控制方法
公开(公告)号：US20100246255A1
公开(公告)日：2010-09-30
申请号：US12729626
申请日：2010-03-23
申请人： Yasuhiro SHIINO , Atsuhiro Sato , Takeshi Kamigaichi
发明人： Yasuhiro SHIINO , Atsuhiro Sato , Takeshi Kamigaichi
IPC分类号： G11C16/28
CPC分类号： G11C16/30 , G11C7/14 , G11C16/0483 , G11C16/10 , G11C16/28 , H01L27/11519 , H01L27/11521
摘要： A nonvolatile semiconductor storage device includes a memory cell array and a peripheral circuit. The memory cell array includes active areas extending in a first direction, a dummy active area extending in the first direction, memory cells on the plurality of active areas, first dummy cells on the dummy active area, diffusion layer areas each connected to the corresponding memory cell and the corresponding first dummy cell, first contacts in the respective active areas, and a second contact in the dummy active area. The peripheral circuit includes a voltage applying unit configured to apply to each of the first contacts a first voltage to set each of the memory cells in a write enable state or a second voltage to set the memory cells in a write inhibit state, and to apply to the second contact a third voltage to change a threshold of the dummy cell.
摘要翻译：非易失性半导体存储装置包括存储单元阵列和外围电路。存储单元阵列包括沿第一方向延伸的有效区域，在第一方向上延伸的虚拟有源区域，多个有效区域上的存储单元，虚拟有效区域上的第一虚设单元，各自连接到对应存储器的扩散层区域单元和对应的第一虚拟单元，在相应的有效区域中首先接触，并且在虚拟活动区域中的第二触点。外围电路包括电压施加单元，其被配置为向每个第一触点施加第一电压，以将每个存储单元设置在写使能状态或第二电压以将存储单元设置在写禁止状态，并且应用向第二接触器施加第三电压以改变虚设电池的阈值。

5. 发明授权

US08270220B2 Nonvolatile semiconductor storage device and method for controlling the same 失效
标题翻译：非易失性半导体存储装置及其控制方法
公开(公告)号：US08270220B2
公开(公告)日：2012-09-18
申请号：US12729626
申请日：2010-03-23
申请人： Yasuhiro Shiino , Atsuhiro Sato , Takeshi Kamigaichi
发明人： Yasuhiro Shiino , Atsuhiro Sato , Takeshi Kamigaichi
IPC分类号： G11C16/06
CPC分类号： G11C16/30 , G11C7/14 , G11C16/0483 , G11C16/10 , G11C16/28 , H01L27/11519 , H01L27/11521
摘要： A nonvolatile semiconductor storage device includes a memory cell array and a peripheral circuit. The memory cell array includes active areas extending in a first direction, a dummy active area extending in the first direction, memory cells on the plurality of active areas, first dummy cells on the dummy active area, diffusion layer areas each connected to the corresponding memory cell and the corresponding first dummy cell, first contacts in the respective active areas, and a second contact in the dummy active area. The peripheral circuit includes a voltage applying unit configured to apply to each of the first contacts a first voltage to set each of the memory cells in a write enable state or a second voltage to set the memory cells in a write inhibit state, and to apply to the second contact a third voltage to change a threshold of the dummy cell.
摘要翻译：非易失性半导体存储装置包括存储单元阵列和外围电路。存储单元阵列包括沿第一方向延伸的有效区域，在第一方向上延伸的虚拟有源区域，多个有效区域上的存储单元，虚拟有效区域上的第一虚设单元，各自连接到对应存储器的扩散层区域单元和对应的第一虚拟单元，在相应的有效区域中首先接触，并且在虚拟活动区域中的第二触点。外围电路包括电压施加单元，其被配置为向每个第一触点施加第一电压，以将每个存储单元设置在写使能状态或第二电压以将存储单元设置在写禁止状态，并且应用向第二接触器施加第三电压以改变虚设电池的阈值。

6. 发明授权

US07796439B2 Semiconductor memory device and write method thereof 失效
标题翻译：半导体存储器件及其写入方法
公开(公告)号：US07796439B2
公开(公告)日：2010-09-14
申请号：US12017543
申请日：2008-01-22
申请人： Fumitaka Arai , Takeshi Kamigaichi , Atsuhiro Sato
发明人： Fumitaka Arai , Takeshi Kamigaichi , Atsuhiro Sato
IPC分类号： G11C11/34 , G11C11/06
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/3454 , G11C16/3459 , G11C2211/5621 , G11C2211/5622 , G11C2211/5642
摘要： A semiconductor memory device includes a memory cell array, bit lines, a source line, a sense amplifier, a data buffer, a voltage generating circuit, and a control circuit, the control circuit being configured such that the control circuit writes batchwise the write data, in the plurality of memory cells of the bit lines, the control circuit, after the batchwise write, causes the plurality of first latch circuits to hold the write data once again, and the control circuit executes verify read from the memory cells, and executes, in a case where read data of the plurality of sense amplifier circuits by the verify read disagree with the write data that are held once again in the plurality of first latch circuits, additional write to write batchwise the held write data in the plurality of memory cells once again.
摘要翻译：半导体存储器件包括存储单元阵列，位线，源极线，读出放大器，数据缓冲器，电压产生电路和控制电路，该控制电路被配置为使得控制电路分批写入写数据在位线的多个存储单元中，控制电路在分批写入之后使得多个第一锁存电路再次保持写入数据，并且控制电路执行从存储器单元的验证读取，并执行在通过验证读取的多个读出放大器电路的读取数据与在多个第一锁存电路中再次被保持的写入数据不同时的情况下，对多个存储器中的保持的写入数据进行分批写入细胞再次。

7. 发明申请

US20110233652A1 NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：非挥发性半导体存储器件
公开(公告)号：US20110233652A1
公开(公告)日：2011-09-29
申请号：US13156727
申请日：2011-06-09
申请人： Yasuhiro Shino , Atsuhiro Sato , Takeshi Kamigaichi , Fumitaka Arai
发明人： Yasuhiro Shino , Atsuhiro Sato , Takeshi Kamigaichi , Fumitaka Arai
IPC分类号： H01L27/115
CPC分类号： H01L27/11578 , H01L27/11573 , H01L27/11582
摘要： A non-volatile semiconductor storage device includes: a memory cell area in which a plurality of electrically rewritable memory cells are formed; and a peripheral circuit area in which transistors that configure peripheral circuits to control the memory cells are formed. The memory cell area has formed therein: a semiconductor layer formed to extend in a vertical direction to a semiconductor substrate; a plurality of conductive layers extending in a parallel direction to, and laminated in a vertical direction to the semiconductor substrate; and a property-varying layer formed between the semiconductor layer and the conductive layers and having properties varying depending on a voltage applied to the conductive layers. The peripheral circuit area has formed therein a plurality of dummy wiring layers that are formed on the same plane as each of the plurality of conductive layers and that are electrically separated from the conductive layers.
摘要翻译：非易失性半导体存储装置包括：形成有多个电可重写存储单元的存储单元区域; 以及外围电路区域，其中形成配置外围电路以控制存储单元的晶体管。在其中形成存储单元区域：形成为在垂直方向上延伸到半导体衬底的半导体层; 多个导电层，沿着与半导体基板的垂直方向平行的方向延伸并层叠; 以及形成在所述半导体层和所述导电层之间的性质变化层，并且具有根据施加到所述导电层的电压而变化的特性。外围电路区域中形成有多个虚拟布线层，其形成在与多个导电层中的每一个相同的平面上，并且与导电层电分离。

8. 发明申请

US20110143530A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20110143530A1
公开(公告)日：2011-06-16
申请号：US13033017
申请日：2011-02-23
申请人： Atsuhiro SATO , Fumitaka Arai , Yoshio Ozawa , Takeshi Kamigaichi
发明人： Atsuhiro SATO , Fumitaka Arai , Yoshio Ozawa , Takeshi Kamigaichi
IPC分类号： H01L21/3205
CPC分类号： H01L21/823462 , H01L27/105 , H01L27/1052 , H01L27/11526 , H01L27/11546 , H01L29/7881
摘要： A semiconductor memory device according to the present invention includes: a first transistor formed on a semiconductor substrate 11, the first transistor including a first gate-insulating film 14a that is oxynitrided; and a second transistor including a second gate-insulating film 14b formed on the semiconductor substrate 11 and a barrier film 20 formed at least partially on the second gate-insulating film 14b, the second gate-insulating film having a lower nitrogen atom concentration than the first gate-insulating film.
摘要翻译：根据本发明的半导体存储器件包括：形成在半导体衬底11上的第一晶体管，所述第一晶体管包括被氮氧化的第一栅极绝缘膜14a; 以及第二晶体管，包括形成在半导体衬底11上的第二栅极绝缘膜14b和至少部分地形成在第二栅极绝缘膜14b上的阻挡膜20，第二栅极绝缘膜具有比第一栅极绝缘膜。

9. 发明申请

US20080181009A1 SEMICONDUCTOR MEMORY DEVICE AND WRITE METHOD THEREOF 失效
标题翻译：半导体存储器件及其写入方法
公开(公告)号：US20080181009A1
公开(公告)日：2008-07-31
申请号：US12017543
申请日：2008-01-22
申请人： Fumitaka Arai , Takeshi Kamigaichi , Atsuhiro Sato
发明人： Fumitaka Arai , Takeshi Kamigaichi , Atsuhiro Sato
IPC分类号： G11C16/04 , G11C16/06 , G11C7/00
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/3454 , G11C16/3459 , G11C2211/5621 , G11C2211/5622 , G11C2211/5642
摘要： A semiconductor memory device includes a memory cell array, bit lines, a source line, a sense amplifier, a data buffer, a voltage generating circuit, and a control circuit, the control circuit being configured such that the control circuit writes batchwise the write data, in the plurality of memory cells of the bit lines, the control circuit, after the batchwise write, causes the plurality of first latch circuits to hold the write data once again, and the control circuit executes verify read from the memory cells, and executes, in a case where read data of the plurality of sense amplifier circuits by the verify read disagree with the write data that are held once again in the plurality of first latch circuits, additional write to write batchwise the held write data in the plurality of memory cells once again.
摘要翻译：半导体存储器件包括存储单元阵列，位线，源极线，读出放大器，数据缓冲器，电压产生电路和控制电路，该控制电路被配置为使得控制电路分批写入写数据在位线的多个存储单元中，控制电路在分批写入之后使得多个第一锁存电路再次保持写入数据，并且控制电路执行从存储器单元的验证读取，并执行在通过验证读取的多个读出放大器电路的读取数据与在多个第一锁存电路中再次被保持的写入数据不同时的情况下，对多个存储器中的保持的写入数据进行分批写入细胞再次。

10. 发明授权

US08279679B2 Non-volatile semiconductor memory device, method of reading data therefrom, and semiconductor device 有权
标题翻译：非挥发性半导体存储器件，从其读取数据的方法以及半导体器件
公开(公告)号：US08279679B2
公开(公告)日：2012-10-02
申请号：US12979796
申请日：2010-12-28
申请人： Takeshi Kamigaichi , Kenji Sawamura
发明人： Takeshi Kamigaichi , Kenji Sawamura
IPC分类号： G11C16/06
CPC分类号： G11C16/3454 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/3418 , G11C2211/5621
摘要： A control circuit is configured to perform, in a write operation to a memory cell and a verify operation for verifying a threshold voltage of the memory cell, a voltage control to provide the memory cell with threshold voltage distributions. The circuit is configured to apply, in a read operation from the memory cell, to a selected memory cell a read voltage between the lower and upper limits of the threshold voltage distributions, and apply to an unselected memory cell a first read-pass voltage higher than the upper limit of a first threshold voltage distribution that is the maximum distribution of the threshold voltage distributions. The circuit is configured to apply, at least during a verify operation in a first write operation conducted before a second write operation that completes writing to the first threshold voltage distribution, a second read-pass voltage lower than the first read-pass voltage to the unselected memory cell, and apply to the semiconductor layer and the source-line a positive voltage.
摘要翻译：控制电路被配置为在对存储器单元的写入操作和用于验证存储器单元的阈值电压的验证操作中执行电压控制，以向存储器单元提供阈值电压分布。该电路被配置为在从存储器单元的读取操作中将阈值电压分布的下限和上限之间的读取电压应用于所选择的存储器单元，并将其应用于未选择的存储器单元的第一读取通过电压超过作为阈值电压分布的最大分布的第一阈值电压分布的上限。该电路被配置为至少在第二写入操作期间在完成对第一阈值电压分布的写入的第二写入操作期间的验证操作期间施加低于第一读通过电压的第二读通过电压未选择的存储单元，并且应用于半导体层和源极线的正电压。

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