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1. 发明授权

US09953718B2 Programming memory cells to be programmed to different levels to an intermediate level from a lowest level 有权
公开(公告)号：US09953718B2
公开(公告)日：2018-04-24
申请号：US15437584
申请日：2017-02-21
申请人： MICRON TECHNOLOGY, INC.
发明人： Carmine Miccoli , Christian Caillat , Akira Goda
IPC分类号： G11C11/34 , G11C16/04 , G11C16/34 , G11C11/56
CPC分类号： G11C16/3427 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3418 , G11C16/3459 , G11C2211/5622
摘要： First memory cells are programmed to an intermediate level from a lowest level, corresponding to a lowest data state, where the first memory cells are to be programmed from the intermediate level to levels other than the lowest level. The first memory cells are not read or verified at the intermediate level. Different first memory cells of the first memory cells that are programmed to the intermediate level are respectively programmed to different levels of the levels other than the lowest level from the intermediate level. A second memory cell is programmed to a lower level than the different levels of the levels other than the lowest level from the lowest level while the different first memory cells are respectively programmed to the different levels of the levels other than the lowest level from the intermediate level.

2. 发明申请

US20180096722A1 TWO-PART PROGRAMMING METHODS 审中-公开
公开(公告)号：US20180096722A1
公开(公告)日：2018-04-05
申请号：US15831718
申请日：2017-12-05
申请人： MICRON TECHNOLOGY, INC.
发明人： Vishal Sarin , Allahyar Vahidimowlavi
IPC分类号： G11C11/56 , G11C16/34 , G11C16/10 , G11C16/04
CPC分类号： G11C11/5628 , G11C16/0408 , G11C16/0458 , G11C16/10 , G11C16/3418 , G11C16/3427 , G11C2211/562 , G11C2211/5622 , G11C2211/5642 , G11C2211/5648
摘要： Memory devices include control logic configured to set a first start program voltage and a first stop program voltage, to load actual first data for cells to be programmed to a level greater than or equal to a first level, and to load inhibit data for cells to be programmed to a level less than a second level. After programming the cells to be programmed to the level greater than or equal to the first level, the control logic is further configured to set a second start program voltage and a second stop program voltage, to load inhibit data for the cells programmed to the level greater than or equal to the first level, and to load actual second data for the cells to be programmed to the level less than the second level, wherein the first level is one level higher than the second level.

3. 发明申请

US20170310341A1 EFFICIENT DATA PATH ARCHITECTURE FOR FLASH DEVICES 审中-公开
公开(公告)号：US20170310341A1
公开(公告)日：2017-10-26
申请号：US15412353
申请日：2017-01-23
申请人： SK Hynix Inc.
发明人： Wei-Hao Yuan , Johnson Yen , ChunHok Ho
IPC分类号： H03M13/11 , G11C29/52 , G11C14/00 , G11C11/56 , G06F3/06 , H03M13/00
CPC分类号： H03M13/1105 , G06F3/0619 , G06F3/0629 , G06F3/0635 , G06F3/0655 , G06F3/0656 , G06F3/0679 , G06F2003/0691 , G11C7/1006 , G11C7/1084 , G11C11/5628 , G11C11/5642 , G11C14/0018 , G11C14/0063 , G11C16/10 , G11C29/52 , G11C2211/562 , G11C2211/5622 , G11C2211/5642 , H03M13/1102 , H03M13/611
摘要： Efficient data path architecture for flash devices requiring multi-pass programming utilizes an external memory as an intermediate buffer to store the encoded data used for a first pass programming of the flash device. The stored encoded data can be read from the external memory for subsequent passes programming instead of fetching the data from an on-chip memory, which stores the data received from a host system. Thus, the on-chip memory can be made available to speed up the next data transfer from the host system.

4. 发明授权

US09767894B2 Programming memories with stepped programming pulses 有权
公开(公告)号：US09767894B2
公开(公告)日：2017-09-19
申请号：US14299074
申请日：2014-06-09
申请人： MICRON TECHNOLOGY, INC.
发明人： Qiang Tang , Xiaojiang Guo , Ramin Ghodsi
IPC分类号： G06F12/00 , G11C11/56 , G06F12/02 , G06F3/06 , G11C16/34 , G11C16/04 , G11C16/12 , G11C16/10
CPC分类号： G11C11/5628 , G06F3/0625 , G06F3/0659 , G06F3/0688 , G06F12/0246 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/3404 , G11C16/3459 , G11C2211/5621 , G11C2211/5622
摘要： Memories and methods for programming memories with multi-step programming pulses are provided. One method includes applying a plurality of programming pulses to cells of the memory device to be programmed, with each programming pulse of the plurality of programming pulses being configured to contribute towards programming a cell of the plurality of cells to each data state of a plurality of programmed data states. A first portion of each programming pulse is used to program certain cells towards a target data state associated with a first threshold voltage level, and a later portion of each programming pulse is used to program other cells towards a target data state associated with a second threshold voltage level that is lower than the first threshold voltage level.

5. 发明申请

US20170076802A1 Programming of Nonvolatile Memory with Verify Level Dependent on Memory State and Programming Loop Count 审中-公开
标题翻译：根据存储器状态和编程循环计数验证电平的非易失性存储器的编程
公开(公告)号：US20170076802A1
公开(公告)日：2017-03-16
申请号：US14853733
申请日：2015-09-14
申请人： SanDisk Technologies, LLC.
发明人： Nima Mokhlesi
IPC分类号： G11C16/14 , G11C16/28 , G11C16/34
CPC分类号： G11C16/3459 , G11C11/5628 , G11C16/10 , G11C16/3481 , G11C2211/5621 , G11C2211/5622 , G11C2211/5624
摘要： A series of programming pulses, where the individual pulses are identified by a pulse number, is used to program a page of memory cells in parallel. After receiving a pulse, the memory cells under verification are verified to determine if they have been programmed to their respective target states. The memory cells that have been verified are inhibited from further programming while those memory cells not verified will be further programmed by subsequent programming pulses. The pulsing, verification and inhibition continue until all memory cells of the page have been program-verified. Each verify level used in the verification is a function of both the target state and the pulse number. This allows adjustment of the verify level to compensate for changes in sensing, including those due to variation in source line loading during the course of programming.
摘要翻译：使用一系列编程脉冲，其中单个脉冲由脉冲数标识，用于并行编程存储器单元的页面。在接收到脉冲之后，验证的存储器单元被确认以确定它们是否被编程到它们各自的目标状态。已经验证的存储器单元被禁止进一步编程，而未被验证的那些存储器单元将被随后的编程脉冲进一步编程。脉冲，验证和禁止继续，直到页面的所有存储单元已经被程序验证。验证中使用的每个验证级别都是目标状态和脉冲数的函数。这允许调整验证电平以补偿感测变化，包括在编程过程中由于源线负载变化引起的变化。

6. 发明授权

US09536612B1 Digital signaling processing for three dimensional flash memory arrays 有权
标题翻译：用于三维闪存阵列的数字信号处理
公开(公告)号：US09536612B1
公开(公告)日：2017-01-03
申请号：US14162493
申请日：2014-01-23
申请人： DENSBITS TECHNOLOGIES LTD.
发明人： Hanan Weingarten , Erez Sabbag
IPC分类号： G11C16/10 , G11C16/04
CPC分类号： G11C16/10 , G11C11/5628 , G11C11/5642 , G11C16/0408 , G11C16/0483 , G11C16/26 , G11C2211/562 , G11C2211/5622 , G11C2211/5641 , G11C2211/5648 , G11C2213/75
摘要： A method for multilevel programming flash memory cells of a three dimensional array of flash memory cells, the method may include receiving or determining a multiple phase programming scheme that is responsive to coupling between flash memory cells of the three dimensional array; and programming data to multiple flash memory cells of the three dimensional array in response to the multiple phase programming scheme. The multiple phase programming scheme determine a manner in which multiple programming levels are applied. At least two programming levels of the multiple programming levels correspond to bits of different significance.
摘要翻译：一种用于多层次编程闪存单元的三维阵列的闪存单元的方法，所述方法可以包括接收或确定响应于三维阵列的闪存单元之间的耦合的多相编程方案; 以及响应于多相编程方案将数据编程到三维阵列的多个闪存单元。多相编程方案确定应用多个编程级别的方式。多个编程级别的至少两个编程级别对应于不同重要性的位。

7. 发明授权

US09502101B2 Two-part programming methods 有权
标题翻译：两部分编程方法
公开(公告)号：US09502101B2
公开(公告)日：2016-11-22
申请号：US14725749
申请日：2015-05-29
申请人： MICRON TECHNOLOGY, INC.
发明人： Vishal Sarin , Allahyar Vahidimowlavi
IPC分类号： G11C11/56 , G11C16/04 , G11C16/10 , G11C16/34
CPC分类号： G11C11/5628 , G11C16/0408 , G11C16/0458 , G11C16/10 , G11C16/3418 , G11C16/3427 , G11C2211/562 , G11C2211/5622 , G11C2211/5642 , G11C2211/5648
摘要： A first memory cell is programmed to a first level using a first set of program pulses within a first programming voltage range. A second memory cell to be programmed to a second level less than the first level is inhibited while programming the first memory cell to the first level. After programming the first memory cell to the first level, the second memory cell is programmed to the second level using a second set of program pulses within a second programming voltage range, where the first programming voltage range overlaps the second programming voltage range. The first memory cell that is programmed to the first level is inhibited while programming the second memory cell to the second level.
摘要翻译：使用第一编程电压范围内的第一组编程脉冲将第一存储单元编程为第一电平。在将第一存储器单元编程到第一电平时，禁止要编程到小于第一电平的第二电平的第二存储器单元。在将第一存储器单元编程到第一电平之后，使用第二编程电压范围内的第二组编程脉冲将第二存储单元编程为第二电平，其中第一编程电压范围与第二编程电压范围重叠。在将第二存储器单元编程到第二级时，禁止编程到第一级的第一存储单元。

8. 发明授权

US09208874B2 Nonvolatile memory device having variable resistive elements and method of driving the same 有权
标题翻译：具有可变电阻元件的非易失性存储器件及其驱动方法
公开(公告)号：US09208874B2
公开(公告)日：2015-12-08
申请号：US14083470
申请日：2013-11-19
申请人： Yong-Kyu Lee , Bo-Geun Kim
发明人： Yong-Kyu Lee , Bo-Geun Kim
IPC分类号： G11C11/00 , G11C13/00 , G11C11/56
CPC分类号： G11C13/0064 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2013/0076 , G11C2013/0078 , G11C2013/0085 , G11C2211/5622 , G11C2213/72
摘要： A method is provided for driving a nonvolatile memory device. The method includes selecting first write drivers based on a predetermined current, performing a first program operation on resistive memory cells corresponding to the first write drivers, verifying whether the resistive memory cells have passed or failed in the first program operation and sorting information regarding failed bit memory cells that failed in the first program operation, selecting second write drivers based on the sorted failed bit memory cell information, and performing a second program operation on resistive memory cells corresponding to the second write drivers.
摘要翻译：提供了用于驱动非易失性存储器件的方法。该方法包括基于预定电流选择第一写入驱动器，对与第一写入驱动器相对应的电阻存储器单元执行第一编程操作，在第一程序操作中验证电阻性存储器单元是否已经通过或失败，以及关于故障位的排序信息在第一程序操作中失败的存储器单元，基于分类的故障位存储器单元信息选择第二写驱动器，以及对与第二写驱动器相对应的电阻存储单元执行第二程序操作。

9. 发明申请

US20140169068A1 NONVOLATILE MEMORY DEVICE HAVING VARIABLE RESISTIVE ELEMENTS AND METHOD OF DRIVING THE SAME 有权
标题翻译：具有可变电阻元件的非易失性存储器件及其驱动方法
公开(公告)号：US20140169068A1
公开(公告)日：2014-06-19
申请号：US14083470
申请日：2013-11-19
申请人： YONG-KYU LEE , BO-GEUN KIM
发明人： YONG-KYU LEE , BO-GEUN KIM
IPC分类号： G11C13/00
CPC分类号： G11C13/0064 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2013/0076 , G11C2013/0078 , G11C2013/0085 , G11C2211/5622 , G11C2213/72
摘要： A method is provided for driving a nonvolatile memory device. The method includes selecting first write drivers based on a predetermined current, performing a first program operation on resistive memory cells corresponding to the first write drivers, verifying whether the resistive memory cells have passed or failed in the first program operation and sorting information regarding failed bit memory cells that failed in the first program operation, selecting second write drivers based on the sorted failed bit memory cell information, and performing a second program operation on resistive memory cells corresponding to the second write drivers.
摘要翻译：提供了用于驱动非易失性存储器件的方法。该方法包括基于预定电流选择第一写入驱动器，对与第一写入驱动器相对应的电阻存储器单元执行第一编程操作，在第一程序操作中验证电阻性存储器单元是否已经通过或失败，以及关于故障位的排序信息在第一程序操作中失败的存储器单元，基于分类的故障位存储器单元信息选择第二写驱动器，以及对与第二写驱动器相对应的电阻存储单元执行第二程序操作。

10. 发明授权

US08737127B2 Memory controllers to output data signals of a number of bits and to receive data signals of a different number of bits 有权
标题翻译：存储器控制器输出多个位的数据信号并接收不同位数的数据信号
公开(公告)号：US08737127B2
公开(公告)日：2014-05-27
申请号：US13770059
申请日：2013-02-19
申请人： Micron Technology, Inc.
发明人： Vishal Sarin , Jung-Sheng Hoei , Jonathan Pabustan , Frankie F. Roohparvar
IPC分类号： G11C16/04
CPC分类号： G11C11/5642 , G11C7/16 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C27/005 , G11C2211/5621 , G11C2211/5622 , G11C2211/5642 , G11C2216/14
摘要： A memory controller has a digital signal processor. The digital signal processor is configured to output a digital data signal of M+N bits of program data intended for programming a memory cell of a memory device. The digital signal processor is configured to receive a digital data signal of M+L bits read from the memory cell of the memory device and to retrieve from the received digital data signal M bits of data that were stored in the memory cell.
摘要翻译：存储器控制器具有数字信号处理器。数字信号处理器被配置为输出用于对存储器件的存储器单元进行编程的程序数据的M + N位的数字数据信号。数字信号处理器被配置为接收从存储器件的存储器单元读取的M + L位的数字数据信号，并从接收的数字数据信号M中取回存储在存储单元中的数据位。

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