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1. 发明授权

US08314455B2 Non-volatile semiconductor storage device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08314455B2
公开(公告)日：2012-11-20
申请号：US13156727
申请日：2011-06-09
申请人： Yasuhiro Shiino , Atsuhiro Sato , Takeshi Kamigaichi , Fumitaka Arai
发明人： Yasuhiro Shiino , Atsuhiro Sato , Takeshi Kamigaichi , Fumitaka Arai
IPC分类号： H01L29/792
CPC分类号： H01L27/11578 , H01L27/11573 , H01L27/11582
摘要： A non-volatile semiconductor storage device includes: a memory cell area in which a plurality of electrically rewritable memory cells are formed; and a peripheral circuit area in which transistors that configure peripheral circuits to control the memory cells are formed. The memory cell area has formed therein: a semiconductor layer formed to extend in a vertical direction to a semiconductor substrate; a plurality of conductive layers extending in a parallel direction to, and laminated in a vertical direction to the semiconductor substrate; and a property-varying layer formed between the semiconductor layer and the conductive layers and having properties varying depending on a voltage applied to the conductive layers. The peripheral circuit area has formed therein a plurality of dummy wiring layers that are formed on the same plane as each of the plurality of conductive layers and that are electrically separated from the conductive layers.
摘要翻译：非易失性半导体存储装置包括：形成有多个电可重写存储单元的存储单元区域; 以及外围电路区域，其中形成配置外围电路以控制存储单元的晶体管。在其中形成存储单元区域：形成为在垂直方向上延伸到半导体衬底的半导体层; 多个导电层，沿着与半导体基板的垂直方向平行的方向延伸并层叠; 以及形成在所述半导体层和所述导电层之间的性质变化层，并且具有根据施加到所述导电层的电压而变化的特性。外围电路区域中形成有多个虚拟布线层，其形成在与多个导电层中的每一个相同的平面上，并且与导电层电分离。

2. 发明申请

US20110233652A1 NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：非挥发性半导体存储器件
公开(公告)号：US20110233652A1
公开(公告)日：2011-09-29
申请号：US13156727
申请日：2011-06-09
申请人： Yasuhiro Shino , Atsuhiro Sato , Takeshi Kamigaichi , Fumitaka Arai
发明人： Yasuhiro Shino , Atsuhiro Sato , Takeshi Kamigaichi , Fumitaka Arai
IPC分类号： H01L27/115
CPC分类号： H01L27/11578 , H01L27/11573 , H01L27/11582
摘要： A non-volatile semiconductor storage device includes: a memory cell area in which a plurality of electrically rewritable memory cells are formed; and a peripheral circuit area in which transistors that configure peripheral circuits to control the memory cells are formed. The memory cell area has formed therein: a semiconductor layer formed to extend in a vertical direction to a semiconductor substrate; a plurality of conductive layers extending in a parallel direction to, and laminated in a vertical direction to the semiconductor substrate; and a property-varying layer formed between the semiconductor layer and the conductive layers and having properties varying depending on a voltage applied to the conductive layers. The peripheral circuit area has formed therein a plurality of dummy wiring layers that are formed on the same plane as each of the plurality of conductive layers and that are electrically separated from the conductive layers.
摘要翻译：非易失性半导体存储装置包括：形成有多个电可重写存储单元的存储单元区域; 以及外围电路区域，其中形成配置外围电路以控制存储单元的晶体管。在其中形成存储单元区域：形成为在垂直方向上延伸到半导体衬底的半导体层; 多个导电层，沿着与半导体基板的垂直方向平行的方向延伸并层叠; 以及形成在所述半导体层和所述导电层之间的性质变化层，并且具有根据施加到所述导电层的电压而变化的特性。外围电路区域中形成有多个虚拟布线层，其形成在与多个导电层中的每一个相同的平面上，并且与导电层电分离。

3. 发明授权

US07977733B2 Non-volatile semiconductor storage device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US07977733B2
公开(公告)日：2011-07-12
申请号：US12394929
申请日：2009-02-27
申请人： Yasuhiro Shiino , Atsuhiro Sato , Takeshi Kamigaichi , Fumitaka Arai
发明人： Yasuhiro Shiino , Atsuhiro Sato , Takeshi Kamigaichi , Fumitaka Arai
IPC分类号： H01L29/792
CPC分类号： H01L27/11578 , H01L27/11573 , H01L27/11582
摘要： A non-volatile semiconductor storage device includes: a memory cell area in which a plurality of electrically rewritable memory cells are formed; and a peripheral circuit area in which transistors that configure peripheral circuits to control the memory cells are formed. The memory cell area has formed therein: a semiconductor layer formed to extend in a vertical direction to a semiconductor substrate; a plurality of conductive layers extending in a parallel direction to, and laminated in a vertical direction to the semiconductor substrate; and a property-varying layer formed between the semiconductor layer and the conductive layers and having properties varying depending on a voltage applied to the conductive layers. The peripheral circuit area has formed therein a plurality of dummy wiring layers that are formed on the same plane as each of the plurality of conductive layers and that are electrically separated from the conductive layers.
摘要翻译：非易失性半导体存储装置包括：形成有多个电可重写存储单元的存储单元区域; 以及外围电路区域，其中形成配置外围电路以控制存储单元的晶体管。在其中形成存储单元区域：形成为在垂直方向上延伸到半导体衬底的半导体层; 多个导电层，沿着与半导体基板的垂直方向平行的方向延伸并层叠; 以及形成在所述半导体层和所述导电层之间的性质变化层，并且具有根据施加到所述导电层的电压而变化的特性。外围电路区域中形成有多个虚拟布线层，其形成在与多个导电层中的每一个相同的平面上，并且与导电层电分离。

4. 发明申请

US20090230450A1 NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：非挥发性半导体存储器件
公开(公告)号：US20090230450A1
公开(公告)日：2009-09-17
申请号：US12394929
申请日：2009-02-27
申请人： Yasuhiro Shiino , Atsuhiro Sato , Takeshi Kamigaichi , Fumitaka Arai
发明人： Yasuhiro Shiino , Atsuhiro Sato , Takeshi Kamigaichi , Fumitaka Arai
IPC分类号： H01L29/788 , H01L21/20
CPC分类号： H01L27/11578 , H01L27/11573 , H01L27/11582
摘要： A non-volatile semiconductor storage device includes: a memory cell area in which a plurality of electrically rewritable memory cells are formed; and a peripheral circuit area in which transistors that configure peripheral circuits to control the memory cells are formed. The memory cell area has formed therein: a semiconductor layer formed to extend in a vertical direction to a semiconductor substrate; a plurality of conductive layers extending in a parallel direction to, and laminated in a vertical direction to the semiconductor substrate; and a property-varying layer formed between the semiconductor layer and the conductive layers and having properties varying depending on a voltage applied to the conductive layers. The peripheral circuit area has formed therein a plurality of dummy wiring layers that are formed on the same plane as each of the plurality of conductive layers and that are electrically separated from the conductive layers.
摘要翻译：非易失性半导体存储装置包括：形成有多个电可重写存储单元的存储单元区域; 以及外围电路区域，其中形成配置外围电路以控制存储单元的晶体管。在其中形成存储单元区域：形成为在垂直方向上延伸到半导体衬底的半导体层; 多个导电层，沿着与半导体基板的垂直方向平行的方向延伸并层叠; 以及形成在所述半导体层和所述导电层之间的性质变化层，并且具有根据施加到所述导电层的电压而变化的特性。外围电路区域中形成有多个虚拟布线层，其形成在与多个导电层中的每一个相同的平面上，并且与导电层电分离。

5. 发明申请

US20080181009A1 SEMICONDUCTOR MEMORY DEVICE AND WRITE METHOD THEREOF 失效
标题翻译：半导体存储器件及其写入方法
公开(公告)号：US20080181009A1
公开(公告)日：2008-07-31
申请号：US12017543
申请日：2008-01-22
申请人： Fumitaka Arai , Takeshi Kamigaichi , Atsuhiro Sato
发明人： Fumitaka Arai , Takeshi Kamigaichi , Atsuhiro Sato
IPC分类号： G11C16/04 , G11C16/06 , G11C7/00
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/3454 , G11C16/3459 , G11C2211/5621 , G11C2211/5622 , G11C2211/5642
摘要： A semiconductor memory device includes a memory cell array, bit lines, a source line, a sense amplifier, a data buffer, a voltage generating circuit, and a control circuit, the control circuit being configured such that the control circuit writes batchwise the write data, in the plurality of memory cells of the bit lines, the control circuit, after the batchwise write, causes the plurality of first latch circuits to hold the write data once again, and the control circuit executes verify read from the memory cells, and executes, in a case where read data of the plurality of sense amplifier circuits by the verify read disagree with the write data that are held once again in the plurality of first latch circuits, additional write to write batchwise the held write data in the plurality of memory cells once again.
摘要翻译：半导体存储器件包括存储单元阵列，位线，源极线，读出放大器，数据缓冲器，电压产生电路和控制电路，该控制电路被配置为使得控制电路分批写入写数据在位线的多个存储单元中，控制电路在分批写入之后使得多个第一锁存电路再次保持写入数据，并且控制电路执行从存储器单元的验证读取，并执行在通过验证读取的多个读出放大器电路的读取数据与在多个第一锁存电路中再次被保持的写入数据不同时的情况下，对多个存储器中的保持的写入数据进行分批写入细胞再次。

6. 发明授权

US07796439B2 Semiconductor memory device and write method thereof 失效
标题翻译：半导体存储器件及其写入方法
公开(公告)号：US07796439B2
公开(公告)日：2010-09-14
申请号：US12017543
申请日：2008-01-22
申请人： Fumitaka Arai , Takeshi Kamigaichi , Atsuhiro Sato
发明人： Fumitaka Arai , Takeshi Kamigaichi , Atsuhiro Sato
IPC分类号： G11C11/34 , G11C11/06
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/3454 , G11C16/3459 , G11C2211/5621 , G11C2211/5622 , G11C2211/5642
摘要： A semiconductor memory device includes a memory cell array, bit lines, a source line, a sense amplifier, a data buffer, a voltage generating circuit, and a control circuit, the control circuit being configured such that the control circuit writes batchwise the write data, in the plurality of memory cells of the bit lines, the control circuit, after the batchwise write, causes the plurality of first latch circuits to hold the write data once again, and the control circuit executes verify read from the memory cells, and executes, in a case where read data of the plurality of sense amplifier circuits by the verify read disagree with the write data that are held once again in the plurality of first latch circuits, additional write to write batchwise the held write data in the plurality of memory cells once again.
摘要翻译：半导体存储器件包括存储单元阵列，位线，源极线，读出放大器，数据缓冲器，电压产生电路和控制电路，该控制电路被配置为使得控制电路分批写入写数据在位线的多个存储单元中，控制电路在分批写入之后使得多个第一锁存电路再次保持写入数据，并且控制电路执行从存储器单元的验证读取，并执行在通过验证读取的多个读出放大器电路的读取数据与在多个第一锁存电路中再次被保持的写入数据不同时的情况下，对多个存储器中的保持的写入数据进行分批写入细胞再次。

7. 发明申请

US20100246255A1 NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR CONTROLLING THE SAME 失效
标题翻译：非易失性半导体存储装置及其控制方法
公开(公告)号：US20100246255A1
公开(公告)日：2010-09-30
申请号：US12729626
申请日：2010-03-23
申请人： Yasuhiro SHIINO , Atsuhiro Sato , Takeshi Kamigaichi
发明人： Yasuhiro SHIINO , Atsuhiro Sato , Takeshi Kamigaichi
IPC分类号： G11C16/28
CPC分类号： G11C16/30 , G11C7/14 , G11C16/0483 , G11C16/10 , G11C16/28 , H01L27/11519 , H01L27/11521
摘要： A nonvolatile semiconductor storage device includes a memory cell array and a peripheral circuit. The memory cell array includes active areas extending in a first direction, a dummy active area extending in the first direction, memory cells on the plurality of active areas, first dummy cells on the dummy active area, diffusion layer areas each connected to the corresponding memory cell and the corresponding first dummy cell, first contacts in the respective active areas, and a second contact in the dummy active area. The peripheral circuit includes a voltage applying unit configured to apply to each of the first contacts a first voltage to set each of the memory cells in a write enable state or a second voltage to set the memory cells in a write inhibit state, and to apply to the second contact a third voltage to change a threshold of the dummy cell.
摘要翻译：非易失性半导体存储装置包括存储单元阵列和外围电路。存储单元阵列包括沿第一方向延伸的有效区域，在第一方向上延伸的虚拟有源区域，多个有效区域上的存储单元，虚拟有效区域上的第一虚设单元，各自连接到对应存储器的扩散层区域单元和对应的第一虚拟单元，在相应的有效区域中首先接触，并且在虚拟活动区域中的第二触点。外围电路包括电压施加单元，其被配置为向每个第一触点施加第一电压，以将每个存储单元设置在写使能状态或第二电压以将存储单元设置在写禁止状态，并且应用向第二接触器施加第三电压以改变虚设电池的阈值。

8. 发明授权

US08270220B2 Nonvolatile semiconductor storage device and method for controlling the same 失效
标题翻译：非易失性半导体存储装置及其控制方法
公开(公告)号：US08270220B2
公开(公告)日：2012-09-18
申请号：US12729626
申请日：2010-03-23
申请人： Yasuhiro Shiino , Atsuhiro Sato , Takeshi Kamigaichi
发明人： Yasuhiro Shiino , Atsuhiro Sato , Takeshi Kamigaichi
IPC分类号： G11C16/06
CPC分类号： G11C16/30 , G11C7/14 , G11C16/0483 , G11C16/10 , G11C16/28 , H01L27/11519 , H01L27/11521
摘要： A nonvolatile semiconductor storage device includes a memory cell array and a peripheral circuit. The memory cell array includes active areas extending in a first direction, a dummy active area extending in the first direction, memory cells on the plurality of active areas, first dummy cells on the dummy active area, diffusion layer areas each connected to the corresponding memory cell and the corresponding first dummy cell, first contacts in the respective active areas, and a second contact in the dummy active area. The peripheral circuit includes a voltage applying unit configured to apply to each of the first contacts a first voltage to set each of the memory cells in a write enable state or a second voltage to set the memory cells in a write inhibit state, and to apply to the second contact a third voltage to change a threshold of the dummy cell.
摘要翻译：非易失性半导体存储装置包括存储单元阵列和外围电路。存储单元阵列包括沿第一方向延伸的有效区域，在第一方向上延伸的虚拟有源区域，多个有效区域上的存储单元，虚拟有效区域上的第一虚设单元，各自连接到对应存储器的扩散层区域单元和对应的第一虚拟单元，在相应的有效区域中首先接触，并且在虚拟活动区域中的第二触点。外围电路包括电压施加单元，其被配置为向每个第一触点施加第一电压，以将每个存储单元设置在写使能状态或第二电压以将存储单元设置在写禁止状态，并且应用向第二接触器施加第三电压以改变虚设电池的阈值。

9. 发明授权

US08377814B2 Semiconductor memory device and manufacturing method thereof 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US08377814B2
公开(公告)日：2013-02-19
申请号：US13164931
申请日：2011-06-21
申请人： Atsuhiro Sato , Hiroyuki Nitta , Fumitaka Arai
发明人： Atsuhiro Sato , Hiroyuki Nitta , Fumitaka Arai
IPC分类号： H01L21/28
CPC分类号： H01L27/11524 , H01L21/76816 , H01L27/11521
摘要： A semiconductor memory device includes a first block having first memory cells and first select transistors, a second block having second memory cells and second select transistors, and arranged adjacent to the first block in a first direction, the second select transistor being arranged to face the first select transistor and commonly having a diffusion region with the first select transistor, a first interconnection layer provided on the diffusion region between the first and second blocks and extending in a second direction, and a second interconnection layer having a first portion provided in contact with an upper portion of the first interconnection layer and extending to a portion outside the first interconnection layer, and a second portion extending in the second direction and connected to the first portion in a portion outside a portion on the first interconnection layer.
摘要翻译：半导体存储器件包括具有第一存储器单元和第一选择晶体管的第一块，具有第二存储单元和第二选择晶体管的第二块，并且沿第一方向布置成与第一块相邻，第二选择晶体管被布置为面对第一选择晶体管，并且通常具有与第一选择晶体管的扩散区，第一互连层，设置在第一和第二块之间的扩散区上并沿第二方向延伸;第二互连层，具有设置成与第一选择晶体管接触的第一部分第一互连层的上部并且延伸到第一互连层外部的部分，以及第二部分，其在第二方向上延伸并且在第一互连层上的部分外部的部分连接到第一部分。

10. 发明授权

US08120092B2 Semiconductor memory device and manufacturing method therefor 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US08120092B2
公开(公告)日：2012-02-21
申请号：US12565181
申请日：2009-09-23
申请人： Atsuhiro Sato , Fumitaka Arai
发明人： Atsuhiro Sato , Fumitaka Arai
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/11519 , H01L27/11521 , H01L27/11529
摘要： First gate electrodes of memory cell transistors are formed in series with each other on a semiconductor substrate. A second gate electrode of a first selection transistor is formed adjacent to one end of the first electrodes. A third gate electrode of a second selection transistor is formed adjacent to the second electrode. A fourth gate electrode of a peripheral transistor is formed on the substrate. First, second, and third sidewall films are formed on side surfaces of the second, third, and fourth gate electrodes, respectively. A film thickness of the third sidewall film is larger than that of the first and second sidewall films. A space between the first electrode and the second electrode is larger than a space between the first electrodes, and a space between the second electrode and the third electrode is larger than a space between the first electrode and the second electrode.
摘要翻译：存储单元晶体管的第一栅电极在半导体衬底上彼此串联形成。第一选择晶体管的第二栅电极与第一电极的一端相邻地形成。第二选择晶体管的第三栅电极与第二电极相邻地形成。在基板上形成周边晶体管的第四栅电极。第一，第二和第三侧壁膜分别形成在第二，第三和第四栅电极的侧表面上。第三侧壁膜的膜厚大于第一和第二侧壁膜的膜厚。第一电极和第二电极之间的空间大于第一电极之间的空间，并且第二电极和第三电极之间的间隔大于第一电极和第二电极之间的间隔。

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