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1. 发明授权

US07741658B2 Self-aligned super stressed PFET 有权
标题翻译：自对准超应力PFET
公开(公告)号：US07741658B2
公开(公告)日：2010-06-22
申请号：US11842437
申请日：2007-08-21
申请人： Yaocheng Liu , Zhijiong Luo , Huilong Zhu
发明人： Yaocheng Liu , Zhijiong Luo , Huilong Zhu
IPC分类号： H01L31/0328
CPC分类号： H01L21/26506 , H01L21/268 , H01L29/1054 , H01L29/165 , H01L29/66545 , H01L29/6659 , H01L29/66636 , H01L29/7833
摘要： The embodiments of the invention comprise a self-aligned super stressed p-type field effect transistor (PFET). More specifically, a field effect transistor comprises a channel region comprising N-doped material and a gate above the channel region. The field effect transistor also includes a source region on a first side of the channel region and a drain region on a second side of the channel region opposite the first side. The source and drain regions each comprise silicon germanium, wherein the silicon germanium has structural indicia of epitaxial growth.
摘要翻译：本发明的实施例包括自对准超应力p型场效应晶体管（PFET）。更具体地，场效应晶体管包括包含N掺杂材料的沟道区和沟道区上方的栅。场效应晶体管还包括在沟道区的第一侧上的源极区域和与第一侧相对的沟道区域的第二侧上的漏极区域。源极和漏极区域各自包含硅锗，其中硅锗具有外延生长的结构标记。

2. 发明申请

US20090050942A1 SELF-ALIGNED SUPER STRESSED PFET 有权
标题翻译：自对准超级应力PFET
公开(公告)号：US20090050942A1
公开(公告)日：2009-02-26
申请号：US11842437
申请日：2007-08-21
申请人： Yaocheng Liu , Zhijiong Luo , Huilong Zhu
发明人： Yaocheng Liu , Zhijiong Luo , Huilong Zhu
IPC分类号： H01L29/94 , H01L21/336
CPC分类号： H01L21/26506 , H01L21/268 , H01L29/1054 , H01L29/165 , H01L29/66545 , H01L29/6659 , H01L29/66636 , H01L29/7833
摘要： The embodiments of the invention comprise a self-aligned super stressed p-type field effect transistor (PFET). More specifically, a field effect transistor comprises a channel region comprising N-doped material and a gate above the channel region. The field effect transistor also includes a source region on a first side of the channel region and a drain region on a second side of the channel region opposite the first side. The source and drain regions each comprise silicon germanium, wherein the silicon germanium has structural indicia of epitaxial growth.
摘要翻译：本发明的实施例包括自对准超应力p型场效应晶体管（PFET）。更具体地，场效应晶体管包括包含N掺杂材料的沟道区和沟道区上方的栅。场效应晶体管还包括在沟道区的第一侧上的源极区域和与第一侧相对的沟道区域的第二侧上的漏极区域。源极和漏极区域各自包含硅锗，其中硅锗具有外延生长的结构标记。

3. 发明授权

US09356025B2 Enhancing MOSFET performance with corner stresses of STI 有权
标题翻译：通过STI拐角应力增强MOSFET性能
公开(公告)号：US09356025B2
公开(公告)日：2016-05-31
申请号：US14348579
申请日：2012-03-29
申请人： Huilong Zhu , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L27/092 , H01L29/78 , H01L21/8238 , H01L21/762 , H01L29/66
CPC分类号： H01L27/092 , H01L21/76224 , H01L21/823807 , H01L21/823878 , H01L29/66575 , H01L29/7846
摘要： The present invention relates to enhancing MOSFET performance with the corner stresses of STI. A method of manufacturing a MOS device comprises the steps of: providing a semiconductor substrate; forming trenches on the semiconductor substrate and at least a pMOS region and at least an nMOS region surrounded by the trenches; filling the trenches with a dielectric material having a stress; removing at least the dielectric material having a stress in the trenches which is adjacent to a position where a channel is to be formed on each of the pMOS and nMOS regions so as to form exposed regions; filling the exposed regions with a insulating material; and forming pMOS and nMOS devices on the pMOS region and the nMOS region, respectively, wherein each of the pMOS and nMOS devices comprises a channel, a gate formed above the channel, and a source and a drain formed at both sides of the channel; wherein in a channel length direction, the boundary of each exposed region is substantially aligned with the boundary of the position of the channel, or the boundary of each exposed region extends along the channel length direction to be aligned with the boundary of corresponding pMOS or nMOS region.
摘要翻译：本发明涉及利用STI的拐角应力来增强MOSFET的性能。一种制造MOS器件的方法包括以下步骤：提供半导体衬底; 在所述半导体衬底和至少一个pMOS区域和由所述沟槽包围的至少nMOS区域中形成沟槽; 用具有应力的介电材料填充沟槽; 至少去除在沟道中具有应力的介电材料，所述沟槽邻近要在pMOS和nMOS区域中的每一个上形成沟道的位置，以形成暴露区域; 用绝缘材料填充暴露的区域; 以及分别在pMOS区域和nMOS区域上形成pMOS和nMOS器件，其中pMOS和nMOS器件中的每一个包括沟道，形成在沟道上方的栅极以及形成在沟道两侧的源极和漏极; 其中在通道长度方向上，每个曝光区域的边界基本上与通道位置的边界对齐，或者每个曝光区域的边界沿着沟道长度方向延伸以与对应的pMOS或nMOS的边界对准地区。

4. 发明授权

US09054221B2 Semiconductor device with a common back gate isolation region and method for manufacturing the same 有权
标题翻译：具有公共背栅隔离区的半导体器件及其制造方法
公开(公告)号：US09054221B2
公开(公告)日：2015-06-09
申请号：US13510807
申请日：2011-11-18
申请人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L27/088 , H01L21/336 , H01L21/84 , H01L27/12
CPC分类号： H01L21/84 , H01L27/1203
摘要： The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device comprises: an SOI wafer comprising a semiconductor substrate, a buried insulation layer, and a semiconductor layer, wherein the buried insulation layer is disposed on the semiconductor substrate, and the semiconductor layer is disposed on the buried insulation layer; a plurality of MOSFETs being formed adjacently to each other in the SOI wafer, wherein each of the MOSFETs comprises a respective backgate being formed in the semiconductor substrate; and a plurality of shallow trench isolations, each of which being formed between respective adjacent MOSFETs to isolate the respective adjacent MOSFETs from each other, wherein the respective adjacent MOSFETs share a common backgate isolation region under and in direct contact with the respective backgate in the semiconductor substrate, and a PNP junction or an NPN junction is formed by the common backgate isolation region and the respective backgate of the respective adjacent MOSFETs. According to the present disclosure, respective backgates of two adjacent MOSFETs are isolated from each other by the shallow trench isolation. Furthermore, the two adjacent MOSFETs are also isolated from each other by the PNP or NPN junction formed by the respective backgates of the two adjacent MOSFETs and the common backgate isolation. As a result, this device structure has a better insulation effect over the prior art MOSFET and it greatly reduces the possibility of breakthrough.
摘要翻译：本发明提供一种半导体器件及其制造方法。半导体器件包括：SOI晶片，其包括半导体衬底，掩埋绝缘层和半导体层，其中所述掩埋绝缘层设置在所述半导体衬底上，并且所述半导体层设置在所述掩埋绝缘层上; 在SOI晶片中彼此相邻形成的多个MOSFET，其中每个MOSFET包括形成在半导体衬底中的相应后栅; 以及多个浅沟槽隔离，其中每一个均形成在各个相邻的MOSFET之间，以将各个相邻的MOSFET彼此隔离，其中相应的相邻MOSFET在半导体内部和相应的后栅极直接接触并与之直接接触。衬底，并且PNP结或NPN结由公共背栅隔离区和相应的相邻MOSFET的相应背栅形成。根据本公开，两个相邻MOSFET的相应背板通过浅沟槽隔离彼此隔离。此外，两个相邻的MOSFET也通过由两个相邻MOSFET的相应后沿和公共背栅隔离形成的PNP或NPN结彼此隔离。结果，该器件结构具有比现有技术的MOSFET更好的绝缘效果，并且大大降低了突破的可能性。

5. 发明授权

US08981454B2 Non-volatile memory device using finfet and method for manufacturing the same 有权
标题翻译：使用finfet的非易失性存储器件及其制造方法
公开(公告)号：US08981454B2
公开(公告)日：2015-03-17
申请号：US13061461
申请日：2010-09-25
申请人： Huilong Zhu , Haizhou Yin , Zhijiong Luo
发明人： Huilong Zhu , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L29/788 , H01L29/66 , H01L29/78
CPC分类号： H01L29/66825 , H01L21/28273 , H01L21/845 , H01L29/42324 , H01L29/785 , H01L29/7881
摘要： The present application discloses a non-volatile memory device, comprising a semiconductor fin on an insulating layer; a channel region at a central portion of the semiconductor fin; source/drain regions on both sides of the semiconductor fin; a floating gate arranged at a first side of the semiconductor fin and extending in a direction further away from the semiconductor fin; and a first control gate arranged on top of the floating gate or covering top and sidewall portions of the floating gate. The non-volatile memory device reduces a short channel effect, has an increased memory density, and is cost effective.
摘要翻译：本申请公开了一种非易失性存储器件，其包括绝缘层上的半导体鳍片; 在半导体鳍片的中心部分处的沟道区域; 半导体鳍片两侧的源极/漏极区域; 布置在半导体鳍片的第一侧并沿远离半导体鳍片的方向延伸的浮动栅极; 以及布置在所述浮动栅极的顶部上或覆盖所述浮动栅极的顶部和侧壁部分的第一控制栅极。非易失性存储器件减少短通道效应，具有增加的存储器密度，并且是成本有效的。

6. 发明授权

US08952453B2 MOSFET formed on an SOI wafer with a back gate 有权
标题翻译：在具有背栅的SOI晶片上形成MOSFET
公开(公告)号：US08952453B2
公开(公告)日：2015-02-10
申请号：US13580053
申请日：2011-11-18
申请人： Huilong Zhu , Qingqing Liang , Haizhou Yin , Zhijiong Luo
发明人： Huilong Zhu , Qingqing Liang , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L27/12 , H01L21/84 , H01L29/66 , H01L29/786
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/66545 , H01L29/78648
摘要： The present application discloses a MOSFET and a method for manufacturing the same. The MOSFET is formed on an SOI wafer, comprising: a shallow trench isolation for defining an active region in the semiconductor layer; a gate stack on the semiconductor layer; a source region and a drain region in the semiconductor layer on both sides of the gate stack; a channel region in the semiconductor layer and sandwiched by the source region and the drain region; a back gate in the semiconductor substrate; a first dummy gate stack overlapping with a boundary between the semiconductor layer and the shallow trench isolation; and a second dummy gate stack on the shallow trench isolation, wherein the MOSFET further comprises a plurality of conductive vias which are disposed between the gate stack and the first dummy gate stack and electrically connected to the source region and the drain region respectively, and between the first dummy gate stack and the second dummy gate stack and electrically connected to the back gate. The MOSFET avoids short circuit between the back gate and the source/drain regions by the dummy gate stacks.
摘要翻译：本申请公开了一种MOSFET及其制造方法。 MOSFET形成在SOI晶片上，包括：用于限定半导体层中的有源区的浅沟槽隔离; 半导体层上的栅极堆叠; 栅极堆叠的两侧的半导体层中的源极区域和漏极区域; 半导体层中的沟道区，被源极区和漏极区夹持; 半导体衬底中的背栅; 与半导体层和浅沟槽隔离之间的边界重叠的第一虚拟栅极堆叠; 以及在浅沟槽隔离上的第二虚拟栅极堆叠，其中所述MOSFET还包括多个导电通孔，所述多个导电通孔设置在所述栅极堆叠和所述第一伪栅极堆叠之间，并分别电连接到所述源极区域和所述漏极区域之间，以及第一虚拟栅极堆叠和第二虚拟栅极堆叠并且电连接到背栅极。 MOSFET通过虚拟栅极堆叠避免了背栅极和源极/漏极区域之间的短路。

7. 发明授权

US08928089B2 Semiconductor structure and method for forming the same 有权
标题翻译：半导体结构及其形成方法
公开(公告)号：US08928089B2
公开(公告)日：2015-01-06
申请号：US13201827
申请日：2011-02-24
申请人： Huilong Zhu , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L21/70 , H01L21/8238 , H01L29/78
CPC分类号： H01L21/823807 , H01L21/823864 , H01L29/7843
摘要： A semiconductor structure and a method for forming the same are provided. The structure comprises a semiconductor substrate (100) with an nMOSFET region (102) and a pMOSFET region (104) on it. An nMOSFET structure and a pMOSFET structure are formed in the nMOSFET region (102) and the pMOSFET region (104), respectively. The nMOSFET structure comprises a first channel region (182) formed in the nMOSFET region (102) and a first gate stack formed in the first channel region (182). The nMOSFET structure is covered with a compressive-stressed material layer (130) to apply a tensile stress to the first channel region (182). The pMOSFET structure comprises a second channel region (184) formed in the pMOSFET region (104) and a second gate stack formed in the second channel region (184). The pMOSFET structure is covered with a tensile-stressed material layer (140) to apply a compressive stress to the second channel region (184).
摘要翻译：提供半导体结构及其形成方法。该结构包括其上具有nMOSFET区域（102）和pMOSFET区域（104）的半导体衬底（100）。 nMOSFET结构和pMOSFET结构分别形成在nMOSFET区域（102）和pMOSFET区域（104）中。 nMOSFET结构包括形成在nMOSFET区域（102）中的第一沟道区（182）和形成在第一沟道区（182）中的第一栅叠层。 nMOSFET结构用压应力材料层（130）覆盖，以向第一沟道区域（182）施加拉伸应力。 pMOSFET结构包括形成在pMOSFET区域（104）中的第二沟道区（184）和形成在第二沟道区（184）中的第二栅叠层。 pMOSFET结构被拉伸应力材料层（140）覆盖，以向第二通道区域（184）施加压缩应力。

8. 发明授权

US08841777B2 Bonded structure employing metal semiconductor alloy bonding 有权
标题翻译：使用金属半导体合金结合的结合结构
公开(公告)号：US08841777B2
公开(公告)日：2014-09-23
申请号：US12685954
申请日：2010-01-12
申请人： Mukta G. Farooq , Zhengwen Li , Zhijiong Luo , Huilong Zhu
发明人： Mukta G. Farooq , Zhengwen Li , Zhijiong Luo , Huilong Zhu
IPC分类号： H01L21/48 , H01L21/52 , H01L21/40 , H01L21/20 , H01L27/06 , H01L21/768
CPC分类号： H01L21/76841 , H01L21/2007 , H01L27/0688 , H01L2224/80357 , H01L2224/80895 , H01L2224/80896
摘要： Vertical stacks of a metal portion and a semiconductor portion formed on a first substrate are brought into physical contact with vertical stacks of a metal portion and a semiconductor portion formed on a second substrate. Alternately, vertical stacks of a metal portion and a semiconductor portion formed on a first substrate are brought into physical contact with metal portions formed on a second substrate. The assembly of the first and second substrates is subjected to an anneal at a temperature that induces formation of a metal semiconductor alloy derived from the semiconductor portions and the metal portions. The first substrate and the second substrate are bonded through metal semiconductor alloy portions that adhere to the first and second substrates.
摘要翻译：形成在第一基板上的金属部分和半导体部分的垂直叠层与形成在第二基板上的金属部分和半导体部分的垂直叠层物理接触。或者，形成在第一基板上的金属部分和半导体部分的垂直堆叠与形成在第二基板上的金属部分物理接触。在引起由半导体部分和金属部分衍生的金属半导体合金的形成的温度下对第一和第二基板的组装进行退火。第一基板和第二基板通过粘附到第一和第二基板的金属半导体合金部分接合。

9. 发明授权

US08815698B2 Well region formation method and semiconductor base 有权
标题翻译：井区形成方法和半导体基础
公开(公告)号：US08815698B2
公开(公告)日：2014-08-26
申请号：US13381636
申请日：2011-07-26
申请人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
发明人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
IPC分类号： H01L27/04 , H01L21/76 , H01L21/8238 , H01L29/16 , H01L21/8234 , H01L29/66
CPC分类号： H01L21/823481 , H01L21/823493 , H01L21/823878 , H01L21/823892 , H01L29/1608 , H01L29/161 , H01L29/66651
摘要： A well region formation method and a semiconductor base in the field of semiconductor technology are provided. A method comprises: forming isolation regions in a semiconductor substrate to isolate active regions; selecting at least one of the active regions, and forming a first well region in the selected active region; forming a mask to cover the selected active region, and etching the rest of the active regions, so as to form grooves; and growing a semiconductor material by epitaxy to fill the grooves. Another method comprises: forming isolation regions in a semiconductor substrate for isolating active regions; forming well regions in the active regions; etching the active regions to form grooves, such that the grooves have a depth less than or equal to a depth of the well regions; and growing a semiconductor material by epitaxy to fill the grooves.
摘要翻译：提供了半导体技术领域中的阱区形成方法和半导体基底。一种方法包括：在半导体衬底中形成隔离区以隔离有源区; 选择所述有源区域中的至少一个，以及在所选择的有源区域中形成第一阱区域; 形成掩模以覆盖所选择的有源区，并蚀刻其余的有源区，以便形成沟槽; 并通过外延生长半导体材料以填充凹槽。另一种方法包括：在半导体衬底中形成用于隔离有源区的隔离区; 在活跃区域形成井区; 蚀刻有源区以形成凹槽，使得凹槽具有小于或等于阱区深度的深度; 并通过外延生长半导体材料以填充凹槽。

10. 发明申请

US20140197410A1 Semiconductor Structure and Method for Manufacturing the Same 审中-公开
标题翻译：半导体结构及其制造方法
公开(公告)号：US20140197410A1
公开(公告)日：2014-07-17
申请号：US13697096
申请日：2012-05-17
申请人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
发明人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
IPC分类号： H01L29/78 , H01L29/66 , H01L29/04
CPC分类号： H01L29/78 , H01L21/76283 , H01L29/04 , H01L29/66477 , H01L29/66772 , H01L29/7843 , H01L29/7848 , H01L29/78603 , H01L29/78618 , H01L29/78696
摘要： The present invention provides a method for manufacturing a semiconductor structure. The method comprises: providing an SOI substrate and forming a gate structure on said SOI substrate; etching a SOI layer and a BOX layer of the SOI substrate on both sides of the gate structure to form a trench exposing the BOX layer, said trench partially entering into the BOX layer; forming a stressed layer that fills up a part of said trench; forming a semiconductor layer covering the stressed layer in the trench. Correspondingly, the present invention also provides a semiconductor structure formed by the above method. In the semiconductor structure and the method for manufacturing the same according to the present invention, a trench is formed on an ultrathin SOI substrate, first filled with a stressed layer, and then filled with a semiconductor material to be ready for forming a source/drain region. The stressed layer provides a favorable stress to the channel of the semiconductor device, thus facilitating improving the performance of the semiconductor device.
摘要翻译：本发明提供一种半导体结构的制造方法。该方法包括：提供SOI衬底并在所述SOI衬底上形成栅极结构; 在栅极结构的两侧蚀刻SOI衬底的SOI层和BOX层，以形成露出BOX层的沟槽，所述沟槽部分地进入BOX层; 形成填充所述沟槽的一部分的应力层; 形成覆盖沟槽中的应力层的半导体层。相应地，本发明还提供了通过上述方法形成的半导体结构。在根据本发明的半导体结构及其制造方法中，在超薄SOI衬底上形成沟槽，首先填充有应力层，然后填充半导体材料以准备形成源极/漏极地区。应力层对半导体器件的通道提供有利的应力，从而有助于提高半导体器件的性能。

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