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1. 发明授权

US07598147B2 Method of forming CMOS with Si:C source/drain by laser melting and recrystallization 有权
标题翻译：通过激光熔融和重结晶用Si：C源极/漏极形成CMOS的方法
公开(公告)号：US07598147B2
公开(公告)日：2009-10-06
申请号：US11860127
申请日：2007-09-24
申请人： Yaocheng Liu , Qiqing C. Ouyang , Kathryn T. Schonenberg , Chun-Yung Sung
发明人： Yaocheng Liu , Qiqing C. Ouyang , Kathryn T. Schonenberg , Chun-Yung Sung
IPC分类号： H01L21/336
CPC分类号： H01L21/26506 , H01L21/268 , H01L21/823807 , H01L21/823814 , H01L21/823828 , H01L29/665 , H01L29/66545 , H01L29/7848
摘要： A method of forming crystalline Si:C in source and drain regions is provided. After formation of shallow trench isolation and gate electrodes of field effect transistors, gate spacers are formed on gate electrodes. Preamorphization implantation is performed in the source and drain regions, followed by carbon implantation. The upper portion of the source and drain regions comprises an amorphous mixture of silicon, germanium, and/or carbon. An anti-reflective layer is deposited to enhance the absorption of a laser beam into the silicon substrate. The laser beam is scanned over the silicon substrate including the upper source and drain region with the amorphous mixture. The energy of the laser beam is controlled so that the temperature of the semiconductor substrate is above the melting temperature of the amorphous mixture but below the glass transition temperature of silicon oxide so that structural integrity of the semiconductor structure is preserved.
摘要翻译：提供了在源极和漏极区域中形成晶体Si：C的方法。在形成浅沟槽隔离和场效应晶体管的栅电极之后，在栅电极上形成栅极间隔物。在源极和漏极区域中进行前置放电，随后进行碳注入。源区和漏区的上部包括硅，锗和/或碳的无定形混合物。沉积抗反射层以增强激光束到硅衬底中的吸收。激光束在包括具有无定形混合物的上源极和漏极区域的硅衬底上扫描。控制激光束的能量使得半导体衬底的温度高于无定形混合物的熔融温度但低于氧化硅的玻璃化转变温度，从而保持半导体结构的结构完整性。

2. 发明申请

US20090081836A1 METHOD OF FORMING CMOS WITH SI:C SOURCE/DRAIN BY LASER MELTING AND RECRYSTALLIZATION 有权
标题翻译：通过激光熔化和重结晶形成CMOS与Si：C源/漏极的方法
公开(公告)号：US20090081836A1
公开(公告)日：2009-03-26
申请号：US11860127
申请日：2007-09-24
申请人： Yaocheng Liu , Qiqing C. Ouyang , Kathryn T. Schonenberg , Chun-Yung Sung
发明人： Yaocheng Liu , Qiqing C. Ouyang , Kathryn T. Schonenberg , Chun-Yung Sung
IPC分类号： H01L21/265 , H01L21/8238
CPC分类号： H01L21/26506 , H01L21/268 , H01L21/823807 , H01L21/823814 , H01L21/823828 , H01L29/665 , H01L29/66545 , H01L29/7848
摘要： A method of forming crystalline Si:C in source and drain regions is provided. After formation of shallow trench isolation and gate electrodes of field effect transistors, gate spacers are formed on gate electrodes. Preamorphization implantation is performed in the source and drain regions, followed by carbon implantation. The upper portion of the source and drain regions comprises an amorphous mixture of silicon, germanium, and/or carbon. An anti-reflective layer is deposited to enhance the absorption of a laser beam into the silicon substrate. The laser beam is scanned over the silicon substrate including the upper source and drain region with the amorphous mixture. The energy of the laser beam is controlled so that the temperature of the semiconductor substrate is above the melting temperature of the amorphous mixture but below the glass transition temperature of silicon oxide so that structural integrity of the semiconductor structure is preserved.
摘要翻译：提供了在源极和漏极区域中形成晶体Si：C的方法。在形成浅沟槽隔离和场效应晶体管的栅电极之后，在栅电极上形成栅极间隔物。在源极和漏极区域中进行前置放电，随后进行碳注入。源区和漏区的上部包括硅，锗和/或碳的无定形混合物。沉积抗反射层以增强激光束到硅衬底中的吸收。激光束在包括具有无定形混合物的上源极和漏极区域的硅衬底上扫描。控制激光束的能量使得半导体衬底的温度高于无定形混合物的熔融温度但低于氧化硅的玻璃化转变温度，从而保持了半导体结构的结构完整性。

3. 发明授权

US07618857B2 Method of reducing detrimental STI-induced stress in MOSFET channels 有权
标题翻译：降低MOSFET通道中有害的STI诱发应力的方法
公开(公告)号：US07618857B2
公开(公告)日：2009-11-17
申请号：US11623935
申请日：2007-01-17
申请人： Meikei Leong , Qiqing C. Ouyang , Chun-Yung Sung
发明人： Meikei Leong , Qiqing C. Ouyang , Chun-Yung Sung
IPC分类号： H01L21/8238
CPC分类号： H01L21/823878 , H01L21/823807 , H01L29/1083 , H01L29/665 , H01L29/7846
摘要： A method for reducing STI processing induced stress on a substrate during fabrication of a MOSFET. The method includes providing a substrate, wells (including dopants), and STIs in an upper layer of the substrate. A layer of an oxide substance is formed on a top surface of the upper layer of the substrate covering the STIs. A layer of a nitride substance is formed over the oxide layer. The substrate is annealed using temperatures greater than 1000° C. to activate the dopants in the wells which results in less stress on the STIs and hence less stress in the channels because of the nitride substance layer. The nitride and oxide substance layers are then stripped off the substrate, and CMOS fabrication is continued. The low stress remains in the channels if the thermal budget in following processes are low by using low temperature RTA and/or laser anneal.
摘要翻译：一种在制造MOSFET期间减少STI处理引起的衬底上的应力的方法。该方法包括在衬底的上层中提供衬底，阱（包括掺杂剂）和STI。在覆盖STI的衬底的上层的顶表面上形成氧化物层。在氧化物层上形成氮化物层。使用大于1000℃的温度对衬底进行退火以激活阱中的掺杂剂，这导致STI上的应力较小，因此由于氮化物物质层而导致通道中的较小的应力。然后将氮化物和氧化物物质层从衬底上剥离，继续进行CMOS制造。如果通过使用低温RTA和/或激光退火，以下过程中的热预算为低，则低应力保留在通道中。

4. 发明申请

US20080083955A1 INTRINSICALLY STRESSED LINER AND FABRICATION METHODS THEREOF 审中-公开
标题翻译：本发明的内衬及其制造方法
公开(公告)号：US20080083955A1
公开(公告)日：2008-04-10
申请号：US11538506
申请日：2006-10-04
申请人： Thomas S. Kanarsky , Qiqing Ouyang , Kathryn T. Schonenberg , Chun-Yung Sung
发明人： Thomas S. Kanarsky , Qiqing Ouyang , Kathryn T. Schonenberg , Chun-Yung Sung
IPC分类号： H01L29/76
CPC分类号： H01L29/7833 , H01L21/76829 , H01L21/76831 , H01L21/76841 , H01L21/76865 , H01L29/7843 , H01L29/7845
摘要： A stressed liner for improving carrier mobility in a transistor and a method for fabricating the same is disclosed. The stressed liner includes an intrinsically stressed conductive film encapsulated between two insulating layers such as silicon nitride, silicon oxide, or oxynitride. The stressed liner may be compressively-stressed or tensile-stressed depending on whether an n-FET or p-FET is required.
摘要翻译：公开了一种用于改善晶体管中的载流子迁移率的应力衬垫及其制造方法。应力衬里包括密封在两个绝缘层（例如氮化硅，氧化硅或氮氧化物）之间的本征应力导电膜。根据是否需要n-FET或p-FET，应力衬垫可以是压应力或拉伸应力。

5. 发明申请

US20080171413A1 Method of Reducing Detrimental STI-Induced Stress in MOSFET Channels 有权
标题翻译：降低MOSFET通道中有害的STI诱导应力的方法
公开(公告)号：US20080171413A1
公开(公告)日：2008-07-17
申请号：US11623935
申请日：2007-01-17
申请人： Meikei Leong , Qiqing C. Ouyang , Chun-Yung Sung
发明人： Meikei Leong , Qiqing C. Ouyang , Chun-Yung Sung
IPC分类号： H01L21/26 , H01L21/8238
CPC分类号： H01L21/823878 , H01L21/823807 , H01L29/1083 , H01L29/665 , H01L29/7846
摘要： A method for reducing STI processing induced stress on a substrate during fabrication of a MOSFET. The method includes providing a substrate, wells (including dopants), and STIs in an upper layer of the substrate. A layer of an oxide substance is formed on a top surface of the upper layer of the substrate covering the STIs. A layer of a nitride substance is formed over the oxide layer. The substrate is annealed using temperatures greater than 1000° C. to activate the dopants in the wells which results in less stress on the STIs and hence less stress in the channels because of the nitride substance layer. The nitride and oxide substance layers are then stripped off the substrate, and CMOS fabrication is continued. The low stress remains in the channels if the thermal budget in following processes are low by using low temperature RTA and/or laser anneal.
摘要翻译：一种在制造MOSFET期间减少STI处理引起的衬底上的应力的方法。该方法包括在衬底的上层中提供衬底，阱（包括掺杂剂）和STI。在覆盖STI的衬底的上层的顶表面上形成氧化物层。在氧化物层上形成氮化物层。使用大于1000℃的温度对衬底进行退火，以激活阱中的掺杂剂，这导致STI上的应力较小，因此由于氮化物物质层而导致通道中的较小的应力。然后将氮化物和氧化物物质层从衬底上剥离，继续进行CMOS制造。如果通过使用低温RTA和/或激光退火，以下过程中的热预算为低，则低应力保留在通道中。

6. 发明申请

US20080248626A1 SHALLOW TRENCH ISOLATION SELF-ALIGNED TO TEMPLATED RECRYSTALLIZATION BOUNDARY 审中-公开
标题翻译： SHOWOW TRENCH ISOLATION自对准至模拟重构边界
公开(公告)号：US20080248626A1
公开(公告)日：2008-10-09
申请号：US11697102
申请日：2007-04-05
申请人： Yaocheng Liu , Zhijiong Luo , Katherine L. Saenger , Chun-Yung Sung , Rajasekhar Venigalla , Haizhou Yin
发明人： Yaocheng Liu , Zhijiong Luo , Katherine L. Saenger , Chun-Yung Sung , Rajasekhar Venigalla , Haizhou Yin
IPC分类号： H01L21/762
CPC分类号： H01L21/26506 , H01L21/02667 , H01L21/187 , H01L21/76224
摘要： A hybrid orientation direct-semiconductor-bond (DSB) substrate with shallow trench isolation (STI) that is self-aligned to recrystallization boundaries is formed by patterning a hard mask layer for STI, a first amorphization implantation into openings in the hard mask layer, lithographic patterning of portions of a top semiconductor layer, a second amorphization implantation into exposed portions of the DSB substrate, recrystallization of the portions of the top semiconductor layer, and formation of STI utilizing the pattern in the hard mask layer. The edges of patterned photoresist for the second amorphization implantation are located within the openings in the patterned hard mask layer. Defective boundary regions formed underneath the openings in the hard mask layer are removed during the formation of STI to provide a leakage path free substrate. Due to elimination of a requirement for increased STI width, device density is increased compared to non-self-aligning process integration schemes.
摘要翻译：通过将STI的硬掩模层图案化，在硬掩模层的开口中进行第一非晶化注入，形成具有与重结晶边界自对准的浅沟槽隔离（STI）的混合取向直接半导体结合（DSB）顶部半导体层的部分的平版印刷图案化，第二非晶化注入到DSB衬底的暴露部分中，顶部半导体层的部分的再结晶，以及利用硬掩模层中的图案形成STI。用于第二非晶化注入的图案化光致抗蚀剂的边缘位于图案化的硬掩模层的开口内。在形成STI期间去除在硬掩模层中形成在开口下面的有缺陷的边界区域，以提供无泄漏路径的衬底。由于消除了对于增加的STI宽度的要求，与非自对准工艺集成方案相比，器件密度增加。

7. 发明授权

US09413075B2 Graphene based structures and methods for broadband electromagnetic radiation absorption at the microwave and terahertz frequencies 有权
公开(公告)号：US09413075B2
公开(公告)日：2016-08-09
申请号：US13523182
申请日：2012-06-14
申请人： Phaedon Avouris , Alberto V. Garcia , Chun-Yung Sung , Fengnian Xia , Hugen Yan
发明人： Phaedon Avouris , Alberto V. Garcia , Chun-Yung Sung , Fengnian Xia , Hugen Yan
IPC分类号： H01Q17/00
CPC分类号： H01Q17/00
摘要： Structures and methods for cloaking an object to electromagnetic radiation at the microwave and terahertz frequencies include disposing a plurality of graphene sheets about the object. Intermediate layers of a transparent dielectric material can be disposed between graphene sheets to optimize the performance. In other embodiments, the graphene can be formulated into a paint formulation or a fabric and applied to the object. The structures and methods absorb at least a portion of the electromagnetic radiation at the microwave and terabyte frequencies.

8. 发明授权

US09174413B2 Graphene based structures and methods for shielding electromagnetic radiation 有权
公开(公告)号：US09174413B2
公开(公告)日：2015-11-03
申请号：US13523178
申请日：2012-06-14
申请人： Phaedon Avouris , Alberto Valdes Garcia , Chun-Yung Sung , Fengnian Xia , Hugen Yan
发明人： Phaedon Avouris , Alberto Valdes Garcia , Chun-Yung Sung , Fengnian Xia , Hugen Yan
IPC分类号： F21V9/00 , G02B5/02 , G02C7/10 , G02F1/361 , G03B1/00 , H05K9/00 , B32B9/04 , B82Y30/00 , C23C16/00
CPC分类号： H05K9/0088 , B32B9/04 , B32B37/18 , B32B2457/00 , B82Y30/00 , H05K9/0081 , Y10T156/10
摘要： Electromagnetic interference shielding structures and methods of shielding an object form electromagnetic radiation at frequencies greater than a megahertz generally include providing highly doped graphene sheets about the object to be shielded. The highly doped graphene sheets may have a dopant concentration greater than >1e1013 cm−2, which is effective to reflect the electromagnetic radiation or a dopant concentration of 1e1013 cm−2>n>0 cm−2, which is effective to absorb the electromagnetic radiation.

9. 发明授权

US07960263B2 Amorphization/templated recrystallization method for hybrid orientation substrates 有权
标题翻译：混合取向基板的非晶化/模板重结晶方法
公开(公告)号：US07960263B2
公开(公告)日：2011-06-14
申请号：US12767261
申请日：2010-04-26
申请人： Keith Edward Fogel , Katherine L. Saenger , Chun-Yung Sung , Haizhou Yin
发明人： Keith Edward Fogel , Katherine L. Saenger , Chun-Yung Sung , Haizhou Yin
IPC分类号： H01L21/20
CPC分类号： H01L21/02675 , H01L21/02532 , H01L21/2022 , H01L21/76224 , H01L21/823807
摘要： The present invention provides an improved amorphization/templated recrystallization (ATR) method for fabricating low-defect-density hybrid orientation substrates. ATR methods for hybrid orientation substrate fabrication generally start with a Si layer having a first orientation bonded to a second Si layer or substrate having a second orientation. Selected regions of the first Si layer are amorphized and then recrystallized into the orientation of the second Si layer by using the second Si layer as a template. The process flow of the present invention solves two major difficulties not disclosed by prior art ATR methods: the creation of “corner defects” at the edges of amorphized Si regions bounded by trenches, and undesired orientation changes during a high temperature post-recrystallization defect-removal annealing of non-ATR'd regions not bounded by trenches. In particular, this invention provides a process flow comprising the steps of (i) amorphization and low-temperature recrystallization performed in substrate regions free of trenches, (ii) formation of trench isolation regions that subsume the defective regions at the edge of the ATR'd regions, and (iii) a high-temperature defect-removal anneal performed with the trench isolation regions in place.
摘要翻译：本发明提供了用于制造低缺陷密度混合取向基材的改进的非晶化/模板重结晶（ATR）方法。用于混合取向衬底制造的ATR方法通常从具有第一取向键合到具有第二取向的第二Si层或衬底的Si层开始。第一Si层的选定区域是非晶化的，然后通过使用第二Si层作为模板将其再结晶成第二Si层的取向。本发明的工艺流程解决了现有技术ATR方法未公开的两个主要困难：在由沟槽限定的非晶化Si区域的边缘产生“角部缺陷”，以及在高温后再结晶缺陷 - 未被沟槽限定的非ATR区域的去除退火。特别地，本发明提供了一种工艺流程，其包括以下步骤：（i）在没有沟槽的衬底区域中进行非晶化和低温重结晶，（ii）形成在ATR'边缘处的缺陷区域的沟槽隔离区域的形成， d区域，以及（iii）在沟槽隔离区域中进行的高温缺陷去除退火。

10. 发明授权

US07678622B2 Semiconductor method and device with mixed orientation substrate 有权
标题翻译：具有混合取向衬底的半导体方法和器件
公开(公告)号：US07678622B2
公开(公告)日：2010-03-16
申请号：US11868001
申请日：2007-10-05
申请人： Jiang Yan , Chun-Yung Sung , Danny Pak-Chum Shum , Alois Gutmann
发明人： Jiang Yan , Chun-Yung Sung , Danny Pak-Chum Shum , Alois Gutmann
IPC分类号： H01L21/84
CPC分类号： H01L27/1203 , H01L21/76232 , H01L21/76283 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1207 , H01L29/045 , H01L29/78687
摘要： In a method of forming a semiconductor device, a wafer includes a first semiconductor region of a first crystal orientation and a second semiconductor region of a second crystal orientation. Insulating material is formed over the wafer. A first portion of the insulating material is removed to expose the first semiconductor region and a second portion of the insulating material is removed to expose the second semiconductor region. Semiconductor material of the first crystal orientation is epitaxially grown over the exposed first semiconductor region and semiconductor material of the second crystal orientation is epitaxially grown over the exposed second semiconductor region.
摘要翻译：在形成半导体器件的方法中，晶片包括第一晶体取向的第一半导体区域和第二晶体取向的第二半导体区域。在晶片上形成绝缘材料。除去绝缘材料的第一部分以暴露第一半导体区域，并且去除绝缘材料的第二部分以暴露第二半导体区域。在暴露的第一半导体区域上外延生长第一晶体取向的半导体材料，并且在暴露的第二半导体区域上外延生长第二晶体取向的半导体材料。

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