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1. 发明授权

US06291327B1 Optimization of S/D annealing to minimize S/D shorts in memory array 失效
标题翻译：优化S / D退火以最小化存储器阵列中的S / D短路
公开(公告)号：US06291327B1
公开(公告)日：2001-09-18
申请号：US09192094
申请日：1998-11-13
申请人： Xiao-Yu Li , Sunil D. Mehta , Christopher O. Schmidt , Robert H. Tu
发明人： Xiao-Yu Li , Sunil D. Mehta , Christopher O. Schmidt , Robert H. Tu
IPC分类号： H01L21336
CPC分类号： H01L21/76237 , H01L21/823418 , H01L21/823462 , H01L27/1052
摘要： A method for eliminating source/drain shorting generated during the highly-doped source/drain implant steps in a standard STI process is provided. This is achieved by reducing the RTA temperature to be less than 1000° C. so as to minimize enhanced doping diffusion. Further, the energy level for the highly-doped source/drain implant steps is increased so to compensate for poly depletion in the gate electrodes.
摘要翻译：提供了一种用于消除在标准STI工艺中的高掺杂源极/漏极注入步骤期间产生的源极/漏极短路的方法。这是通过将RTA温度降低至小于1000℃来实现的，以便使增强的掺杂扩散最小化。此外，高掺杂源极/漏极注入步骤的能级增加，以补偿栅电极中的多晶硅耗尽。

2. 发明授权

US06172392B2 Boron doped silicon capacitor plate 失效
标题翻译：硼掺杂硅电容器板
公开(公告)号：US06172392B2
公开(公告)日：2001-01-09
申请号：US09280887
申请日：1999-03-29
申请人： Christopher O. Schmidt , Sunil D. Mehta , Xiao-Yu Li
发明人： Christopher O. Schmidt , Sunil D. Mehta , Xiao-Yu Li
IPC分类号： H01L29788
CPC分类号： H01L27/11558 , H01L27/115 , H01L27/11521
摘要： A nonvolatile memory device utilizing a program junction region of a p-type impurity and oxide grown thereon. In one aspect, the device comprises a programming structure and a program junction separated from said programming structure by a field oxide region. A program junction oxide layer overlies said program junction region. A floating gate is provided over the oxide which covers said programming structure, said program junction oxide layer, and in some embodiments the gate oxide of a sense transistor.
摘要翻译：一种利用p型杂质的程序结区域和在其上生长的氧化物的非易失性存储器件。一方面，该装置包括编程结构和通过场氧化物区与所述编程结构分离的程序结。程序结氧化物层覆盖所述程序结区域。在覆盖所述编程结构，所述程序结氧化物层的氧化物上提供浮置栅极，并且在一些实施例中，提供感测晶体管的栅极氧化物。

3. 发明授权

US06221733B1 Reduction of mechanical stress in shallow trench isolation process 有权
标题翻译：浅沟槽隔离过程中机械应力的降低
公开(公告)号：US06221733B1
公开(公告)日：2001-04-24
申请号：US09192096
申请日：1998-11-13
申请人： Xiao-Yu Li , Sunil D. Mehta , Robert H. Tu
发明人： Xiao-Yu Li , Sunil D. Mehta , Robert H. Tu
IPC分类号： H01L2176
CPC分类号： H01L21/76232 , Y10S148/05
摘要： A method of minimizing mechanical stress generated during the trench-forming/trench-filling process steps in a standard shallow trench isolation (STI) process is provided. This is achieved by forming trenches with a more sloped and smoother profile, and/or limiting the trench depth to be less than 0.4 &mgr;m, and/or reducing or increasing the trench densification temperature, and/or performing the densification step after the chemical-mechanical polishing step. In addition, a furnace TEOS oxide film is used as the trench-filling material.
摘要翻译：提供了一种使标准浅沟槽隔离（STI）工艺中的沟槽形成/沟槽填充工艺步骤期间产生的机械应力最小化的方法。这是通过形成具有更倾斜和更平滑轮廓的沟槽和/或限制沟槽深度小于0.4μm，和/或减小或增加沟槽致密化温度，和/或在化学处理之后执行致密化步骤来实现的，机械抛光步骤。此外，使用炉TEOS氧化物膜作为沟槽填充材料。

4. 发明授权

US06309942B1 STI punch-through defects and stress reduction by high temperature oxide reflow process 有权
标题翻译： STI穿透缺陷和通过高温氧化物回流工艺的应力降低
公开(公告)号：US06309942B1
公开(公告)日：2001-10-30
申请号：US09245161
申请日：1999-02-04
申请人： Ting Y. Tsui , Robert H. Tu , Xiao-Yu Li , Sunil D. Mehta
发明人： Ting Y. Tsui , Robert H. Tu , Xiao-Yu Li , Sunil D. Mehta
IPC分类号： H01L2176
CPC分类号： H01L21/76229
摘要： A method of manufacturing a semiconductor device with reduced shallow trench isolation defects and stress is disclosed. The disclosed method begins by providing a silicon substrate including a capping layer. A plurality of isolation trenches are then etched through the capping layer and into the silicon substrate to form a plurality of isolation regions in the silicon substrate. The isolation trenches are then filled with an oxide layer. The oxide layer and the capping layer are then polished back using techniques known in the art. After polishing, the semiconductor device is annealed between a temperature range of about 1150° C. to about 1200° C.
摘要翻译：公开了一种制造具有减小的浅沟槽隔离缺陷和应力的半导体器件的方法。所公开的方法开始于提供包括封盖层的硅衬底。然后通过覆盖层蚀刻多个隔离沟槽并进入硅衬底，以在硅衬底中形成多个隔离区域。然后用氧化物层填充隔离沟槽。然后使用本领域已知的技术将氧化物层和覆盖层进行抛光。在抛光之后，半导体器件在约1150℃至约1200℃的温度范围内退火

5. 发明授权

US6075293A Semiconductor device having a multi-layer metal interconnect structure 有权
标题翻译：具有多层金属互连结构的半导体器件
公开(公告)号：US6075293A
公开(公告)日：2000-06-13
申请号：US263412
申请日：1999-03-05
申请人： Xiao-Yu Li , Sunil D. Mehta , Van H. Pham , Amit P. Marathe
发明人： Xiao-Yu Li , Sunil D. Mehta , Van H. Pham , Amit P. Marathe
IPC分类号： H01L23/532 , H01L23/48
CPC分类号： H01L23/53223 , H01L2924/0002
摘要： A multi-level metal interconnect structure in a semiconductor device includes a plurality of overlying metal layers separated by ILD layers and electrically connected by filled vias in the ILD layers. Each metal layer includes a relatively thick antireflective layer for improved electromigration resistance. Each metal layer also includes a metal lining layer and a metal interconnect layer overlying the metal lining layer. Enhanced electromigration resistance is obtained by forming the antireflective layer to a thickness of no less than the thickness of the metal lining layer. In a preferred embodiment of the invention, the antireflective layer has a thickness of about 1000 angstroms.
摘要翻译：半导体器件中的多级金属互连结构包括由ILD层分离并由ILD层中的填充通孔电连接的多个上覆金属层。每个金属层包括相对较厚的抗反射层，用于改善电迁移阻力。每个金属层还包括覆盖金属衬里层的金属衬里层和金属互连层。通过将抗反射层形成为不小于金属衬里层的厚度的厚度来获得增强的电迁移电阻。在本发明的优选实施例中，抗反射层的厚度为约1000埃。

6. 发明授权

US06326663B1 Avalanche injection EEPROM memory cell with P-type control gate 失效
标题翻译：雪崩注入EEPROM存储单元，带P型控制门
公开(公告)号：US06326663B1
公开(公告)日：2001-12-04
申请号：US09277441
申请日：1999-03-26
申请人： Xiao-Yu Li , Steven J. Fong , Sunil D. Mehta
发明人： Xiao-Yu Li , Steven J. Fong , Sunil D. Mehta
IPC分类号： H01L29788
CPC分类号： H01L27/11517 , H01L27/115
摘要： A non-volatile memory cell, comprising a semiconductor substrate having a first conductivity type. A control region is formed of said first conductivity type in the substrate and a control region oxide formed over the control region. The cell includes a program element having a first active region of a second conductivity type formed in said substrate, a doped or implanted region adjacent to said first active region, and a gate oxide overlying at least the channel region. An active region oxide covers a portion of the first active region. A floating gate is formed over said semiconductor substrate on said active region oxide and said control region oxide.
摘要翻译：一种非易失性存储单元，包括具有第一导电类型的半导体衬底。控制区域由衬底中的所述第一导电类型形成，并且在控制区域上形成控制区氧化物。单元包括具有形成在所述衬底中的第二导电类型的第一有源区，与所述第一有源区相邻的掺杂或注入区以及覆盖至少沟道区的栅极氧化物的程序元件。有源区氧化物覆盖第一有源区的一部分。在所述有源区氧化物和所述控制区氧化物上的所述半导体衬底上形成浮栅。

7. 发明授权

US06093946A EEPROM cell with field-edgeless tunnel window using shallow trench isolation process 失效
标题翻译：具有无源隧道窗的EEPROM单元采用浅沟槽隔离工艺
公开(公告)号：US06093946A
公开(公告)日：2000-07-25
申请号：US26814
申请日：1998-02-20
申请人： Xiao-Yu Li , Sunil D. Mehta
发明人： Xiao-Yu Li , Sunil D. Mehta
IPC分类号： H01L21/28 , H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L27/11558 , H01L29/7883
摘要： An improved EEPROM cell having a field-edgeless tunnel window is provided which is fabricated by a STI process so as to produce reliable endurance and data retention. The EEPROM cell includes a floating gate, a programmable junction region, and a tunneling oxide layer separating the programmable junction region and the floating gate. The tunneling oxide layer defines a tunnel window which allows for programming and erasing of the floating gate by tunneling electrons therethrough. The programmable junction region has a width dimension and a length dimension so as to define a first area. The tunnel window has a width dimension and a length dimension so as to define a second area. The second area of the tunnel window is completely confined within the first area of the programmable junction region so as to form a field-edgeless tunnel window.
摘要翻译：提供了具有场无边界隧道窗的改进的EEPROM单元，其通过STI工艺制造，以便产生可靠的耐久性和数据保持。 EEPROM单元包括浮置栅极，可编程结区域和分离可编程结区域和浮置栅极的隧穿氧化物层。隧道氧化物层限定隧道窗口，其允许通过隧穿电子进行浮动栅极的编程和擦除。可编程连接区域具有宽度尺寸和长度尺寸，以便限定第一区域。隧道窗口具有宽度尺寸和长度尺寸，以便限定第二区域。隧道窗口的第二区域被完全限制在可编程连接区域的第一区域内，从而形成无边界的隧道窗口。

8. 发明授权

US6087696A Stacked tunneling dielectric technology for improving data retention of EEPROM cell 失效
标题翻译：堆叠隧道电介质技术，用于改善EEPROM单元的数据保留
公开(公告)号：US6087696A
公开(公告)日：2000-07-11
申请号：US86437
申请日：1998-05-28
申请人： Xiao-Yu Li , Qi Xiang , Sunil D. Mehta
发明人： Xiao-Yu Li , Qi Xiang , Sunil D. Mehta
IPC分类号： H01L21/28 , H01L21/8247 , H01L29/51 , H01L29/788
CPC分类号： H01L21/28194 , H01L21/28273 , H01L27/11521 , H01L27/11558 , H01L29/513 , H01L29/517 , H01L21/28202 , H01L21/28211 , H01L29/518
摘要： An improved EEPROM cell structure and a method of fabricating the same is provided so as to improve data retention. The EEPROM cell includes a stacked dielectric structure consisting of a thin tunnel oxide layer and a high-k dielectric layer to function as the tunneling dielectric barrier so as to suppress leakage current.
摘要翻译：提供了改进的EEPROM单元结构及其制造方法，以便改善数据保留。 EEPROM单元包括由薄的隧道氧化物层和高k电介质层构成的叠层电介质结构，用作隧道电介质势垒，以便抑制漏电流。

9. 发明授权

US5969992A EEPROM cell using P-well for tunneling across a channel 失效
标题翻译：使用P阱的EEPROM单元进行跨通道的隧穿
公开(公告)号：US5969992A
公开(公告)日：1999-10-19
申请号：US217647
申请日：1998-12-21
申请人： Sunil D. Mehta , Xiao-Yu Li
发明人： Sunil D. Mehta , Xiao-Yu Li
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115
CPC分类号： H01L27/11521 , G11C16/0433 , H01L27/115 , H01L27/11558
摘要： An EEPROM cell is described that is programmed and erased by electron tunneling across an entire portion of separate transistor channels. The EEPROM cell has three transistors formed in a P-well of a semiconductor substrate. The three transistors are a tunneling transistor (NMOS), a sense transistor (NMOS) and a read transistor (NMOS). Electron tunneling occurs to program the EEPROM cell through a sense tunnel oxide layer upon incurrence of a sufficient voltage potential between a floating gate and the sense channel. Electron tunneling also occurs to erase the EEPROM cell through a tunnel oxide layer upon incurrence of a sufficient voltage potential between the floating gate and the tunneling channel.
摘要翻译：描述了通过遍及分离的晶体管通道的整个部分的电子隧道编程和擦除的EEPROM单元。 EEPROM单元具有形成在半导体衬底的P阱中的三个晶体管。三个晶体管是隧道晶体管（NMOS），感测晶体管（NMOS）和读取晶体管（NMOS）。发生电子隧穿，以在浮动栅极和感测通道之间发生足够的电压电势时通过感测隧道氧化物层来编程EEPROM单元。当浮置栅极和隧穿通道之间产生足够的电压电势时，也会发生电子隧穿，以通过隧道氧化物层擦除EEPROM单元。

10. 发明授权

US06207989B1 Non-volatile memory device having a high-reliability composite insulation layer 失效
标题翻译：具有高可靠性复合绝缘层的非易失性存储器件
公开(公告)号：US06207989B1
公开(公告)日：2001-03-27
申请号：US09268897
申请日：1999-03-16
申请人： Xiao-Yu Li , Sunil D. Mehta
发明人： Xiao-Yu Li , Sunil D. Mehta
IPC分类号： H01L2976
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11558
摘要： A non-volatile memory device includes a floating-gate electrode overlying a tunnel oxide layer. A portion of the floating-gate electrode forms the control gate electrode for a sense transistor that is used to determine the presence of charge on the floating-gate electrode. A composite insulation layer overlies the floating-gate electrode. The composite insulation layer includes a dielectric layer, a doped insulating layer overlying the dielectric layer, and a planarization layer overlying the doped insulating layer. The thicknesses of the dielectric layer and the doped insulating layer are precisely determined, such that the doped insulating layer getters mobile ions, such as hydrogen ions, away from the floating-gate electrode, while not capacitively coupling with the floating-gate electrode. In a preferred embodiment of the invention, the dielectric layer has a thickness of about 450 to about 550 Å, and the doped insulating layer has a thickness of about 2900 to about 3100 Å, and the planarization layer has a thickness of about 6000 to 8000 Å.
摘要翻译：非易失性存储器件包括覆盖隧道氧化物层的浮栅电极。浮栅电极的一部分形成用于确定浮栅电极上电荷存在的读出晶体管的控制栅电极。复合绝缘层覆盖浮栅电极。复合绝缘层包括电介质层，覆盖电介质层的掺杂绝缘层和覆盖掺杂绝缘层的平坦化层。电介质层和掺杂绝缘层的厚度被精确地确定，使得掺杂的绝缘层在不与浮栅电极电容耦合的同时将诸如氢离子的移动离子吸引到浮栅电极。在本发明的优选实施例中，电介质层的厚度为约450至约550，掺杂绝缘层的厚度为约2900至约3100，平坦化层的厚度为约6000至8000 一个。

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