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1. 发明授权

US06326663B1 Avalanche injection EEPROM memory cell with P-type control gate 失效
标题翻译：雪崩注入EEPROM存储单元，带P型控制门
公开(公告)号：US06326663B1
公开(公告)日：2001-12-04
申请号：US09277441
申请日：1999-03-26
申请人： Xiao-Yu Li , Steven J. Fong , Sunil D. Mehta
发明人： Xiao-Yu Li , Steven J. Fong , Sunil D. Mehta
IPC分类号： H01L29788
CPC分类号： H01L27/11517 , H01L27/115
摘要： A non-volatile memory cell, comprising a semiconductor substrate having a first conductivity type. A control region is formed of said first conductivity type in the substrate and a control region oxide formed over the control region. The cell includes a program element having a first active region of a second conductivity type formed in said substrate, a doped or implanted region adjacent to said first active region, and a gate oxide overlying at least the channel region. An active region oxide covers a portion of the first active region. A floating gate is formed over said semiconductor substrate on said active region oxide and said control region oxide.
摘要翻译：一种非易失性存储单元，包括具有第一导电类型的半导体衬底。控制区域由衬底中的所述第一导电类型形成，并且在控制区域上形成控制区氧化物。单元包括具有形成在所述衬底中的第二导电类型的第一有源区，与所述第一有源区相邻的掺杂或注入区以及覆盖至少沟道区的栅极氧化物的程序元件。有源区氧化物覆盖第一有源区的一部分。在所述有源区氧化物和所述控制区氧化物上的所述半导体衬底上形成浮栅。

2. 发明授权

US6064595A Floating gate memory apparatus and method for selected programming thereof 有权
标题翻译：浮栅存储装置及其选择编程方法
公开(公告)号：US6064595A
公开(公告)日：2000-05-16
申请号：US220201
申请日：1998-12-23
申请人： Stewart G. Logie , Sunil D. Mehta , Steven J. Fong
发明人： Stewart G. Logie , Sunil D. Mehta , Steven J. Fong
IPC分类号： H01L21/8247 , G11C16/04 , G11C16/10 , H01L27/115 , H01L29/788 , H01L29/792 , G11C13/00
CPC分类号： G11C16/0441 , G11C16/10 , H01L29/7886
摘要： A method of creating a reverse breakdown condition in an array of memory cells arranged in columns and rows in the array, and an array structure are provided. The method comprises the steps of applying a first voltage on a first column connection coupling a first column of said cells, and a second voltage on a second column connection coupling a second column of said cells; and applying a third voltage on a first row connection coupling a first row of said cells, and applying said second voltage on a second row connection coupling a second row of said cells. In this aspect, the difference between the first voltage and the third voltage creates said reverse breakdown condition in at least one cell occupying said first column and first row. In a further aspect, each cell includes a floating gate and the method of the invention includes the step of programming one of said cells by coupling a control voltage to each floating gate. The structure includes a substrate having formed therein at least an Nth or Mth row-wise oriented well, each well isolated from adjacent ones of said wells. Also provided are at least an Nth and Mth word bit line formed by an Nth and Mth impurity regions in said substrate and at least an Nth and Mth array control gate lines. A plurality of memory cells, each cell formed in at least said Nth or Mth row-wise well, is further provided. Each cell comprises a drain, a floating gate, a drain connection one of said Nth or Mth word bit line (WBL), and a substrate well connection to one of said Nth or Mth wells, and a control gate connection to one of said Nth or Mth array control gate lines(ACG).
摘要翻译：提供了在阵列中以行和列排列的存储单元阵列中产生反向故障条件的方法，以及阵列结构。该方法包括以下步骤：在耦合所述单元的第一列的第一列连接上施加第一电压，以及在耦合所述单元的第二列的第二列连接上施加第二电压; 以及在耦合所述单元的第一行的第一行连接上施加第三电压，以及将耦合所述单元的第二行的第二行连接上施加所述第二电压。在这方面，第一电压和第三电压之间的差异在占据所述第一列和第一行的至少一个单元中产生所述反向击穿条件。在另一方面，每个单元包括浮动栅极，并且本发明的方法包括通过将控制电压耦合到每个浮动栅极来编程所述单元之一的步骤。该结构包括在其中形成有至少第N或第M行行取向阱的衬底，每个阱与相邻的所述阱分离。还提供了由所述衬底中的第N和第M杂质区形成的至少第N和第M字位线以及至少第N和第M阵列控制栅极线。还提供多个存储单元，每个单元形成在至少所述第N或第M行列井中。每个单元包括所述第N或第M字位线（WBL）之一的漏极，浮置栅极，漏极连接以及与所述第N或第M阱之一的衬底阱连接，以及到所述第N个或第M阵列控制栅极线（ACG）。

3. 发明授权

US06215700B1 PMOS avalanche programmed floating gate memory cell structure 失效
标题翻译： PMOS雪崩编程浮栅存储单元结构
公开(公告)号：US06215700B1
公开(公告)日：2001-04-10
申请号：US09226702
申请日：1999-01-07
申请人： Steven J. Fong , Stewart G. Logie , Sunil D. Mehta
发明人： Steven J. Fong , Stewart G. Logie , Sunil D. Mehta
IPC分类号： G11C1604
CPC分类号： H01L27/115 , G11C16/0433 , G11C2216/10
摘要： A non-volatile memory cell structure which includes a floating gate, a reverse breakdown element and a read transistor. The reverse breakdown element is at least partially formed in a first region of a first conductivity type in a semiconductor substrate, and underlies a portion of the floating gate; and the read transistor is at least partially formed in the first region and connected to the reverse breakdown element. In a further embodiment a control gate is capacitively coupled to the floating gate and is formed in a second region of the substrate, outside the well region.
摘要翻译：一种包括浮动栅极，反向击穿元件和读取晶体管的非易失性存储单元结构。反向击穿元件至少部分地形成在半导体衬底中的第一导电类型的第一区域中，并且位于浮置栅极的一部分下方; 并且读取晶体管至少部分地形成在第一区域中并连接到反向击穿元件。在另一个实施例中，控制栅极电容耦合到浮置栅极，并且形成在衬底的第二区域中，在阱区域外部。

4. 发明授权

US06294810B1 EEPROM cell with tunneling at separate edge and channel regions 失效
标题翻译： EEPROM单元在分离的边缘和通道区域进行隧穿
公开(公告)号：US06294810B1
公开(公告)日：2001-09-25
申请号：US09218987
申请日：1998-12-22
申请人： Xiao-Yu Li , Steven J. Fong
发明人： Xiao-Yu Li , Steven J. Fong
IPC分类号： H01L29792
CPC分类号： G11C16/0441 , H01L27/115
摘要： An EEPROM cell is described that is programmed and erased by electron tunneling at separate regions, an edge of a tunneling drain and a sense transistor channel. The EEPROM cell has three transistors formed in a semiconductor substrate. The three transistors are a tunneling transistor (NMOS), a sense transistor (NMOS) and a read transistor (NMOS). Electron tunneling occurs to program the EEPROM cell through a sense tunnel oxide layer by electron tunneling across an entire portion of a sense channel upon incurrence of a sufficient voltage potential between a floating gate and the sense channel. Electron tunneling also occurs to erase the EEPROM cell through a tunnel oxide layer be electron tunneling at an edge of a tunneling drain upon incurrence of a sufficient voltage potential between the floating gate and the tunneling drain.
摘要翻译：描述了通过在分开的区域，隧道漏极的边缘和感测晶体管沟道处的电子隧穿来编程和擦除的EEPROM单元。 EEPROM单元具有形成在半导体衬底中的三个晶体管。三个晶体管是隧道晶体管（NMOS），感测晶体管（NMOS）和读取晶体管（NMOS）。发生电子隧穿，以在浮动栅极和感测通道之间发生足够的电压电势时，通过感测通道氧化物层来对EEPROM单元进行编程，以便在感测通道的整个部分上进行电子隧穿。还发生电子隧穿，以通过隧道氧化物层擦除EEPROM电池，在隧穿漏极的边缘处电子隧穿，在浮动栅极和隧道漏极之间发生足够的电压电势。

5. 发明授权

US06404006B2 EEPROM cell with tunneling across entire separated channels 失效
标题翻译： EEPROM单元，穿过整个分离的通道
公开(公告)号：US06404006B2
公开(公告)日：2002-06-11
申请号：US09203149
申请日：1998-12-01
申请人： Xiao-Yu Li , Steven J. Fong
发明人： Xiao-Yu Li , Steven J. Fong
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , G11C16/0441 , H01L27/115 , H01L27/11558
摘要： An EEPROM cell is described that is programmed and erased by electron tunneling across an entire portion of separate transistor channels. The EEPROM cell has three transistors formed in a semiconductor substrate. The three transistors are a tunneling transistor (PMOS), a sense transistor (NMOS) and a read transistor (NMOS). Electron tunneling occurs to program the EEPROM cell through a sense tunnel oxide layer having a thickness to allow the electron tunneling across an entire portion of a sense channel upon incurrence of a sufficient voltage potential between a floating gate and the tunnel channel. Electron tunneling also occurs to erase the EEPROM cell through a tunnel oxide layer having a thickness to allow electron tunneling across an entire portion of a tunneling channel upon incurrence of a sufficient voltage potential between the floating gate and the tunneling channel.
摘要翻译：描述了通过遍及分离的晶体管通道的整个部分的电子隧道编程和擦除的EEPROM单元。 EEPROM单元具有形成在半导体衬底中的三个晶体管。三个晶体管是隧道晶体管（PMOS），感测晶体管（NMOS）和读取晶体管（NMOS）。发生电子隧穿，以通过具有厚度的感测隧道氧化物层对EEPROM单元进行编程，以便在浮动栅极和隧道通道之间发生足够的电压电势时允许跨越感测通道的整个部分的电子隧穿。还发生电子隧穿，以通过具有厚度的隧道氧化物层擦除EEPROM电池，以在浮动栅极和隧道通道之间发生足够的电压电势时允许穿过隧道通道的整个部分的电子隧穿。

6. 发明授权

US06294811B1 Two transistor EEPROM cell 失效
标题翻译：两个晶体管EEPROM单元
公开(公告)号：US06294811B1
公开(公告)日：2001-09-25
申请号：US09245813
申请日：1999-02-05
申请人： Steven J. Fong , Xiao-Yu Li
发明人： Steven J. Fong , Xiao-Yu Li
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , G11C16/0433 , H01L27/115 , H01L27/11558 , H01L29/7883
摘要： A two transistor EEPROM cell is described that is erased by electron tunneling across an entire portion of a tunneling channel and programmed by electron tunneling at an edge of a tunneling drain.
摘要翻译：描述了两个晶体管EEPROM单元，其通过穿过隧道通道的整个部分的电子隧穿而被擦除，并且通过在隧道漏极的边缘处的电子隧道编程。

7. 发明授权

US08539409B1 Simultaneous development of complementary IC families 有权
标题翻译：互补IC家族同时发展
公开(公告)号：US08539409B1
公开(公告)日：2013-09-17
申请号：US13178599
申请日：2011-07-08
申请人： Shawn Murray , John Schadt , Steven J. Fong , Luan Phoc Chau , Thomas R. Gustafson
发明人： Shawn Murray , John Schadt , Steven J. Fong , Luan Phoc Chau , Thomas R. Gustafson
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： Two (or more) different, but complementary, families of integrated circuits having the same layout are developed simultaneously where the different families are achieved by changing one or more design parameters of transistors used to implement the integrated circuits. For example, a low-power (but low-speed) family of one or more ICs (e.g., for handheld applications) can be achieved by designing at least some transistors with relatively high threshold-voltage (Vt) levels, while a different, but complementary, high-speed (but high-power) family of one or more ICs (e.g., for server applications) can be achieved by designing corresponding transistors with relatively low Vt levels. In this way, the two families can share in common all but a very few masks used to fabricate the ICs of the different families.
摘要翻译：同时开发具有相同布局的两个（或更多）不同但互补的集成电路系列，其中通过改变用于实现集成电路的晶体管的一个或多个设计参数来实现不同系列。例如，可以通过设计至少一些具有相对高的阈值电压（Vt）电平的晶体管来实现一个或多个IC的低功率（但是低速）系列（例如用于手持应用）但是可以通过设计具有相对较低Vt电平的相应晶体管来实现一个或多个IC（例如，用于服务器应用）的互补的高速（但是高功率）系列。这样一来，这两个家庭可以共同分享，只有很少的面具用于制造不同家庭的IC。

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