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1. 发明授权

US07353438B2 Transparent error correcting memory 失效
标题翻译：透明错误纠正内存
公开(公告)号：US07353438B2
公开(公告)日：2008-04-01
申请号：US10645861
申请日：2003-08-20
申请人： Wingyu Leung , Kit Sang Tam , Mikolaj Tworek , Fu-Chieh Hsu
发明人： Wingyu Leung , Kit Sang Tam , Mikolaj Tworek , Fu-Chieh Hsu
IPC分类号： G11C29/00
CPC分类号： G06F11/1048
摘要： A memory system with transparent error correction circuitry provides full stuck-at fault coverage for both test data patterns and the corresponding error correction code (ECC) values. The memory system includes a semiconductor memory having a memory array, a memory interface and an error detection/correction unit. The memory array is configured to store test data patterns and corresponding error correction code (ECC) values. The memory interface is configured such that the ECC values are not directly accessible. The error detection/correction unit is configured to correct single-bit errors in the test data patterns and corresponding ECC values. A set of test data patterns associated with the semiconductor memory is selected such that any multiple-bit error in a test data pattern and the corresponding ECC value causes the error detection/correction unit to provide an output data pattern having an error, thereby rendering multiple-bit faults 100% detectable.
摘要翻译：具有透明误差校正电路的存储器系统为测试数据模式和相应的纠错码（ECC）值提供完全卡住的故障覆盖。存储器系统包括具有存储器阵列，存储器接口和错误检测/校正单元的半导体存储器。存储器阵列被配置为存储测试数据模式和相应的纠错码（ECC）值。存储器接口被配置为使得ECC值不能直接访问。错误检测/校正单元被配置为校正测试数据模式中的单位错误和对应的ECC值。选择与半导体存储器相关联的一组测试数据模式，使得测试数据模式中的任何多位错误和相应的ECC值导致错误检测/校正单元提供具有错误的输出数据模式，从而渲染多个位错误100％可检测。

2. 发明授权

US07206913B2 High speed memory system 有权
标题翻译：高速存储系统
公开(公告)号：US07206913B2
公开(公告)日：2007-04-17
申请号：US10927157
申请日：2004-08-25
申请人： Fu-Chieh Hsu , Wingyu Leung
发明人： Fu-Chieh Hsu , Wingyu Leung
IPC分类号： G06F12/00
CPC分类号： G06F12/0893 , G06F12/0855 , G06F12/0879 , G06F12/0897 , G06F12/10 , G11C7/10 , G11C7/1018 , G11C7/1051 , G11C7/1069 , G11C7/1078 , G11C7/1096 , G11C11/406 , G11C11/4076 , G11C11/4096
摘要： A method and structure for implementing a DRAM memory array as a second level cache memory in a computer system. The computer system includes a central processing unit (CPU), a first level SRAM cache memory, a CPU bus coupled to the CPU, and second level cache memory which includes a DRAM array coupled to the CPU bus. When accessing the DRAM array, row access and column decoding operations are performed in a self-timed asynchronous manner. Predetermined sequences of column select operations are then performed in a synchronous manner with respect to a clock signal. A widened data path is provided to the DRAM array, effectively increasing the data rate of the DRAM array. By operating the DRAM array at a higher data rate than the CPU bus, additional time is provided for precharging the DRAM array. As a result, precharging of the DRAM array is transparent to the CPU bus.
摘要翻译：一种用于在计算机系统中实现DRAM存储器阵列作为第二级高速缓冲存储器的方法和结构。计算机系统包括中央处理单元（CPU），第一级SRAM缓存存储器，耦合到CPU的CPU总线以及包括与CPU总线耦合的DRAM阵列的第二级高速缓冲存储器。当访问DRAM阵列时，以自定时的异步方式执行行访问和列解码操作。然后以相对于时钟信号的同步方式执行列选择操作的预定序列。向DRAM阵列提供加宽的数据路径，有效地增加DRAM阵列的数据速率。通过以比CPU总线更高的数据速率操作DRAM阵列，为DRAM阵列预充电提供了额外的时间。因此，DRAM阵列的预充电对于CPU总线是透明的。

3. 发明申请

US20050027929A1 High speed memory system 有权
标题翻译：高速存储系统
公开(公告)号：US20050027929A1
公开(公告)日：2005-02-03
申请号：US10927157
申请日：2004-08-25
申请人： Fu-Chieh Hsu , Wingyu Leung
发明人： Fu-Chieh Hsu , Wingyu Leung
IPC分类号： G06F12/00 , G06F12/06 , G06F12/08
CPC分类号： G06F12/0893 , G06F12/0855 , G06F12/0879 , G06F12/0897 , G06F12/10 , G11C7/10 , G11C7/1018 , G11C7/1051 , G11C7/1069 , G11C7/1078 , G11C7/1096 , G11C11/406 , G11C11/4076 , G11C11/4096
摘要： A method and structure for implementing a DRAM memory array as a second level cache memory in a computer system. The computer system includes a central processing unit (CPU), a first level SRAM cache memory, a CPU bus coupled to the CPU, and second level cache memory which includes a DRAM array coupled to the CPU bus. When accessing the DRAM array, row access and column decoding operations are performed in a self-timed asynchronous manner. Predetermined sequences of column select operations are then performed in a synchronous manner with respect to a clock signal. A widened data path is provided to the DRAM array, effectively increasing the data rate of the DRAM array. By operating the DRAM array at a higher data rate than the CPU bus, additional time is provided for precharging the DRAM array. As a result, precharging of the DRAM array is transparent to the CPU bus.
摘要翻译：一种用于在计算机系统中实现DRAM存储器阵列作为第二级高速缓冲存储器的方法和结构。计算机系统包括中央处理单元（CPU），第一级SRAM缓存存储器，耦合到CPU的CPU总线以及包括与CPU总线耦合的DRAM阵列的第二级高速缓冲存储器。当访问DRAM阵列时，以自定时的异步方式执行行访问和列解码操作。然后以相对于时钟信号的同步方式执行列选择操作的预定序列。向DRAM阵列提供加宽的数据路径，有效地增加了DRAM阵列的数据速率。通过以比CPU总线更高的数据速率操作DRAM阵列，为DRAM阵列预充电提供了额外的时间。因此，DRAM阵列的预充电对于CPU总线是透明的。

4. 发明授权

US06754746B1 Memory array with read/write methods 失效
标题翻译：具有读/写方式的内存数组
公开(公告)号：US06754746B1
公开(公告)日：2004-06-22
申请号：US09535656
申请日：2000-03-23
申请人： Wingyu Leung , Winston Lee , Fu-Chieh Hsu
发明人： Wingyu Leung , Winston Lee , Fu-Chieh Hsu
IPC分类号： G06F1300
CPC分类号： H04L25/026 , G06F13/40 , G06F13/4072 , G06F13/4077
摘要： Improved circuitry for connecting the memory array to a data bus allows for high speed accessing of the memory array. Sense amplifier latches are coupled to each column of memory cells. The latched sense amplifiers are coupled to decoders which, in turn, are coupled to data amplifiers. The data amplifiers are coupled to a data bus. Data being read from or written to the memory cells is via the sense amplifier latches, the decoders, and data amplifiers.
摘要翻译：用于将存储器阵列连接到数据总线的改进的电路允许存储器阵列的高速存取。读出放大器锁存器耦合到每列存储器单元。锁存的读出放大器耦合到解码器，解码器又耦合到数据放大器。数据放大器耦合到数据总线。通过读出放大器锁存器，解码器和数据放大器读取或写入存储器单元的数据。

5. 发明授权

US06509595B1 DRAM cell fabricated using a modified logic process and method for operating same 失效
标题翻译：使用改进的逻辑处理和操作方法制造的DRAM单元
公开(公告)号：US06509595B1
公开(公告)日：2003-01-21
申请号：US09427383
申请日：1999-10-25
申请人： Wingyu Leung , Fu-Chieh Hsu
发明人： Wingyu Leung , Fu-Chieh Hsu
IPC分类号： H01L31119
CPC分类号： H01L27/10852 , G11C5/147 , G11C8/08 , G11C11/4074 , G11C11/4085 , G11C2207/104 , H01L27/1085 , H01L27/10873 , H01L28/91
摘要： A memory system that includes a dynamic random access memory (DRAM) cell that includes an access transistor and a storage capacitor. The storage capacitor of the DRAM cell is fabricated by forming a polysilicon crown electrode, a dielectric layer overlying the polysilicon crown, and a polysilicon plate electrode overlying the dielectric layer. A first set of thermal cycles are performed during the formation of the storage capacitor to form and anneal the elements of the capacitor structure. After the first set of thermal cycles are complete, shallow P+ and/or N+ regions are formed by ion implantation, and metal salicide is formed. As a result, the relatively high first set of thermal cycles required to form the capacitor structure does not adversely affect the shallow P+ and N+ regions or the metal salicide. A second set of thermal cycles, which are comparable to or less than the first set of thermal cycles, are performed during the formation of the shallow regions and the metal salicide. The DRAM cell is operated in response to a word line driver that is controlled to provide a positive boosted voltage and a negative boosted voltage to the word line, thereby controlling access to the DRAM cell. The positive boosted voltage is greater than Vdd but less than Vdd plus the absolute value of a transistor threshold voltage Vt. Similarly, the negative boosted voltage generator is less than VSS by an amount less than Vt.
摘要翻译：一种包括动态随机存取存储器（DRAM）单元的存储器系统，其包括存取晶体管和存储电容器。 DRAM单元的存储电容器通过形成多晶硅冠状电极，覆盖多晶硅冠的电介质层和覆盖在电介质层上的多晶硅板电极来制造。在形成存储电容器期间执行第一组热循环以形成和退火电容器结构的元件。在第一组热循环完成后，通过离子注入形成浅的P +和/或N +区，形成金属硅化物。结果，形成电容器结构所需的相对较高的第一组热循环不会对浅的P +和N +区域或金属硅化物产生不利影响。在浅区域和金属硅化物的形成期间执行第二组热循环，其与第一组热循环相当或者小于第一组热循环。响应于字线驱动器操作DRAM单元，该字线驱动器被控制以向该字线提供正升压电压和负升压电压，从而控制对DRAM单元的访问。正升压电压大于Vdd但小于Vdd加上晶体管阈值电压Vt的绝对值，类似地，负升压电压小于VSS的量小于Vt。

6. 发明授权

US5729152A Termination circuits for reduced swing signal lines and methods for operating same 失效
标题翻译：用于减少摆动信号线的终端电路及其操作方法
公开(公告)号：US5729152A
公开(公告)日：1998-03-17
申请号：US549610
申请日：1995-10-27
申请人： Wingyu Leung , Winston Lee , Fu-Chieh Hsu
发明人： Wingyu Leung , Winston Lee , Fu-Chieh Hsu
IPC分类号： G11C11/41 , G06F3/00 , G06F12/16 , G06F13/16 , G06F13/40 , G11C7/00 , G11C11/401 , G11C11/407 , G11C11/417 , G11C29/00 , G11C29/04 , H04L25/02 , H03K17/16
CPC分类号： H04L25/028 , G06F13/40 , G06F13/4072 , G06F13/4077 , H04L25/026 , H04L25/0292 , Y02B60/1228 , Y02B60/1235
摘要： A memory device which utilizes a plurality of memory modules coupled in parallel to a master I/O module through a single directional asymmetrical signal swing (DASS) bus. This structure provides an I/O scheme having symmetrical swing around half the supply voltage, high through-put, high data bandwidth, short access time, low latency and high noise immunity. The memory device utilizes improved column access circuitry including an improved address sequencing circuit and a data amplifier within each memory module. The memory device includes a resynchronization circuit which allows the device to operate either synchronously and asynchronously using the same pins. Each memory module has independent address and command decoders to enable independent operation. Thus, each memory module is activated by commands on the DASS bus only when a memory access operation is performed within the particular memory module. The memory device includes redundant memory modules to replace defective memory modules. Replacement can be carried out through commands on the DASS bus. The memory device can be configured to simultaneously write a single input data stream to multiple memory modules or to perform high-speed interleaved read and write operations. In one embodiment, multiple memory devices are coupled to a common, high-speed I/O bus without requiring large bus drivers and complex bus receivers in the memory modules.
摘要翻译：一种存储器件，其利用通过单向非对称信号摆幅（DASS）总线并联到主I / O模块的多个存储器模块。这种结构提供了一个在电源电压的一半左右，高输入，高数据带宽，短访问时间，低延迟和高抗噪声的对称摆动的I / O方案。存储器件利用改进的列存取电路，包括改进的地址排序电路和每个存储器模块内的数据放大器。存储器件包括再同步电路，其允许器件使用相同的引脚同步和异步地操作。每个存储器模块具有独立的地址和命令解码器，以实现独立操作。因此，只有当在特定存储器模块内执行存储器访问操作时，每个存储器模块才被DASS总线上的命令激活。存储器件包括用于替换有缺陷的存储器模块的冗余存储器模块。可以通过DASS总线上的命令进行更换。存储器件可被配置为将单个输入数据流同时写入多个存储器模块或执行高速交错读写操作。在一个实施例中，多个存储器件耦合到公共的高速I / O总线，而不需要存储器模块中的大的总线驱动器和复杂的总线接收器。

7. 发明授权

US5498990A Reduced CMOS-swing clamping circuit for bus lines 失效
标题翻译：减少用于总线的CMOS摆幅钳位电路
公开(公告)号：US5498990A
公开(公告)日：1996-03-12
申请号：US417511
申请日：1995-04-05
申请人： Wingyu Leung , Winston Lee , Fu-Chieh Hsu
发明人： Wingyu Leung , Winston Lee , Fu-Chieh Hsu
IPC分类号： G06F5/16 , G06F11/00 , G06F11/10 , G06F11/20 , G06F12/06 , G06F13/40 , G11C29/00 , G11C29/48 , H01L21/66 , H01L27/02 , H04L25/02 , H03K5/08
CPC分类号： H04L25/026 , G06F12/0661 , G06F13/4077 , G06F5/16 , G11C29/006 , G11C29/48 , G11C29/76 , G11C29/808 , G11C29/832 , G11C29/88 , H01L22/22 , G06F11/006 , G06F11/10 , G06F11/1666 , H01L27/0203 , Y02B60/1225 , Y02B60/1228 , Y02B60/1235
摘要： A memory system having several memory devices coupled to a memory controller through an I/O bus, each memory device including multiple memory modules coupled to a chip I/O interface through an internal bus. The system includes a circuit for driving the I/O bus with a reduced CMOS-swing, a circuit for driving the internal bus with a full CMOS-swing in one bus direction and with a reduced CMOS-swing in the other bus direction, a column address generation circuit for allowing sequentially addressed data to be accessed with the decoder delay being eliminated, and a circuit for re-synchronizing data from a source clock to a destination clock with reduced access latency penalty. Simultaneously writing data into multiple circuit modules significantly increases the write bandwidth of the memory. Also included are a dynamic base-address mapping into an address space, a read or write operation across multiple memory modules, a novel I/O bus format, and a protocol and test mode for testing redundant memory sub-arrays.
摘要翻译：具有通过I / O总线耦合到存储器控制器的几个存储器件的存储器系统，每个存储器件包括通过内部总线耦合到芯片I / O接口的多个存储器模块。该系统包括用于以减小的CMOS摆动驱动I / O总线的电路，用于在一个总线方向上以完全CMOS摆动驱动内部总线并且在另一个总线方向上以减小的CMOS摆幅驱动内部总线的电路列地址产生电路，用于允许在解码器延迟被消除的情况下访问顺序寻址的数据;以及电路，用于将来自源时钟的数据重新同步到具有降低的访问延迟代价的目的地时钟。同时将数据写入多个电路模块会显着增加存储器的写入带宽。还包括动态基地址映射到地址空间，跨多个存储器模块的读或写操作，新颖的I / O总线格式以及用于测试冗余存储器子阵列的协议和测试模式。

8. 发明申请

US20080209303A1 Error Detection/Correction Method 审中-公开
标题翻译：错误检测/校正方法
公开(公告)号：US20080209303A1
公开(公告)日：2008-08-28
申请号：US12043527
申请日：2008-03-06
申请人： Wingyu Leung , Fu-Chieh Hsu
发明人： Wingyu Leung , Fu-Chieh Hsu
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H04L25/0272 , G06F11/006 , G06F11/10 , G06F11/1032 , G06F11/2007 , G06F12/0661 , G06F13/4077 , G11C5/04 , G11C29/006 , G11C29/08 , G11C29/48 , G11C29/76 , G11C29/808 , G11C29/81 , G11C29/832 , G11C29/88 , G11C2029/0401 , G11C2029/0411 , G11C2029/4402 , H01L22/22 , H01L27/0203 , H04L5/1461 , H04L25/026 , H04L25/028 , H04L25/029 , H04L25/0292 , Y10S257/907
摘要： A method for error detection and correction (EDC) includes: generating a complete EDC code in response to a data packet; distributing the complete EDC code among the data packet to create a plurality of bytes, each including a data portion from the data packet and an EDC code portion from the complete EDC code; storing the bytes in a memory module; retrieving the bytes from the memory module; forwarding the data portions of the bytes retrieved from the memory module to a requesting device; providing the data portions of the bytes retrieved from the memory module to an EDC functional block; providing the EDC code portions of the bytes retrieved from the memory module to the EDC functional block; and performing error checking and correction in the EDC functional block upon receiving the complete EDC code from the provided EDC code portions.
摘要翻译：一种用于错误检测和校正（EDC）的方法包括：响应于数据包产生完整的EDC码; 在数据分组中分发完整的EDC代码以创建多个字节，每个字节包括来自数据分组的数据部分和来自完整EDC代码的EDC代码部分; 将字节存储在存储器模块中; 从存储器模块检索字节; 将从存储器模块检索的字节的数据部分转发到请求设备; 将从存储器模块检索的字节的数据部分提供给EDC功能块; 将从存储器模块检索的字节的EDC代码部分提供给EDC功能块; 并且在从所提供的EDC代码部分接收到完整的EDC代码时，在EDC功能块中执行错误校验和校正。

9. 发明授权

US06654295B2 Reduced topography DRAM cell fabricated using a modified logic process and method for operating same 有权
公开(公告)号：US06654295B2
公开(公告)日：2003-11-25
申请号：US10043386
申请日：2002-01-11
申请人： Wingyu Leung , Fu-Chieh Hsu
发明人： Wingyu Leung , Fu-Chieh Hsu
IPC分类号： G11C1604
CPC分类号： G11C5/147 , G11C8/08 , G11C11/4074 , G11C11/4085 , G11C2207/104 , H01L21/76895 , H01L27/0214 , H01L27/10835 , H01L27/1085 , H01L27/10852 , H01L27/10873 , H01L28/86 , H01L28/91
摘要： A memory system that includes a DRAM cell that includes an access transistor and a storage capacitor. The storage capacitor is fabricated by forming a polysilicon crown electrode, a dielectric layer overlying the polysilicon crown, and a polysilicon plate electrode overlying the dielectric layer. A first set of thermal cycles are performed during the formation of the storage capacitor to form and anneal the elements of the capacitor structure. Subsequently, shallow P+ and/or N+ regions are formed by ion implantation, and metal salicide is formed. As a result, the relatively high first set of thermal cycles required to form the capacitor structure does not adversely affect the shallow P+ and N+ regions or the metal salicide. A second set of thermal cycles, which are comparable to or less than the first set of thermal cycles, are performed during the formation of the shallow regions and the metal salicide.

10. 发明授权

US5999474A Method and apparatus for complete hiding of the refresh of a semiconductor memory 有权
标题翻译：完全隐藏半导体存储器更新的方法和装置
公开(公告)号：US5999474A
公开(公告)日：1999-12-07
申请号：US165228
申请日：1998-10-01
申请人： Wingyu Leung , Fu-Chieh Hsu
发明人： Wingyu Leung , Fu-Chieh Hsu
IPC分类号： G11C11/41 , G06F12/00 , G06F12/08 , G11C11/00 , G11C11/401 , G11C11/403 , G11C11/406 , G11C11/407 , G11C11/413 , G11C7/00
CPC分类号： G11C11/40618 , G06F12/0893 , G11C11/005 , G11C11/406 , G06F2212/3042
摘要： A method and apparatus for handling the refresh of a DRAM array or other memory array that requires periodic refresh operations. The method and apparatus handles external accesses and refresh operations such that the refresh operations do not interfere with the external accesses under any conditions. As a result, an SRAM compatible device can be built from DRAM or 1-Transistor cells. The apparatus includes a multi-bank DRAM memory and an SRAM cache that stores the most recently accessed data. Each of the DRAM banks is operated with independent control, thereby enabling parallel refresh operations and read-write accesses to different banks. The capacity of the SRAM cache is selected such that refresh operations can be carried out even under the condition of indefinite 100% access of the multi-bank DRAM memory.
摘要翻译：一种用于处理需要周期性刷新操作的DRAM阵列或其他存储器阵列的刷新的方法和装置。该方法和装置处理外部访问和刷新操作，使得刷新操作在任何情况下不干扰外部访问。因此，可以从DRAM或1晶体管单元构建SRAM兼容器件。该装置包括存储最近访问的数据的多存储体DRAM存储器和SRAM高速缓存。每个DRAM组都通过独立的控制进行操作，从而实现对不同存储区的并行刷新操作和读写访问。选择SRAM缓存的容量，使得即使在多存储器DRAM存储器的100％无限访问的条件下也可以执行刷新操作。

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