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1. 发明授权

US09312262B2 Dynamic random access memory unit and fabrication method thereof 有权
标题翻译：动态随机存取存储单元及其制造方法
公开(公告)号：US09312262B2
公开(公告)日：2016-04-12
申请号：US14256033
申请日：2014-04-18
申请人： INOTERA MEMORIES, INC.
发明人： Tzung-Han Lee
IPC分类号： H01L27/00 , H01L27/108 , H01L29/78 , H01L21/762
CPC分类号： H01L27/10823 , H01L21/76224 , H01L27/10814 , H01L27/10817 , H01L27/10835 , H01L27/10841 , H01L27/10855 , H01L27/10864 , H01L27/10867 , H01L27/1087 , H01L27/10876 , H01L27/10885 , H01L29/7827
摘要： A dynamic random access memory unit includes a substrate having a trench disposed therein, a self-aligned trench isolation structure formed in the bottom portion of the trench, and a first trenched gate formed in the bottom portion of the trench and above the self-aligned trench isolation structure. The substrate includes at least one pillar-shaped active body having a drain region, a body region atop the drain region, and a source region atop the body region. The first trenched gate includes a first spacer formed on the side-wall in the bottom portion of the trench to selectively cover and surround the portion of the side-wall in the trench that comprises the drain region, such for defining the width of the self-aligned trench isolation structure.
摘要翻译：动态随机存取存储器单元包括其中设置有沟槽的衬底，形成在沟槽底部的自对准沟槽隔离结构，以及形成在沟槽底部的第一沟槽栅极和自对准沟隔离结构。衬底包括至少一个具有漏极区域的柱状有源体，漏极区域顶部的体区域，以及身体区域顶部的源极区域。第一沟槽栅包括形成在沟槽底部的侧壁上的第一隔离层，以选择性地覆盖和围绕包括漏区的沟槽中侧壁的部分，以限定自身的宽度对准沟槽隔离结构。

2. 发明授权

US07763924B2 Dynamic random access memory structure having merged trench and stack capacitors 有权
标题翻译：具有合并沟槽和堆叠电容器的动态随机存取存储器结构
公开(公告)号：US07763924B2
公开(公告)日：2010-07-27
申请号：US12244747
申请日：2008-10-02
申请人： Wen-Kuei Huang
发明人： Wen-Kuei Huang
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L27/10855 , H01L27/10835 , H01L27/1085 , H01L27/10867 , Y10S257/906 , Y10S257/908
摘要： A dynamic random access memory structure includes a recessed-gate transistor disposed in the substrate; a trench capacitor structure disposed in the substrate and electrically connected to a first source/drain of the recessed-gate transistor; a first conductive structure disposed on and contacting the trench capacitor structure; a stack capacitor structure disposed on and contacting the first conductive structure, wherein a bottom electrode of the trench capacitor structure and a top electrode of the stack capacitor structure are electrically connected to serve as a common electrode; and a bit line disposed above a second source/drain of the recessed-gate transistor and electrically connected to the second source/drain, wherein the top of the bit line is lower than the top of the gate conductive layer of the recessed-gate transistor.
摘要翻译：动态随机存取存储器结构包括设置在衬底中的凹入栅极晶体管; 沟槽电容器结构，其设置在所述基板中并电连接到所述凹陷栅极晶体管的第一源极/漏极; 设置在所述沟槽电容器结构上并与所述沟槽电容器结构接触的第一导电结构; 布置在第一导电结构上并与第一导电结构接触的堆叠电容器结构，其中沟槽电容器结构的底部电极和堆叠电容器结构的顶部电极电连接以用作公共电极; 以及设置在所述凹入栅极晶体管的第二源极/漏极上方并电连接到所述第二源极/漏极的位线，其中所述位线的顶部低于所述凹入栅极晶体管的栅极导电层的顶部。

3. 发明授权

US07399679B2 Narrow width effect improvement with photoresist plug process and STI corner ion implantation 有权
标题翻译：使用光刻胶插塞工艺和STI角落离子注入的窄宽度效应改善
公开(公告)号：US07399679B2
公开(公告)日：2008-07-15
申请号：US11288858
申请日：2005-11-29
申请人： Yi-Ming Sheu , Da-Wen Lin , Cheng-Ku Chen , Po-Ying Yeh , Shi-Shung Peng , Chung-Cheng Wu
发明人： Yi-Ming Sheu , Da-Wen Lin , Cheng-Ku Chen , Po-Ying Yeh , Shi-Shung Peng , Chung-Cheng Wu
IPC分类号： H01L21/337 , H01L21/336 , H01L21/76 , H01L21/425
CPC分类号： H01L28/40 , H01L21/31144 , H01L21/76237 , H01L21/823481 , H01L27/10835 , H01L27/10861 , H01L27/1087
摘要： A method to reduce the inverse narrow width effect in NMOS transistors is described. An oxide liner is deposited in a shallow trench that is formed to isolate active areas in a substrate. A photoresist plug is formed in the shallow trench and is recessed below the top of the substrate to expose the top portion of the oxide liner. An angled indium implant through the oxide liner into the substrate is then performed. The plug is removed and an insulator is deposited to fill the trenches. After planarization and wet etch steps, formation of a gate dielectric layer and a patterned gate layer, the NMOS transistor exhibits an improved Vt roll-off of 40 to 45 mVolts for both long and short channels. The improvement is achieved with no degradation in junction or isolation performance. The indium implant dose and angle may be varied to provide flexibility to the process.
摘要翻译：描述了一种在NMOS晶体管中减小反向窄宽度效应的方法。氧化物衬垫沉积在形成为隔离衬底中的有源区域的浅沟槽中。在浅沟槽中形成光致抗蚀剂插塞，并且在衬底的顶部下方凹入以暴露氧化物衬垫的顶部部分。然后进行通过氧化物衬垫到衬底中的成角度的铟植入物。去除插头并沉积绝缘体以填充沟槽。在平坦化和湿蚀刻步骤之后，形成栅极介电层和图案化栅极层，NMOS晶体管对于长沟道和短沟道都表现出改善的Vt滚降为40至45毫伏。在不会降低结或隔离性能的情况下实现改进。可以改变铟注入剂量和角度以提供该过程的灵活性。

4. 发明授权

US07235838B2 Semiconductor device substrate with embedded capacitor 有权
标题翻译：具有嵌入式电容器的半导体器件衬底
公开(公告)号：US07235838B2
公开(公告)日：2007-06-26
申请号：US10881372
申请日：2004-06-30
申请人： Chun-Chieh Lin , Wen-Chin Lee
发明人： Chun-Chieh Lin , Wen-Chin Lee
IPC分类号： H01L27/108
CPC分类号： H01L27/0688 , H01L21/8221 , H01L21/84 , H01L27/10832 , H01L27/10835 , H01L27/10858 , H01L27/10861 , H01L27/1203 , H01L28/55 , H01L28/82
摘要： A method for forming a semiconductor device including a DRAM cell structure comprising a silicon on insulator (SOI) substrate with an embedded capacitor structure including providing a substrate comprising an overlying first electrically insulating layer; forming a first electrically conductive layer on the first electrically insulating layer to form a first electrode; forming a capacitor dielectric layer on the first electrode; forming a second electrically conductive layer on the capacitor dielectric layer to form a second electrode; forming a second electrically insulating layer on the second electrode; and, forming a monocrystalline silicon layer over the second electrode to form an SOI substrate comprising a first capacitor structure.
摘要翻译：一种用于形成半导体器件的方法，该半导体器件包括具有嵌入式电容器结构的绝缘体上硅（SOI）衬底的DRAM单元结构，包括提供包括上覆的第一电绝缘层的衬底; 在所述第一电绝缘层上形成第一导电层以形成第一电极; 在所述第一电极上形成电容器电介质层; 在所述电容器介电层上形成第二导电层以形成第二电极; 在所述第二电极上形成第二电绝缘层; 以及在所述第二电极上形成单晶硅层以形成包括第一电容器结构的SOI衬底。

5. 发明申请

US20060024918A1 Semiconductor memory device and manufacturing method of the same 失效
公开(公告)号：US20060024918A1
公开(公告)日：2006-02-02
申请号：US11236668
申请日：2005-09-28
申请人： Masakazu Hirose , Fukashi Morishita
发明人： Masakazu Hirose , Fukashi Morishita
IPC分类号： H01L21/46
CPC分类号： H01L27/10873 , G11C11/404 , G11C11/4085 , G11C2211/4016 , H01L21/84 , H01L27/0218 , H01L27/10808 , H01L27/10817 , H01L27/10832 , H01L27/10835 , H01L27/10882 , H01L27/10894 , H01L27/1203 , H01L29/78612
摘要： In this semiconductor memory device, a potential clamping region having no insulation layer formed therein is provided in an insulation layer. More specifically, the potential clamping region is formed under a body portion at a position near a first impurity region, and extends to a first semiconductor layer. A body fixing portion is formed in a boundary region between the body portion and the potential clamping region. This structure enables improvement in operation performance without increasing the layout area in the case where a DRAM cell is formed in a SOI (Silicon On Insulator) structure.

6. 发明授权

US06812093B2 Method for fabricating memory cell structure employing contiguous gate and capacitor dielectric layer 失效
标题翻译：使用连续的栅极和电容器介质层制造存储单元结构的方法
公开(公告)号：US06812093B2
公开(公告)日：2004-11-02
申请号：US10401429
申请日：2003-03-28
申请人： Kuo-Chi Tu
发明人： Kuo-Chi Tu
IPC分类号： H01L218242
CPC分类号： H01L27/10867 , H01L27/10835 , H01L27/1087 , H01L28/91 , H01L29/66181 , H01L29/945
摘要： A method for fabricating a memory cell structure provides for fabricating a capacitor within the memory cell structure within an asymmetric trench within an isolation region adjoining an active region such that a capacitor node layer within the capacitor contacts a sidewall of the active region and is electrically connected to a source/drain region within a field effect transistor device fabricated within the active region. The method also employs when fabricating the memory cell structure a contiguous dielectric layer as a gate dielectric layer within the field effect transistor device and a capacitor dielectric layer within the capacitor. The dynamic random access memory cell structure may be efficiently fabricated as an embedded dynamic random access memory cell structure.
摘要翻译：一种用于制造存储单元结构的方法提供了在邻近有源区的隔离区内的非对称沟槽内的存储单元结构内制造电容器，使得电容器内的电容器节点层接触有源区的侧壁并电连接到在有源区内制造的场效应晶体管器件内的源/漏区。当在存储单元结构中制造作为场效应晶体管器件内的栅介质层的连续介质层和电容器内的电容器介质层时，该方法也采用。动态随机存取存储器单元结构可以被有效地制造为嵌入式动态随机存取存储单元结构。

7. 发明申请

US20030236002A1 Capacitor dielectric structure of a dram cell and method for forming thereof 有权
标题翻译：电容器的电容器电介质结构及其形成方法
公开(公告)号：US20030236002A1
公开(公告)日：2003-12-25
申请号：US10376230
申请日：2003-03-03
申请人： PROMOS TECHNOLOGIES INC.
发明人： Yung-Hsien Wu , Cheng-Che Lee
IPC分类号： H01L021/20 , H01L021/31 , H01L021/469
CPC分类号： H01L21/02326 , H01L21/0214 , H01L21/0217 , H01L21/02337 , H01L21/3144 , H01L21/3185 , H01L27/10835 , H01L27/1087 , H01L29/66181
摘要： A capacitor dielectric structure of a deep trench capacitor for a DRAM cell. A semiconductor silicon substrate is provided wit a deep trench. Silicon nitride deposition is used to form a silicon nitride layer on the sidewall and bottom of the deep trench. An oxynitride process with wet oxidation and N2O reactive gas is used to form an oxynitride layer on the silicon nitride layer. A post oxynitride growth annealing is performed on the oxynitride layer.
摘要翻译：用于DRAM单元的深沟槽电容器的电容器电介质结构。半导体硅衬底具有深沟槽。氮化硅沉积用于在深沟槽的侧壁和底部上形成氮化硅层。使用具有湿氧化和N2O反应气体的氧氮化物工艺在氮化硅层上形成氧氮化物层。在氧氮化物层上进行氧氮化后生长退火。

8. 发明申请

US20030057488A1 Semiconductor memory device and manufacturing method of the same 失效
公开(公告)号：US20030057488A1
公开(公告)日：2003-03-27
申请号：US10224317
申请日：2002-08-21
申请人： Mitsubishi Denki Kabushiki Kaisha
发明人： Masakazu Hirose , Fukashi Morishita
IPC分类号： H01L021/00 , H01L029/76 , H01L031/119 , H01L027/01
CPC分类号： H01L27/10873 , G11C11/404 , G11C11/4085 , G11C2211/4016 , H01L21/84 , H01L27/0218 , H01L27/10808 , H01L27/10817 , H01L27/10832 , H01L27/10835 , H01L27/10882 , H01L27/10894 , H01L27/1203 , H01L29/78612
摘要： In this semiconductor memory device, a potential clamping region having no insulation layer formed therein is provided in an insulation layer. More specifically, the potential clamping region is formed under a body portion at a position near a first impurity region, and extends to a first semiconductor layer. A body fixing portion is formed in a boundary region between the body portion and the potential clamping region. This structure enables improvement in operation performance without increasing the layout area in the case where a DRAM cell is formed in a SOI (Silicon On Insulator) structure.

9. 发明授权

US06468887B2 Semiconductor device and a method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06468887B2
公开(公告)日：2002-10-22
申请号：US09906708
申请日：2001-07-18
申请人： Shoichi Iwasa , Tatsuya Kawamata
发明人： Shoichi Iwasa , Tatsuya Kawamata
IPC分类号： H01L213205
CPC分类号： H01L29/785 , H01L21/28273 , H01L21/823425 , H01L27/10823 , H01L27/10826 , H01L27/10835 , H01L27/10861 , H01L27/10876 , H01L27/10879 , H01L29/42324 , H01L29/66545 , H01L29/66795 , H01L29/66818 , H01L29/66825 , H01L29/7881
摘要： In a semiconductor device of this invention, a pillar projection serving as a very thin active region is formed on the surface of a p-type silicon semiconductor substrate. A gate electrode 21 is formed to cover a central portion of the pillar projection. A pair of impurity diffusion layers 22 are formed on the pillar projection on the two sides of the gate electrode. An element isolation insulating film 23 is formed to sandwich and bury the side surfaces of the pillar projection. This semiconductor device has high performance equivalent to that of an SOI structure. The semiconductor device of this invention has three channels corresponding to a pair of a source and a drain, is selectively formed on the same semiconductor substrate as a common bulk transistor, and has a very fine structure and high drivability.
摘要翻译：在本发明的半导体器件中，在p型硅半导体衬底的表面上形成有作为非常薄的有源区的柱状突起。栅电极21形成为覆盖柱状突起的中央部。在栅电极的两侧的支柱突起上形成一对杂质扩散层22。形成元件隔离绝缘膜23以夹住并埋入柱形突起的侧表面。该半导体器件具有与SOI结构相当的高性能。本发明的半导体器件具有与一对源极和漏极对应的三个沟道，其选择性地形成在与公共体晶体管相同的半导体衬底上，并且具有非常精细的结构和高的驾驶性能。

10. 发明申请

US20010052610A1 Reduced topography DRAM cell fabricated using a modified logic process and method for operating same 有权
标题翻译：使用修改的逻辑过程制造的减少的地形DRAM单元和用于操作的方法
公开(公告)号：US20010052610A1
公开(公告)日：2001-12-20
申请号：US09772434
申请日：2001-01-29
发明人： Wingyu Leung , Fu-Chieh Hsu
IPC分类号： H01L029/76 , H01L021/20
CPC分类号： G11C5/147 , G11C8/08 , G11C11/4074 , G11C11/4085 , G11C2207/104 , H01L21/76895 , H01L27/0214 , H01L27/10835 , H01L27/1085 , H01L27/10852 , H01L27/10873 , H01L28/86 , H01L28/91
摘要： A memory system that includes a DRAM cell that includes an access transistor and a storage capacitor. The storage capacitor is fabricated by forming a polysilicon crown electrode, a dielectric layer overlying the polysilicon crown, and a polysilicon plate electrode overlying the dielectric layer. A first set of thermal cycles are performed during the formation of the storage capacitor to form and anneal the elements of the capacitor structure. Subsequently, shallow Pnull and/or Nnull regions are formed by ion implantation, and metal salicide is formed. As a result, the relatively high first set of thermal cycles required to form the capacitor structure does not adversely affect the shallow Pnull and Nnull regions or the metal salicide. A second set of thermal cycles, which are comparable to or less than the first set of thermal cycles, are performed during the formation of the shallow regions and the metal salicide.
摘要翻译：一种包括具有存取晶体管和存储电容器的DRAM单元的存储器系统。存储电容器通过形成多晶硅冠电极，覆盖多晶硅冠的电介质层和覆盖在电介质层上的多晶硅板电极来制造。在形成存储电容器期间执行第一组热循环以形成和退火电容器结构的元件。随后，通过离子注入形成浅的P +和/或N +区，形成金属硅化物。结果，形成电容器结构所需的相对较高的第一组热循环不会对浅的P +和N +区域或金属硅化物产生不利影响。在浅区域和金属硅化物的形成期间执行第二组热循环，其与第一组热循环相当或者小于第一组热循环。

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