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1. 发明授权

US06754760B1 Programmable interface for a configurable system bus 有权
标题翻译：可配置系统总线的可编程接口
公开(公告)号：US06754760B1
公开(公告)日：2004-06-22
申请号：US09644223
申请日：2000-08-21
申请人： Wilson Yee , Brian Fox , Sridhar Krishnamurthy , Bart Reynolds , Steven Winegarden
发明人： Wilson Yee , Brian Fox , Sridhar Krishnamurthy , Bart Reynolds , Steven Winegarden
IPC分类号： G06F1340
CPC分类号： G06F13/4018
摘要： Interface logic is disclosed. The interface logic comprises a first address decoder, a first set of mode logic coupled to the address decoder and a first selector coupled to the first set of mode logic. The interface logic is adaptable to connect the programmable logic to the system interconnect via one of a plurality of access modes supported by the system interconnect.
摘要翻译：公开了接口逻辑。接口逻辑包括第一地址解码器，耦合到地址解码器的第一模式逻辑组和耦合到第一组模式逻辑的第一选择器。接口逻辑适用于通过系统互连支持的多种访问模式之一将可编程逻辑连接到系统互连。

2. 发明授权

US06467009B1 Configurable processor system unit 有权
标题翻译：可配置的处理器系统单元
公开(公告)号：US06467009B1
公开(公告)日：2002-10-15
申请号：US09172918
申请日：1998-10-14
申请人： Steven Paul Winegarden , Bart Reynolds , Brian Fox , Jean-Didier Allegrucci , Sridhar Krishnamurthy , Danesh Tavana , Arye Ziklik , Andreas Papaliolios , Stanley S. Yang , Fung Fung Lee
发明人： Steven Paul Winegarden , Bart Reynolds , Brian Fox , Jean-Didier Allegrucci , Sridhar Krishnamurthy , Danesh Tavana , Arye Ziklik , Andreas Papaliolios , Stanley S. Yang , Fung Fung Lee
IPC分类号： G06F100
CPC分类号： G06F15/7867 , G06F13/4217
摘要： The configurable processor system includes a processor, an internal system bus, and a programmable logic all interconnected via the internal system bus, on a single integrated circuit.
摘要翻译：可配置处理器系统包括处理器，内部系统总线和经由内部系统总线在单个集成电路上互连的可编程逻辑。

3. 发明授权

US06910002B1 Method and apparatus for specifying addressability and bus connections in a logic design 有权
标题翻译：用于在逻辑设计中指定可寻址性和总线连接的方法和装置
公开(公告)号：US06910002B1
公开(公告)日：2005-06-21
申请号：US09649437
申请日：2000-08-23
申请人： Bart Reynolds , Cheng-I Chuang , Chukwuweta Chukwudebe , Sridhar Krishnamurthy , Damon McCormick , Tom Shui , Kai Zhu
发明人： Bart Reynolds , Cheng-I Chuang , Chukwuweta Chukwudebe , Sridhar Krishnamurthy , Damon McCormick , Tom Shui , Kai Zhu
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： In one embodiment, a method for specifying addressability in a memory-mapped device is disclosed. A data access primitive is used to model addressablity for the memory-mapped device. Addressability comprises an address matching function, a lane matching function and one or more bus connections. A first starting address for the memory-mapped device is specified. A first set of addressing matching function, lane matching function and one or more bus connections for the memory-mapped device is generated using the data access primitive and the first starting address.
摘要翻译：在一个实施例中，公开了一种用于指定存储器映射设备中的可寻址性的方法。数据访问原语用于建立内存映射设备的可通信性。可寻址性包括地址匹配功能，车道匹配功能和一个或多个总线连接。指定内存映射设备的第一个起始地址。使用数据访问原语和第一起始地址生成用于存储器映射设备的第一组寻址匹配功能，通道匹配功能和一个或多个总线连接。

4. 发明授权

US06661812B1 Bidirectional bus for use as an interconnect routing resource 有权
标题翻译：双向总线用作互连路由资源
公开(公告)号：US06661812B1
公开(公告)日：2003-12-09
申请号：US09543292
申请日：2000-04-05
申请人： Bart Reynolds , Sridhar Krishnamurthy
发明人： Bart Reynolds , Sridhar Krishnamurthy
IPC分类号： H04J302
CPC分类号： H03K19/17736
摘要： A bidirectional bus structure includes a first multiplexer path propagating signals in a first direction and a second multiplexer path propagating signals in a second direction. For one embodiment, the bus structure further includes a circuit for selectively combining the signals on the first and second paths and selectively propagating the signal on one of the first and second paths. For another embodiment, the bus structure further includes a logic gate for combining the signals on the first and second paths and a circuit for selectively propagating the signal on one of the first path, the second path, and an output signal of the logic gate. For both embodiments, the present invention allows multiple signals to use the bus without contention, thereby providing an extremely flexible interconnect routing resource. This bidirectional bus can selectively drive signals onto the general interconnect as well as onto a system bus in a configurable system on a chip.
摘要翻译：双向总线结构包括在第一方向传播信号的第一多路复用器路径和在第二方向传播信号的第二多路复用器路径。对于一个实施例，总线结构还包括用于选择性地组合第一和第二路径上的信号并选择性地传播第一和第二路径之一上的信号的电路。对于另一个实施例，总线结构还包括用于组合第一和第二路径上的信号的逻辑门和用于选择性地在第一路径，第二路径和逻辑门的输出信号之一上传播信号的电路。对于这两个实施例，本发明允许多个信号在没有争用的情况下使用总线，从而提供非常灵活的互连路由资源。该双向总线可以选择性地将信号驱动到一般互连以及芯片上的可配置系统中的系统总线上。

5. 发明授权

US06658547B1 Method and apparatus for specifying address offsets and alignment in logic design 有权
标题翻译：用于在逻辑设计中指定地址偏移和对齐的方法和装置
公开(公告)号：US06658547B1
公开(公告)日：2003-12-02
申请号：US09645865
申请日：2000-08-23
申请人： Bart Reynolds , Sridhar Krishnamurthy , Damon McCormick , Kai Zhu
发明人： Bart Reynolds , Sridhar Krishnamurthy , Damon McCormick , Kai Zhu
IPC分类号： G06F1200
CPC分类号： G06F17/5045 , G06F12/0661
摘要： A method for asserting an address alignment of an address for a memory-mapped device in a logic design is disclosed. An align primitive comprising an alignment size port, an input address port and an output address port is used. The alignment size port has data indicating a desired address boundary. The input address port is used for an address to be verified against the desired address boundary. The output address port is used to provide an address that is on the desired address boundary. The address to be verified against the desired address boundary is provided at the output address port when that address meets the desired address boundary. Another method for specifying an offset address for a memory-mapped device in a logic design is disclosed. An offset primitive is used to assert an address for the memory-mapped device. The offset primitive comprises an incoming address port, an outgoing address port and an offset value port. The offset value port has a data value indicating a desired address offset. The incoming address port has a base address to calculate an offset address. The outgoing address port has the offset address. The offset value is a multiple of a transaction size at the memory-mapped device.
摘要翻译：公开了一种在逻辑设计中用于断言存储器映射设备的地址的地址对齐的方法。使用包括对齐尺寸端口，输入地址端口和输出地址端口的对齐图元。对齐尺寸端口具有指示所需地址边界的数据。输入地址端口用于要针对所需地址边界进行验证的地址。输出地址端口用于提供所需地址边界上的地址。当该地址满足期望的地址边界时，在输出地址端口处提供要针对所需地址边界进行验证的地址。公开了用于在逻辑设计中指定存储器映射器件的偏移地址的另一种方法。偏移原语用于断言存储器映射设备的地址。偏移原语包括输入地址端口，输出地址端口和偏移值端口。偏移值端口具有指示期望的地址偏移的数据值。输入地址端口有一个基地址来计算一个偏移地址。出站地址端口具有偏移地址。偏移值是存储器映射设备的事务大小的倍数。

6. 发明授权

US09042431B1 Wide band deterministic interface 有权
标题翻译：宽带确定性接口
公开(公告)号：US09042431B1
公开(公告)日：2015-05-26
申请号：US12391712
申请日：2009-02-24
申请人： Venkat Yadavalli , Sridhar Krishnamurthy , Gerardo Orlando , David Richardson King , Ken Clauss , Mark Krumpoch , Peter Markou
发明人： Venkat Yadavalli , Sridhar Krishnamurthy , Gerardo Orlando , David Richardson King , Ken Clauss , Mark Krumpoch , Peter Markou
IPC分类号： H04B1/38 , H04L1/24 , H04L1/00
CPC分类号： H04L1/243 , H04L1/0001
摘要： A transceiver with non-deterministic delay characteristics is analyzed and adjusted to provide a transceiver with deterministic delay characteristics. The transceiver may be implemented with a variety of device types to support high bandwidth operation over a wide range of frequencies. Deterministic behavior allows use of the transceiver in source synchronous interfaces. The transceiver may also be dynamically analyzed and adjusted during operation as operation frequency changes.
摘要翻译：分析和调整具有非确定性延迟特性的收发器，以提供具有确定性延迟特性的收发器。收发器可以用各种设备类型来实现，以支持在宽范围的频率上的高带宽操作。确定性行为允许在源同步接口中使用收发器。收发器在操作频率变化时也可以动态分析和调整。

7. 发明授权

US07926016B1 Timing driven logic block configuration 有权
标题翻译：定时驱动逻辑块配置
公开(公告)号：US07926016B1
公开(公告)日：2011-04-12
申请号：US12344155
申请日：2008-12-24
申请人： Priya Sundararajan , Sridhar Krishnamurthy
发明人： Priya Sundararajan , Sridhar Krishnamurthy
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A method of configuring a logic block of a programmable logic device (PLD) during physical implementation of a circuit design, wherein ports of the logic block are selectively registered, can include identifying the logic block of the PLD, wherein the logic block is located on a critical path. For each of a plurality of selectively registerable portions of the logic block, the method can include computing input slacks and output slacks based upon potential register usage within the logic block. The method further can include determining register usage for the logic block by maximizing a function which depends upon a measure of worst case slack for pipeline stages.
摘要翻译：一种在电路设计的物理实现期间配置可编程逻辑器件（PLD）的逻辑块的方法，其中逻辑块的端口被选择性地注册，可以包括识别PLD的逻辑块，其中逻辑块位于一个关键的路径。对于逻辑块的多个可选择地可注册部分中的每一个，该方法可以包括基于逻辑块内的潜在寄存器使用计算输入宽度和输出宽度。该方法还可以包括通过使取决于流水线级的最差情况松弛的度量的函数最大化来确定逻辑块的寄存器使用。

8. 发明授权

US07610573B1 Implementation of alternate solutions in technology mapping and placement 有权
标题翻译：在技术测绘和放置中实施替代解决方案
公开(公告)号：US07610573B1
公开(公告)日：2009-10-27
申请号：US11881307
申请日：2007-07-26
申请人： Vi Chi Chan , Tetse Jang , Sridhar Krishnamurthy , Kevin Chung
发明人： Vi Chi Chan , Tetse Jang , Sridhar Krishnamurthy , Kevin Chung
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F2217/08
摘要： A computer-implemented method of implementing a circuit design within a target integrated circuit (IC) can include, during technology mapping of the circuit design, determining a plurality of implementations of at least one sub-circuit of the circuit design and placing the circuit design on the target IC using a primary implementation of the plurality of implementations of the sub-circuit. The primary implementation of the sub-circuit can be selectively replaced with an alternate implementation of the sub-circuit selected from the plurality of implementations of the sub-circuit. The placed circuit design, including either the primary implementation or the alternate implementation of the sub-circuit, can be output.
摘要翻译：在目标集成电路（IC）中实现电路设计的计算机实现的方法可以包括在电路设计的技术映射期间，确定电路设计的至少一个子电路的多个实现并且将电路设计在目标IC上使用子电路的多个实现的主要实现。子电路的主要实现可以被选择性地替换为从子电路的多个实现中选择的子电路的替代实现。可以输出放置的电路设计，包括子电路的主要实现或替代实现。

9. 发明授权

US07058919B1 Methods of generating test designs for testing specific routing resources in programmable logic devices 失效
标题翻译：生成用于测试可编程逻辑器件中特定路由资源的测试设计的方法
公开(公告)号：US07058919B1
公开(公告)日：2006-06-06
申请号：US10696357
申请日：2003-10-28
申请人： Jay T. Young , Sridhar Krishnamurthy , Jeffrey V. Lindholm , Ian L. McEwen
发明人： Jay T. Young , Sridhar Krishnamurthy , Jeffrey V. Lindholm , Ian L. McEwen
IPC分类号： G06F17/50
CPC分类号： G01R31/318516 , G01R31/31704
摘要： Methods of directly targeting specified routing resources in a PLD, e.g., routing resources that need to be tested. Test designs are produced that implement observable nets using the targeted routing resources. A PLD router is used to route from a target routing resource backwards through the routing fabric of the PLD to the source of an observable net. The net is identified based on the source, and loads of the net are identified as router load targets. The router is then used to route from the target routing resource forwards to one of the loads on the net. This process can be repeated for a list of target routing resources to provide a test design that tests as many of the targeted routing resources as possible. Additional test designs can be created to test remaining target routing resources. In other embodiments, the router routes first forwards, then backwards.
摘要翻译：直接针对PLD中的指定路由资源的方法，例如路由需要测试的资源。使用目标路由资源实现可观察网络的测试设计。 PLD路由器用于从目标路由资源向后路由PLD的路由结构到可观察网络的源。网络基于源标识，网络的负载被标识为路由器负载目标。路由器然后用于从目标路由资源转发到网络上的一个负载。可以针对目标路由资源列表重复此过程，以提供尽可能多的目标路由资源的测试设计。可以创建其他测试设计来测试剩余的目标路由资源。在其他实施例中，路由器首先向前路由，然后向后路由。

10. 发明授权

US06574655B1 Associative management of multimedia assets and associated resources using multi-domain agent-based communication between heterogeneous peers 有权
标题翻译：多媒体资产和相关资源的联合管理使用异构同层之间的多域代理进行通信
公开(公告)号：US06574655B1
公开(公告)日：2003-06-03
申请号：US09342490
申请日：1999-06-29
申请人： Scott A. Libert , Robert J. Woolridge , Baochun Jin , Alex C. Tran , P. Murugavel , Mark S. Hillebrandt , Suhas Joshi , Sridhar Krishnamurthy , Rajagopal Govindakrishnan
发明人： Scott A. Libert , Robert J. Woolridge , Baochun Jin , Alex C. Tran , P. Murugavel , Mark S. Hillebrandt , Suhas Joshi , Sridhar Krishnamurthy , Rajagopal Govindakrishnan
IPC分类号： G06F1516
CPC分类号： H04L67/104 , H04L29/06027 , H04L63/10 , H04L67/2819 , H04L67/2823 , H04L67/2828 , H04L69/24 , H04L69/329 , H04L2463/101 , Y10S707/99945
摘要： Associative management of distributed multimedia assets and associated resources using multi-domain agent-based communication between heterogeneous peers is achieved using an Asset/Resource Management (ARM) platform architecture that has an ARM Framework that is used by Asset Management Agents. The ARM Framework includes an ARM Infrastructure which is a system of protocols and libraries from which communities of agents that are grouped in logical Agent Domains are built. The agents communicate via the KQML language embedded within TCP/IP messages, advertise their capabilities and cooperate together to perform meaningful work. An XML-based language is used to embed “content” within the KQML language, providing a self-describing data representation using various character sets. The ARM Framework includes system agents including in each Agent Domain a Resolver for keeping track of asset logical locations, an Agent Name Server (ANS) for keeping track of security access to the assets, and the “Yellow Pages” containing the Advertised System Knowledge (ASK) agent for keeping track of the capabilities of the Asset Management Agents.
摘要翻译：使用具有由资产管理代理使用的ARM框架的资产/资源管理（ARM）平台架构实现了使用异构对等体之间的基于多域代理的通信的分布式多媒体资产和相关资源的关联管理。 ARM框架包括一个ARM基础架构，它是一个协议和库的系统，构建了分组在逻辑代理域中的代理团体。代理人通过嵌入在TCP / IP消息中的KQML语言进行通信，宣传他们的能力，并且携手合作，进行有意义的工作。使用基于XML的语言将“内容”嵌入到KQML语言中，使用各种字符集提供自描述数据表示。 ARM框架包括系统代理，包括每个代理域中的一个用于跟踪资产逻辑位置的解析器，用于跟踪资产安全访问的代理名称服务器（ANS）和包含广告系统知识的“黄页”（ ASK）代理，用于跟踪资产管理代理的能力。

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