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1. 发明授权

US06910002B1 Method and apparatus for specifying addressability and bus connections in a logic design 有权
标题翻译：用于在逻辑设计中指定可寻址性和总线连接的方法和装置
公开(公告)号：US06910002B1
公开(公告)日：2005-06-21
申请号：US09649437
申请日：2000-08-23
申请人： Bart Reynolds , Cheng-I Chuang , Chukwuweta Chukwudebe , Sridhar Krishnamurthy , Damon McCormick , Tom Shui , Kai Zhu
发明人： Bart Reynolds , Cheng-I Chuang , Chukwuweta Chukwudebe , Sridhar Krishnamurthy , Damon McCormick , Tom Shui , Kai Zhu
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： In one embodiment, a method for specifying addressability in a memory-mapped device is disclosed. A data access primitive is used to model addressablity for the memory-mapped device. Addressability comprises an address matching function, a lane matching function and one or more bus connections. A first starting address for the memory-mapped device is specified. A first set of addressing matching function, lane matching function and one or more bus connections for the memory-mapped device is generated using the data access primitive and the first starting address.
摘要翻译：在一个实施例中，公开了一种用于指定存储器映射设备中的可寻址性的方法。数据访问原语用于建立内存映射设备的可通信性。可寻址性包括地址匹配功能，车道匹配功能和一个或多个总线连接。指定内存映射设备的第一个起始地址。使用数据访问原语和第一起始地址生成用于存储器映射设备的第一组寻址匹配功能，通道匹配功能和一个或多个总线连接。

2. 发明授权

US06658547B1 Method and apparatus for specifying address offsets and alignment in logic design 有权
标题翻译：用于在逻辑设计中指定地址偏移和对齐的方法和装置
公开(公告)号：US06658547B1
公开(公告)日：2003-12-02
申请号：US09645865
申请日：2000-08-23
申请人： Bart Reynolds , Sridhar Krishnamurthy , Damon McCormick , Kai Zhu
发明人： Bart Reynolds , Sridhar Krishnamurthy , Damon McCormick , Kai Zhu
IPC分类号： G06F1200
CPC分类号： G06F17/5045 , G06F12/0661
摘要： A method for asserting an address alignment of an address for a memory-mapped device in a logic design is disclosed. An align primitive comprising an alignment size port, an input address port and an output address port is used. The alignment size port has data indicating a desired address boundary. The input address port is used for an address to be verified against the desired address boundary. The output address port is used to provide an address that is on the desired address boundary. The address to be verified against the desired address boundary is provided at the output address port when that address meets the desired address boundary. Another method for specifying an offset address for a memory-mapped device in a logic design is disclosed. An offset primitive is used to assert an address for the memory-mapped device. The offset primitive comprises an incoming address port, an outgoing address port and an offset value port. The offset value port has a data value indicating a desired address offset. The incoming address port has a base address to calculate an offset address. The outgoing address port has the offset address. The offset value is a multiple of a transaction size at the memory-mapped device.
摘要翻译：公开了一种在逻辑设计中用于断言存储器映射设备的地址的地址对齐的方法。使用包括对齐尺寸端口，输入地址端口和输出地址端口的对齐图元。对齐尺寸端口具有指示所需地址边界的数据。输入地址端口用于要针对所需地址边界进行验证的地址。输出地址端口用于提供所需地址边界上的地址。当该地址满足期望的地址边界时，在输出地址端口处提供要针对所需地址边界进行验证的地址。公开了用于在逻辑设计中指定存储器映射器件的偏移地址的另一种方法。偏移原语用于断言存储器映射设备的地址。偏移原语包括输入地址端口，输出地址端口和偏移值端口。偏移值端口具有指示期望的地址偏移的数据值。输入地址端口有一个基地址来计算一个偏移地址。出站地址端口具有偏移地址。偏移值是存储器映射设备的事务大小的倍数。

3. 发明授权

US06661812B1 Bidirectional bus for use as an interconnect routing resource 有权
标题翻译：双向总线用作互连路由资源
公开(公告)号：US06661812B1
公开(公告)日：2003-12-09
申请号：US09543292
申请日：2000-04-05
申请人： Bart Reynolds , Sridhar Krishnamurthy
发明人： Bart Reynolds , Sridhar Krishnamurthy
IPC分类号： H04J302
CPC分类号： H03K19/17736
摘要： A bidirectional bus structure includes a first multiplexer path propagating signals in a first direction and a second multiplexer path propagating signals in a second direction. For one embodiment, the bus structure further includes a circuit for selectively combining the signals on the first and second paths and selectively propagating the signal on one of the first and second paths. For another embodiment, the bus structure further includes a logic gate for combining the signals on the first and second paths and a circuit for selectively propagating the signal on one of the first path, the second path, and an output signal of the logic gate. For both embodiments, the present invention allows multiple signals to use the bus without contention, thereby providing an extremely flexible interconnect routing resource. This bidirectional bus can selectively drive signals onto the general interconnect as well as onto a system bus in a configurable system on a chip.
摘要翻译：双向总线结构包括在第一方向传播信号的第一多路复用器路径和在第二方向传播信号的第二多路复用器路径。对于一个实施例，总线结构还包括用于选择性地组合第一和第二路径上的信号并选择性地传播第一和第二路径之一上的信号的电路。对于另一个实施例，总线结构还包括用于组合第一和第二路径上的信号的逻辑门和用于选择性地在第一路径，第二路径和逻辑门的输出信号之一上传播信号的电路。对于这两个实施例，本发明允许多个信号在没有争用的情况下使用总线，从而提供非常灵活的互连路由资源。该双向总线可以选择性地将信号驱动到一般互连以及芯片上的可配置系统中的系统总线上。

4. 发明授权

US06467009B1 Configurable processor system unit 有权
标题翻译：可配置的处理器系统单元
公开(公告)号：US06467009B1
公开(公告)日：2002-10-15
申请号：US09172918
申请日：1998-10-14
申请人： Steven Paul Winegarden , Bart Reynolds , Brian Fox , Jean-Didier Allegrucci , Sridhar Krishnamurthy , Danesh Tavana , Arye Ziklik , Andreas Papaliolios , Stanley S. Yang , Fung Fung Lee
发明人： Steven Paul Winegarden , Bart Reynolds , Brian Fox , Jean-Didier Allegrucci , Sridhar Krishnamurthy , Danesh Tavana , Arye Ziklik , Andreas Papaliolios , Stanley S. Yang , Fung Fung Lee
IPC分类号： G06F100
CPC分类号： G06F15/7867 , G06F13/4217
摘要： The configurable processor system includes a processor, an internal system bus, and a programmable logic all interconnected via the internal system bus, on a single integrated circuit.
摘要翻译：可配置处理器系统包括处理器，内部系统总线和经由内部系统总线在单个集成电路上互连的可编程逻辑。

5. 发明授权

US06754760B1 Programmable interface for a configurable system bus 有权
标题翻译：可配置系统总线的可编程接口
公开(公告)号：US06754760B1
公开(公告)日：2004-06-22
申请号：US09644223
申请日：2000-08-21
申请人： Wilson Yee , Brian Fox , Sridhar Krishnamurthy , Bart Reynolds , Steven Winegarden
发明人： Wilson Yee , Brian Fox , Sridhar Krishnamurthy , Bart Reynolds , Steven Winegarden
IPC分类号： G06F1340
CPC分类号： G06F13/4018
摘要： Interface logic is disclosed. The interface logic comprises a first address decoder, a first set of mode logic coupled to the address decoder and a first selector coupled to the first set of mode logic. The interface logic is adaptable to connect the programmable logic to the system interconnect via one of a plurality of access modes supported by the system interconnect.
摘要翻译：公开了接口逻辑。接口逻辑包括第一地址解码器，耦合到地址解码器的第一模式逻辑组和耦合到第一组模式逻辑的第一选择器。接口逻辑适用于通过系统互连支持的多种访问模式之一将可编程逻辑连接到系统互连。

6. 发明授权

US5448493A Structure and method for manually controlling automatic configuration in an integrated circuit logic block array 失效
标题翻译：用于手动控制集成电路逻辑块阵列中的自动配置的结构和方法
公开(公告)号：US5448493A
公开(公告)日：1995-09-05
申请号：US456010
申请日：1989-12-20
申请人： Todd J. Topolewski , Christine M. Weir , Bart Reynolds , Julia M. Smuts , Pardner Wynn , Stephen M. Trimberger
发明人： Todd J. Topolewski , Christine M. Weir , Bart Reynolds , Julia M. Smuts , Pardner Wynn , Stephen M. Trimberger
IPC分类号： G06F17/50 , G06F15/60
CPC分类号： G06F17/5072 , G06F17/5054
摘要： Highly integrated programmable arrays, in which a logic array integrated circuit chip is divided into configurable logic blocks interconnected by configurable interconnect lines, have been programmed by automatic means and methods. The present invention provides for allowing a user to manually specify the partitioning of a logic design, and to allow a user to retain portions of a previously partitioned, placed, and routed design when making revisions. To allow for manual control of partitioning, a library of symbols includes a partitioning symbol that specifies which primitive logic functions can be grouped. The user specifies which ports of primitive logic functions will correspond with ports on the logic block symbol. The present invention also allows for partitioning parts of a design before combining the parts.
摘要翻译：高度集成的可编程阵列（其中将逻辑阵列集成电路芯片划分为可配置互连线互连的可配置逻辑块）已经通过自动化手段和方法编程。本发明提供允许用户手动指定逻辑设计的划分，并且允许用户在进行修改时保留先前分割的，放置的和路由的设计的部分。为了允许对分区进行手动控制，符号库包括一个分配符号，用于指定哪些原始逻辑功能可以分组。用户指定原始逻辑功能的哪些端口将对应于逻辑块符号上的端口。本发明还允许在组合部件之前对设计的部分进行分区。

7. 发明授权

US07451425B1 Determining controlling pins for a tile module of a programmable logic device 有权
标题翻译：确定可编程逻辑器件的瓦片模块的控制引脚
公开(公告)号：US07451425B1
公开(公告)日：2008-11-11
申请号：US11502922
申请日：2006-08-11
申请人： Bart Reynolds , Keith R. Bean , Daniel P. Kirkwood , James F. Barei , Benjamin D. Ralston
发明人： Bart Reynolds , Keith R. Bean , Daniel P. Kirkwood , James F. Barei , Benjamin D. Ralston
IPC分类号： G06F17/50 , H03K17/693
CPC分类号： G06F17/5054
摘要： A processor-implemented method is provided for determining controlling pins of a programmable logic device (PLD) design. A netlist that describes the PLD design and an identification of a tile module are input. Characterization data is input for a sub-module of the tile module that specifies a select input pin controlling a programmable function of the sub-module, which is either a multiplexer or a logic site. Characterization data is input for a configuration memory cell of the tile module that specifies a data output pin of the configuration memory cell. The controlling pin is determined for each select input pin of each instance of the sub-module of the tile module. The controlling pin of a select input pin is the data output pin of an instance of a configuration memory cell of the tile module. A specification is output of the select input pin and corresponding controlling pin.
摘要翻译：提供了一种用于确定可编程逻辑器件（PLD）设计的控制引脚的处理器实现的方法。输入描述PLD设计的网表和瓦片模块的标识。为瓦片模块的子模块输入表征数据，该模块指定控制作为多路复用器或逻辑站点的子模块的可编程功能的选择输入引脚。输入表示配置存储单元的数据输出引脚的瓦片模块的配置存储单元的特征数据。为瓦片模块的子模块的每个实例的每个选择输入引脚确定控制引脚。选择输入引脚的控制引脚是瓦片模块的配置存储单元的实例的数据输出引脚。选择输入引脚和相应的控制引脚输出规格。

8. 发明授权

US07451424B1 Determining programmable connections through a switchbox of a programmable logic device 有权
标题翻译：通过可编程逻辑器件的开关盒确定可编程连接
公开(公告)号：US07451424B1
公开(公告)日：2008-11-11
申请号：US11502911
申请日：2006-08-11
申请人： Bart Reynolds , Keith R. Bean , Daniel P. Kirkwood , James F. Barei , Benjamin D. Ralston
发明人： Bart Reynolds , Keith R. Bean , Daniel P. Kirkwood , James F. Barei , Benjamin D. Ralston
IPC分类号： G06F17/50 , H03K17/693
CPC分类号： G06F17/5054
摘要： A processor-implemented method is provided for determining programmable connections through a switchbox module of a programmable logic device (PLD) design. A netlist that describes the PLD design and an identification of the switchbox module are input. Characterization data is input for each multiplexer module of the switchbox module. The characterization data specifies input pins and at least one output pin of the multiplexer module. The multiplexer module programmably connects each output pin to one of the input pins. Pins of the switchbox module are determined through which the programmable connections are provided via an instance of a multiplexer module of the switchbox module. Each pair of the pins of the switchbox module is determined that are functionally connected via at least one instance of the at least one multiplexer module, with each pair specifying a programmable connection. A specification of the programmable connections is output.
摘要翻译：提供了一种处理器实现的方法，用于通过可编程逻辑器件（PLD）设计的开关盒模块来确定可编程连接。输入描述PLD设计和识别开关盒模块的网表。为开关盒模块的每个复用器模块输入特征数据。表征数据指定多路复用器模块的输入引脚和至少一个输出引脚。多路复用器模块可编程地将每个输出引脚连接到其中一个输入引脚。确定开关盒模块的引脚，通过该引脚通过开关盒模块的多路复用器模块的实例提供可编程连接。确定开关盒模块的每对引脚经由至少一个多路复用器模块的至少一个实例功能连接，每对指定可编程连接。输出可编程连接的规格。

9. 发明授权

US07451423B1 Determining indices of configuration memory cell modules of a programmable logic device 有权
标题翻译：确定可编程逻辑器件的配置存储单元模块的索引
公开(公告)号：US07451423B1
公开(公告)日：2008-11-11
申请号：US11502909
申请日：2006-08-11
申请人： Bart Reynolds , Keith R. Bean , Daniel P. Kirkwood , James F. Barei , Benjamin D. Ralston
发明人： Bart Reynolds , Keith R. Bean , Daniel P. Kirkwood , James F. Barei , Benjamin D. Ralston
IPC分类号： G06F17/50 , H03K17/693
CPC分类号： G06F17/5054 , H03K19/1737
摘要： A processor-implemented method is provided for determining first and second indices of cell instances of a configuration memory cell of a tile module of a programmable logic device (PLD) design. A netlist is input that describes the PLD design and includes the cell instances of the configuration memory cell. An identification of the tile module is input. Characterization data is input for each configuration memory cell specifying address and data input pins. Characterization data is input for each configuration control module specifying a first ordered set of address output pins and a second ordered set of data output pins. For each of the cell instances, the first index of an address output pin in the first ordered set and the second index of a data output pin in the second ordered set are determined and a specification is output of the cell instance and the first and second indices.
摘要翻译：提供了一种处理器实现的方法，用于确定可编程逻辑器件（PLD）设计的瓦片模块的配置存储器单元的第一和第二索引的小区实例。网表是描述PLD设计的输入，包括配置存储单元的单元实例。输入瓦片模块的标识。为每个配置存储单元指定地址和数据输入引脚输入特征数据。为每个配置控制模块输入表征数据，指定地址输出引脚的第一有序集合和第二有序数据输出引脚集合。对于每个小区实例，确定第一有序集合中的地址输出引脚的第一索引和第二有序集合中的数据输出引脚的第二索引，并且输出小区实例的规范，并且第一和第二指数。

10. 发明授权

US06704850B1 Method and apparatus for determining the width of a memory subsystem 有权
标题翻译：用于确定存储器子系统的宽度的方法和装置
公开(公告)号：US06704850B1
公开(公告)日：2004-03-09
申请号：US09648406
申请日：2000-08-23
申请人： Bart Reynolds
发明人： Bart Reynolds
IPC分类号： G06F1200
CPC分类号： G06F12/0684
摘要： A method and apparatus for determining a width of an external memory is described. The method comprises reading a data from memory, and if the data matches an expected data key, determining the width of the memory.
摘要翻译：描述了一种用于确定外部存储器的宽度的方法和装置。该方法包括从存储器读取数据，并且如果数据与预期数据密钥相匹配，则确定存储器的宽度。

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