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1. 发明授权

US08667435B1 Function symmetry-based optimization for physical synthesis of programmable integrated circuits 有权
标题翻译：基于功能对称的可编程集成电路物理综合优化
公开(公告)号：US08667435B1
公开(公告)日：2014-03-04
申请号：US12874993
申请日：2010-09-02
申请人： Tetse Jang , Vi Chi Chan , Kevin Chung
发明人： Tetse Jang , Vi Chi Chan , Kevin Chung
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A computer-implemented method of technology mapping a circuit design for implementation within a programmable logic device can include determining a plurality of cut sets for the circuit design, wherein each cut set includes a plurality of cuts. The method can include evaluating each cut set according to a cost function that depends, at least in part, upon a measure of inter-cut symmetry and selecting a cut set according to the cost function. Each cut of the selected cut set can represent an instantiation of at least one logic component within the programmable logic device. The circuit design specifying the selected cut set can be output.
摘要翻译：计算机实现的映射用于在可编程逻辑器件中实现的电路设计的技术的方法可以包括确定用于电路设计的多个切割组，其中每个切割组包括多个切割。该方法可以包括根据成本函数评估每个切割组，所述成本函数至少部分地取决于切割对称性的度量并且根据成本函数选择切割组。所选切割组的每个切割可以表示可编程逻辑器件内的至少一个逻辑部件的实例。可以输出指定所选切割组的电路设计。

2. 发明授权

US07904842B1 Modifying a logic implementation by swapping inputs of fanout-free cones 有权
标题翻译：通过交换无扇出锥体的输入来修改逻辑实现
公开(公告)号：US07904842B1
公开(公告)日：2011-03-08
申请号：US12006985
申请日：2008-01-08
申请人： Tetse Jang , Vi Chi Chan , Kevin Chung
发明人： Tetse Jang , Vi Chi Chan , Kevin Chung
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5054
摘要： An implementation of a logic description is improved. The implementation has two signals coupled to two inputs of a fanout-free cone. A swap function is determined of the inputs of the fanout-free cone. The swap function indicates whether there is a difference at an output of the fanout free cone between the fanout-free cone with and without swapping the two signals between the two inputs of the fanout-free cone. A do-not-care function of the inputs of the fanout-free cone is determined for the logic description. The do-not-care function indicates that a modification of the output of the fanout-free cone is not observable at the primary outputs of the logic description. A modified implementation of the logic description is output in response to the do-not-care function covering the swap function. The modified implementation of the logic description has the two signals swapped between the two inputs of the fanout-free cone.
摘要翻译：改进了逻辑描述的实现。该实现具有耦合到无扇形锥的两个输入的两个信号。确定无扇形锥的输入的交换功能。交换功能指示无风扇的锥形输出之间是否存在差异，在不带扇出的锥的两个输入之间交换两个信号。逻辑描述确定无扇形锥的输入的无关紧要功能。不关心功能表示在逻辑描述的主要输出处不能观察到无扇出锥的输出的修改。响应于覆盖交换功能的不关心功能输出逻辑描述的修改实现。逻辑描述的修改实现具有在无扇出锥的两个输入之间交换的两个信号。

3. 发明授权

US08201125B1 Network mapping using edges as a parameter 有权
标题翻译：网络映射使用边缘作为参数
公开(公告)号：US08201125B1
公开(公告)日：2012-06-12
申请号：US12366452
申请日：2009-02-05
申请人： Tetse Jang , Vi Chi Chan , Kevin Chung
发明人： Tetse Jang , Vi Chi Chan , Kevin Chung
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5054
摘要： A method and apparatus for circuit design synthesis are described. An edge flow cost function is implemented to obtain edge flow costs for nodes of a network. A subject graph of the network is then mapped using the edge flow costs.
摘要翻译：描述了用于电路设计合成的方法和装置。实现边缘流成本函数以获得网络节点的边缘流成本。然后使用边缘流量成本映射网络的主题图。

4. 发明授权

US07814452B1 Function symmetry-based optimization for physical synthesis of programmable integrated circuits 有权
标题翻译：基于功能对称的可编程集成电路物理综合优化
公开(公告)号：US07814452B1
公开(公告)日：2010-10-12
申请号：US11981916
申请日：2007-11-01
申请人： Tetse Jang , Vi Chi Chan , Kevin Chung
发明人： Tetse Jang , Vi Chi Chan , Kevin Chung
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A computer-implemented method of technology mapping a circuit design for implementation within a programmable logic device can include determining a plurality of cut sets for the circuit design, wherein each cut set includes a plurality of cuts. The method can include evaluating each cut set according to a cost function that depends, at least in part, upon a measure of inter-cut symmetry and selecting a cut set according to the cost function. Each cut of the selected cut set can represent an instantiation of at least one logic component within the programmable logic device. The circuit design specifying the selected cut set can be output.
摘要翻译：计算机实现的映射用于在可编程逻辑器件中实现的电路设计的技术的方法可以包括确定用于电路设计的多个切割组，其中每个切割组包括多个切割。该方法可以包括根据成本函数评估每个切割组，所述成本函数至少部分地取决于切割对称性的度量并且根据成本函数选择切割组。所选切割组的每个切割可以表示可编程逻辑器件内的至少一个逻辑部件的实例。可以输出指定所选切割组的电路设计。

5. 发明授权

US07725855B1 Symmetry-based optimization for the physical synthesis of programmable logic devices 有权
标题翻译：用于可编程逻辑器件的物理合成的基于对称的优化
公开(公告)号：US07725855B1
公开(公告)日：2010-05-25
申请号：US11981910
申请日：2007-11-01
申请人： Tetse Jang , Kevin Chung
发明人： Tetse Jang , Kevin Chung
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/5054
摘要： A computer-implemented method of improving timing of a circuit design for a programmable logic device can include identifying a timing critical wire of the circuit design and determining a fanout free cone coupled to a plurality of leaf nodes, wherein the critical wire links a critical leaf node of the plurality of leaf nodes with the fanout free cone. At least one leaf node set can be selected, wherein the leaf node set includes a plurality of symmetric leaf nodes including the critical leaf node and at least one non-critical leaf node. At least two leaf nodes of a leaf node set can be swapped in the circuit design. The circuit design can be output.
摘要翻译：改进可编程逻辑器件的电路设计时序的计算机实现的方法可以包括识别电路设计的定时关键线，以及确定耦合到多个叶节点的无扇形扇形，其中所述关键线连接关键叶多个叶节点的节点具有扇出自由锥。可以选择至少一个叶节点集合，其中叶节点集合包括多个对称叶节点，包括关键叶节点和至少一个非关键叶节点。叶节点集的至少两个叶节点可以在电路设计中交换。可以输出电路设计。

6. 发明授权

US08145923B2 Circuit for and method of minimizing power consumption in an integrated circuit device 有权
标题翻译：集成电路器件中功耗最小化的电路和方法
公开(公告)号：US08145923B2
公开(公告)日：2012-03-27
申请号：US12034361
申请日：2008-02-20
申请人： Shankar Lakkapragada , Scott Te-Sheng Lien , Tetse Jang , Jesse H. Jenkins, IV , Mark Men Bon Ng
发明人： Shankar Lakkapragada , Scott Te-Sheng Lien , Tetse Jang , Jesse H. Jenkins, IV , Mark Men Bon Ng
IPC分类号： G06F1/26
CPC分类号： H03K19/0016 , H03K19/17704 , H03K19/17784
摘要： A method of minimizing power consumption in an integrated device is disclosed. The method comprises providing a plurality of circuit blocks having circuits for performing logic functions, wherein each circuit block consumes power in a static state; coupling one of a plurality of operating voltages to each circuit block of the plurality of circuit blocks; enabling a reduction of power consumed by a first set of circuit blocks by way of a first power reduction signal; and enabling a reduction of power consumed by a second set of circuit blocks by way of a second power reduction signal. A circuit for minimizing power consumption in a device is also disclosed.
摘要翻译：公开了一种使集成设备中的功耗最小化的方法。该方法包括提供具有用于执行逻辑功能的电路的多个电路块，其中每个电路块以静态消耗功率; 将多个工作电压中的一个耦合到所述多个电路块中的每个电路块; 能够通过第一功率降低信号来减少由第一组电路块消耗的功率; 并且能够通过第二功率降低信号来减少由第二组电路块消耗的功率。还公开了一种用于最小化设备中的功耗的电路。

7. 发明授权

US07620929B1 Programmable logic device having a programmable selector circuit 有权
标题翻译：具有可编程选择电路的可编程逻辑器件
公开(公告)号：US07620929B1
公开(公告)日：2009-11-17
申请号：US12020712
申请日：2008-01-28
申请人： Tetse Jang , Soren T. Soe , Scott Te-Sheng Lien
发明人： Tetse Jang , Soren T. Soe , Scott Te-Sheng Lien
IPC分类号： G06F17/50
CPC分类号： H03K19/17776 , H03K19/17736 , H03K19/17748
摘要： A PLD is configurable to efficiently implement a wide variety of user functions. The PLD includes a programmable interconnect circuit, programmable logic circuits, one-bit registers, selector circuits, and input/output blocks. The programmable interconnect circuit is configurable to connect the signal lines of its output ports to the signal lines of its input ports. The programmable logic circuits are configurable to implement a programmable function generating one-bit signal values from a respective output port of the programmable interconnect circuit. The one-bit registers store a respective one of these one-bit signal values. The programmable selector circuits are each coupled to output ports of a plurality of the one-bit registers, with each of these one-bit registers coupled to a respective one of the programmable logic circuits. The programmable input/output blocks are each coupled to an output port of a respective programmable selector circuit and to a respective input port of the programmable interconnect circuit.
摘要翻译： PLD可配置为有效地实现各种用户功能。 PLD包括可编程互连电路，可编程逻辑电路，一位寄存器，选择器电路和输入/输出块。可编程互连电路可配置为将其输出端口的信号线连接到其输入端口的信号线。可编程逻辑电路可配置为实现从可编程互连电路的相应输出端口产生一位信号值的可编程功能。一位寄存器存储这些一位信号值中的相应的一个。可编程选择器电路各自耦合到多个一位寄存器的输出端口，这些一位寄存器中的每一个耦合到可编程逻辑电路中的相应一个。可编程输入/输出块分别耦合到相应可编程选择器电路的输出端口和可编程互连电路的相应输入端口。

8. 发明授权

US06989690B1 Methods of implementing scalable routing matrices for programmable logic devices 有权
标题翻译：实现可编程逻辑器件的可扩展路由矩阵的方法
公开(公告)号：US06989690B1
公开(公告)日：2006-01-24
申请号：US10869589
申请日：2004-06-15
申请人： Tetse Jang , Scott Te-Sheng Lien
发明人： Tetse Jang , Scott Te-Sheng Lien
IPC分类号： H03K19/177
CPC分类号： H03K19/17736
摘要： Methods of implementing routing matrices for programmable logic devices (PLDs). Each method includes generating a seed matrix, a distribution matrix, adjustment values for the distribution matrix, and a routing matrix pattern. The seed matrix and distribution matrix are implemented according to a set of rules that define valid matrices. The routing matrix is then implemented by applying the routing matrix pattern to provide programmable interconnections between input and output terminals of the routing matrix. Each signal value in the routing matrix pattern corresponds to one of the input terminals, and each row of signal values in the routing matrix pattern corresponds to a set of the input terminals programmably coupled to a different one of the output terminals. By adding additional columns of sub-matrices to an existing distribution matrix, an existing routing matrix can also be expanded to accommodate a larger number of input signals.
摘要翻译：实现可编程逻辑器件（PLD）的路由矩阵的方法。每种方法包括生成种子矩阵，分布矩阵，分布矩阵的调整值以及路由矩阵模式。根据定义有效矩阵的一组规则来实现种子矩阵和分布矩阵。然后通过应用路由矩阵模式来实现路由矩阵，以在路由矩阵的输入和输出端之间提供可编程的互连。路由矩阵模式中的每个信号值对应于一个输入端，并且路由矩阵模式中的每一行信号值对应于可编程地耦合到不同的一个输出端的一组输入端。通过将附加的子矩阵列添加到现有的分布矩阵中，现有的路由矩阵也可以被扩展以适应更大数量的输入信号。

9. 发明授权

US08302041B1 Implementation flow for electronic circuit designs using choice networks 有权
标题翻译：使用选择网络的电子电路设计的实施流程
公开(公告)号：US08302041B1
公开(公告)日：2012-10-30
申请号：US12146313
申请日：2008-06-25
申请人： Vi Chi Chan , Tetse Jang , Kevin Chung , Taneem Ahmed , David Nguyen Van Mau , Mehrdad Parsa , Amit Singh
发明人： Vi Chi Chan , Tetse Jang , Kevin Chung , Taneem Ahmed , David Nguyen Van Mau , Mehrdad Parsa , Amit Singh
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5054
摘要： A computer-implemented method of implementing a circuit design that includes an initial network within a programmable logic device can include generating a first choice network from the circuit design according to a first synthesis technique and determining a placement for the first choice network. At least a second choice network can be generated from the first choice network according to a second synthesis technique. A placement for the second choice network can be determined. The placement for the first choice network can be compared with the placement for the second choice network. A placement and corresponding choice network can be selected according to the comparison, and output.
摘要翻译：实现包括可编程逻辑器件内的初始网络的电路设计的计算机实现的方法可以包括根据第一合成技术从电路设计产生第一选择网络并确定第一选择网络的布局。根据第二合成技术，可以从第一选择网络生成至少第二选择网络。可以确定用于第二选择网络的位置。可以将第一选择网络的位置与第二选择网络的位置进行比较。可以根据比较选择一个布局和相应的选择网络，并输出。

10. 发明授权

US07345508B1 Programmable logic device having a programmable selector circuit 失效
标题翻译：具有可编程选择电路的可编程逻辑器件
公开(公告)号：US07345508B1
公开(公告)日：2008-03-18
申请号：US11338361
申请日：2006-01-24
申请人： Tetse Jang , Soren T. Soe , Scott Te-Sheng Lien
发明人： Tetse Jang , Soren T. Soe , Scott Te-Sheng Lien
IPC分类号： H01L25/00 , H03K19/177
CPC分类号： H03K19/17776 , H03K19/17736 , H03K19/17748
摘要： A PLD is configurable to efficiently implement a wide variety of user functions. The PLD includes a programmable interconnect circuit, programmable logic circuits, one-bit registers, selector circuits, and input/output blocks. The programmable interconnect circuit is configurable to connect the signal lines of its output ports to the signal lines of its input ports. The programmable logic circuits are configurable to implement a programmable function generating one-bit signal values from a respective output port of the programmable interconnect circuit. The one-bit registers store a respective one of these one-bit signal values. The programmable selector circuits are each coupled to output ports of a plurality of the one-bit registers, with each of these one-bit registers coupled to a respective one of the programmable logic circuits. The programmable input/output blocks are each coupled to an output port of a respective programmable selector circuit and to a respective input port of the programmable interconnect circuit.
摘要翻译： PLD可配置为有效地实现各种用户功能。 PLD包括可编程互连电路，可编程逻辑电路，一位寄存器，选择器电路和输入/输出块。可编程互连电路可配置为将其输出端口的信号线连接到其输入端口的信号线。可编程逻辑电路可配置为实现从可编程互连电路的相应输出端口产生一位信号值的可编程功能。一位寄存器存储这些一位信号值中的相应的一个。可编程选择器电路各自耦合到多个一位寄存器的输出端口，这些一位寄存器中的每一个耦合到相应的一个可编程逻辑电路。可编程输入/输出块分别耦合到相应可编程选择器电路的输出端口和可编程互连电路的相应输入端口。

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