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1. 发明授权

US09042431B1 Wide band deterministic interface 有权
标题翻译：宽带确定性接口
公开(公告)号：US09042431B1
公开(公告)日：2015-05-26
申请号：US12391712
申请日：2009-02-24
申请人： Venkat Yadavalli , Sridhar Krishnamurthy , Gerardo Orlando , David Richardson King , Ken Clauss , Mark Krumpoch , Peter Markou
发明人： Venkat Yadavalli , Sridhar Krishnamurthy , Gerardo Orlando , David Richardson King , Ken Clauss , Mark Krumpoch , Peter Markou
IPC分类号： H04B1/38 , H04L1/24 , H04L1/00
CPC分类号： H04L1/243 , H04L1/0001
摘要： A transceiver with non-deterministic delay characteristics is analyzed and adjusted to provide a transceiver with deterministic delay characteristics. The transceiver may be implemented with a variety of device types to support high bandwidth operation over a wide range of frequencies. Deterministic behavior allows use of the transceiver in source synchronous interfaces. The transceiver may also be dynamically analyzed and adjusted during operation as operation frequency changes.
摘要翻译：分析和调整具有非确定性延迟特性的收发器，以提供具有确定性延迟特性的收发器。收发器可以用各种设备类型来实现，以支持在宽范围的频率上的高带宽操作。确定性行为允许在源同步接口中使用收发器。收发器在操作频率变化时也可以动态分析和调整。

2. 发明授权

US07926016B1 Timing driven logic block configuration 有权
标题翻译：定时驱动逻辑块配置
公开(公告)号：US07926016B1
公开(公告)日：2011-04-12
申请号：US12344155
申请日：2008-12-24
申请人： Priya Sundararajan , Sridhar Krishnamurthy
发明人： Priya Sundararajan , Sridhar Krishnamurthy
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A method of configuring a logic block of a programmable logic device (PLD) during physical implementation of a circuit design, wherein ports of the logic block are selectively registered, can include identifying the logic block of the PLD, wherein the logic block is located on a critical path. For each of a plurality of selectively registerable portions of the logic block, the method can include computing input slacks and output slacks based upon potential register usage within the logic block. The method further can include determining register usage for the logic block by maximizing a function which depends upon a measure of worst case slack for pipeline stages.
摘要翻译：一种在电路设计的物理实现期间配置可编程逻辑器件（PLD）的逻辑块的方法，其中逻辑块的端口被选择性地注册，可以包括识别PLD的逻辑块，其中逻辑块位于一个关键的路径。对于逻辑块的多个可选择地可注册部分中的每一个，该方法可以包括基于逻辑块内的潜在寄存器使用计算输入宽度和输出宽度。该方法还可以包括通过使取决于流水线级的最差情况松弛的度量的函数最大化来确定逻辑块的寄存器使用。

3. 发明授权

US07610573B1 Implementation of alternate solutions in technology mapping and placement 有权
标题翻译：在技术测绘和放置中实施替代解决方案
公开(公告)号：US07610573B1
公开(公告)日：2009-10-27
申请号：US11881307
申请日：2007-07-26
申请人： Vi Chi Chan , Tetse Jang , Sridhar Krishnamurthy , Kevin Chung
发明人： Vi Chi Chan , Tetse Jang , Sridhar Krishnamurthy , Kevin Chung
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F2217/08
摘要： A computer-implemented method of implementing a circuit design within a target integrated circuit (IC) can include, during technology mapping of the circuit design, determining a plurality of implementations of at least one sub-circuit of the circuit design and placing the circuit design on the target IC using a primary implementation of the plurality of implementations of the sub-circuit. The primary implementation of the sub-circuit can be selectively replaced with an alternate implementation of the sub-circuit selected from the plurality of implementations of the sub-circuit. The placed circuit design, including either the primary implementation or the alternate implementation of the sub-circuit, can be output.
摘要翻译：在目标集成电路（IC）中实现电路设计的计算机实现的方法可以包括在电路设计的技术映射期间，确定电路设计的至少一个子电路的多个实现并且将电路设计在目标IC上使用子电路的多个实现的主要实现。子电路的主要实现可以被选择性地替换为从子电路的多个实现中选择的子电路的替代实现。可以输出放置的电路设计，包括子电路的主要实现或替代实现。

4. 发明授权

US07058919B1 Methods of generating test designs for testing specific routing resources in programmable logic devices 失效
标题翻译：生成用于测试可编程逻辑器件中特定路由资源的测试设计的方法
公开(公告)号：US07058919B1
公开(公告)日：2006-06-06
申请号：US10696357
申请日：2003-10-28
申请人： Jay T. Young , Sridhar Krishnamurthy , Jeffrey V. Lindholm , Ian L. McEwen
发明人： Jay T. Young , Sridhar Krishnamurthy , Jeffrey V. Lindholm , Ian L. McEwen
IPC分类号： G06F17/50
CPC分类号： G01R31/318516 , G01R31/31704
摘要： Methods of directly targeting specified routing resources in a PLD, e.g., routing resources that need to be tested. Test designs are produced that implement observable nets using the targeted routing resources. A PLD router is used to route from a target routing resource backwards through the routing fabric of the PLD to the source of an observable net. The net is identified based on the source, and loads of the net are identified as router load targets. The router is then used to route from the target routing resource forwards to one of the loads on the net. This process can be repeated for a list of target routing resources to provide a test design that tests as many of the targeted routing resources as possible. Additional test designs can be created to test remaining target routing resources. In other embodiments, the router routes first forwards, then backwards.
摘要翻译：直接针对PLD中的指定路由资源的方法，例如路由需要测试的资源。使用目标路由资源实现可观察网络的测试设计。 PLD路由器用于从目标路由资源向后路由PLD的路由结构到可观察网络的源。网络基于源标识，网络的负载被标识为路由器负载目标。路由器然后用于从目标路由资源转发到网络上的一个负载。可以针对目标路由资源列表重复此过程，以提供尽可能多的目标路由资源的测试设计。可以创建其他测试设计来测试剩余的目标路由资源。在其他实施例中，路由器首先向前路由，然后向后路由。

5. 发明授权

US06574655B1 Associative management of multimedia assets and associated resources using multi-domain agent-based communication between heterogeneous peers 有权
标题翻译：多媒体资产和相关资源的联合管理使用异构同层之间的多域代理进行通信
公开(公告)号：US06574655B1
公开(公告)日：2003-06-03
申请号：US09342490
申请日：1999-06-29
申请人： Scott A. Libert , Robert J. Woolridge , Baochun Jin , Alex C. Tran , P. Murugavel , Mark S. Hillebrandt , Suhas Joshi , Sridhar Krishnamurthy , Rajagopal Govindakrishnan
发明人： Scott A. Libert , Robert J. Woolridge , Baochun Jin , Alex C. Tran , P. Murugavel , Mark S. Hillebrandt , Suhas Joshi , Sridhar Krishnamurthy , Rajagopal Govindakrishnan
IPC分类号： G06F1516
CPC分类号： H04L67/104 , H04L29/06027 , H04L63/10 , H04L67/2819 , H04L67/2823 , H04L67/2828 , H04L69/24 , H04L69/329 , H04L2463/101 , Y10S707/99945
摘要： Associative management of distributed multimedia assets and associated resources using multi-domain agent-based communication between heterogeneous peers is achieved using an Asset/Resource Management (ARM) platform architecture that has an ARM Framework that is used by Asset Management Agents. The ARM Framework includes an ARM Infrastructure which is a system of protocols and libraries from which communities of agents that are grouped in logical Agent Domains are built. The agents communicate via the KQML language embedded within TCP/IP messages, advertise their capabilities and cooperate together to perform meaningful work. An XML-based language is used to embed “content” within the KQML language, providing a self-describing data representation using various character sets. The ARM Framework includes system agents including in each Agent Domain a Resolver for keeping track of asset logical locations, an Agent Name Server (ANS) for keeping track of security access to the assets, and the “Yellow Pages” containing the Advertised System Knowledge (ASK) agent for keeping track of the capabilities of the Asset Management Agents.
摘要翻译：使用具有由资产管理代理使用的ARM框架的资产/资源管理（ARM）平台架构实现了使用异构对等体之间的基于多域代理的通信的分布式多媒体资产和相关资源的关联管理。 ARM框架包括一个ARM基础架构，它是一个协议和库的系统，构建了分组在逻辑代理域中的代理团体。代理人通过嵌入在TCP / IP消息中的KQML语言进行通信，宣传他们的能力，并且携手合作，进行有意义的工作。使用基于XML的语言将“内容”嵌入到KQML语言中，使用各种字符集提供自描述数据表示。 ARM框架包括系统代理，包括每个代理域中的一个用于跟踪资产逻辑位置的解析器，用于跟踪资产安全访问的代理名称服务器（ANS）和包含广告系统知识的“黄页”（ ASK）代理，用于跟踪资产管理代理的能力。

6. 发明申请

US20060267798A1 SYSTEMS AND METHODS FOR GENERATING NETWORK MESSAGES 有权
标题翻译：用于生成网络信息的系统和方法
公开(公告)号：US20060267798A1
公开(公告)日：2006-11-30
申请号：US11419362
申请日：2006-05-19
申请人： Paul Jacobsen , Scott Guillaudeu , David Freeman , Sridhar Krishnamurthy
发明人： Paul Jacobsen , Scott Guillaudeu , David Freeman , Sridhar Krishnamurthy
IPC分类号： G08G1/097 , G08G1/095 , G08G1/07
CPC分类号： H04L43/50
摘要： A networking system may include a traffic generator. The traffic generator may include a scripting module configured to create a script. The traffic generator may execute the script to send and/or receive network messages within the networking system, which may help test one or more components of the networking system. The script may include one or more entries. An entry may be configured to instruct the traffic generator to send one or more network messages.
摘要翻译：网络系统可以包括业务发生器。流量生成器可以包括被配置为创建脚本的脚本模块。业务发生器可以执行脚本以在网络系统内发送和/或接收网络消息，这可以帮助测试网络系统的一个或多个组件。脚本可以包括一个或多个条目。条目可以被配置为指示业务生成器发送一个或多个网络消息。

7. 发明授权

US07111214B1 Circuits and methods for testing programmable logic devices using lookup tables and carry chains 失效
标题翻译：使用查找表和携带链测试可编程逻辑器件的电路和方法
公开(公告)号：US07111214B1
公开(公告)日：2006-09-19
申请号：US10268877
申请日：2002-10-09
申请人： Kamal Chaudhary , Sridhar Krishnamurthy
发明人： Kamal Chaudhary , Sridhar Krishnamurthy
IPC分类号： G01R31/28 , G06F11/00 , G06F7/38 , H01L25/00
CPC分类号： G06F11/263
摘要： Circuit implementations and test methods enable the testing of lookup table (LUT) input paths, “stuck at” memory cell values, and carry chains. One method includes storing a first bit pattern in each LUT, configuring the carry chain to perform a wide AND function of the LUT outputs, and cycling the inputs of each LUT while comparing the carry chain output to an expected value and reporting the PLD faulty if a difference is detected. The carry chain is configured to perform a wide OR function, and the cycling step is repeated. The bit pattern within each LUT is changed to the complement of the first bit pattern by providing a series of shift commands or by otherwise storing new values in the LUT, and the configuring and cycling steps are repeated. The invention also provides PLD circuit implementations that can be used to perform the described methods.
摘要翻译：电路实现和测试方法使得能够测试查找表（LUT）输入路径，“卡在”存储单元值，并携带链。一种方法包括在每个LUT中存储第一位模式，配置进位链以执行LUT输出的宽的AND功能，以及循环每个LUT的输入，同时将进位链输出与期望值进行比较，并报告PLD故障是否检测到差异。进位链被配置为执行宽OR功能，并重复循环步骤。每个LUT中的位模式通过提供一系列移位命令或以其他方式在LUT中存储新值来改变为第一位模式的补码，并且重复配置和循环步骤。本发明还提供了可用于执行所述方法的PLD电路实现。

8. 发明申请

US20060149556A1 Sequential-data correlation at real-time on multiple media and multiple data types 审中-公开
标题翻译：在多媒体和多种数据类型上实时进行连续数据相关
公开(公告)号：US20060149556A1
公开(公告)日：2006-07-06
申请号：US11298625
申请日：2005-12-12
申请人： Sridhar Krishnamurthy , Selvaraj Murugaiyan
发明人： Sridhar Krishnamurthy , Selvaraj Murugaiyan
IPC分类号： G10L11/00
CPC分类号： H04L29/06 , H04L29/06027 , H04L67/12 , H04L69/329
摘要： A method and device for synchronizing data between analog and digital mediums recorded either simultaneously from a single source or recorded from different sources, which requires synchronization. User-Data recorded in analog medium is referenced with out-of-band unique digital reference-data that is generated by the interface device to mark the position of the user data. The same reference-data communicated by the device and the user-data are stored in the digital medium also and a relationship is computed and established in the form of a table between the reference-data and the positions of the recorded user-data. Whenever there is a manipulation of the User-data on either of the mediums for the purpose of viewing, listening or editing, the Reference-data in that medium is interpreted by the device and the corresponding location of the user-data in the other medium is accessed by using the table. Manipulation to the user-data done, on either medium, any number of times is reflected on the user-data in the other medium. The objective of data synchronization stands achieved.
摘要翻译：一种用于在从单个源同时记录或从不同来源记录的同时记录的模拟和数字介质之间同步数据的方法和装置，这需要同步。用户 - 记录在模拟媒体中的数据由接口设备生成的带外唯一数字参考数据参考，以标记用户数据的位置。由设备和用户数据传送的相同的参考数据也被存储在数字介质中，并且以参考数据和记录的用户数据的位置之间的表的形式来计算和建立关系。无论何时在任何一种媒体上操纵用户数据以进行观看，收听或编辑，该媒体中的参考数据将被设备和其他媒体中用户数据的对应位置解释可以通过使用表进行访问。对任何媒体上任何次数的完成的用户数据的操作都会反映在其他媒体中的用户数据上。实现数据同步的目标。

9. 发明授权

US06910002B1 Method and apparatus for specifying addressability and bus connections in a logic design 有权
标题翻译：用于在逻辑设计中指定可寻址性和总线连接的方法和装置
公开(公告)号：US06910002B1
公开(公告)日：2005-06-21
申请号：US09649437
申请日：2000-08-23
申请人： Bart Reynolds , Cheng-I Chuang , Chukwuweta Chukwudebe , Sridhar Krishnamurthy , Damon McCormick , Tom Shui , Kai Zhu
发明人： Bart Reynolds , Cheng-I Chuang , Chukwuweta Chukwudebe , Sridhar Krishnamurthy , Damon McCormick , Tom Shui , Kai Zhu
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： In one embodiment, a method for specifying addressability in a memory-mapped device is disclosed. A data access primitive is used to model addressablity for the memory-mapped device. Addressability comprises an address matching function, a lane matching function and one or more bus connections. A first starting address for the memory-mapped device is specified. A first set of addressing matching function, lane matching function and one or more bus connections for the memory-mapped device is generated using the data access primitive and the first starting address.
摘要翻译：在一个实施例中，公开了一种用于指定存储器映射设备中的可寻址性的方法。数据访问原语用于建立内存映射设备的可通信性。可寻址性包括地址匹配功能，车道匹配功能和一个或多个总线连接。指定内存映射设备的第一个起始地址。使用数据访问原语和第一起始地址生成用于存储器映射设备的第一组寻址匹配功能，通道匹配功能和一个或多个总线连接。

10. 发明授权

US08146041B1 Latch based optimization during implementation of circuit designs for programmable logic devices 有权
标题翻译：实现可编程逻辑器件电路设计时的基于锁存器的优化
公开(公告)号：US08146041B1
公开(公告)日：2012-03-27
申请号：US13180782
申请日：2011-07-12
申请人： Sankaranarayanan Srinivasan , Sridhar Krishnamurthy , Brian D. Philofsky , Kamal Chaudhary , Anirban Rahut
发明人： Sankaranarayanan Srinivasan , Sridhar Krishnamurthy , Brian D. Philofsky , Kamal Chaudhary , Anirban Rahut
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/505
摘要： A computer-implemented method of implementing a circuit design within a programmable logic device can include selecting at least one circuit element of the circuit design. The selected circuit element can be converted to a latch. A timing analysis can be performed upon the circuit design after conversion of the selected circuit element to a latch. A determination can be made by a computer as to whether the timing of the circuit design improves and the conversion of the selected circuit element to a latch can be accepted when the timing of the circuit design improves. The circuit design can be output.
摘要翻译：实现可编程逻辑器件内的电路设计的计算机实现的方法可以包括选择电路设计的至少一个电路元件。所选择的电路元件可以被转换成锁存器。在将所选择的电路元件转换为锁存器之后，可以在电路设计上执行时序分析。当电路设计的时序改善时，计算机可以确定电路设计的时序是否改善，并且可以接受所选择的电路元件到锁存器的转换。可以输出电路设计。

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