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1. 发明授权

US07058919B1 Methods of generating test designs for testing specific routing resources in programmable logic devices 失效
标题翻译：生成用于测试可编程逻辑器件中特定路由资源的测试设计的方法
公开(公告)号：US07058919B1
公开(公告)日：2006-06-06
申请号：US10696357
申请日：2003-10-28
申请人： Jay T. Young , Sridhar Krishnamurthy , Jeffrey V. Lindholm , Ian L. McEwen
发明人： Jay T. Young , Sridhar Krishnamurthy , Jeffrey V. Lindholm , Ian L. McEwen
IPC分类号： G06F17/50
CPC分类号： G01R31/318516 , G01R31/31704
摘要： Methods of directly targeting specified routing resources in a PLD, e.g., routing resources that need to be tested. Test designs are produced that implement observable nets using the targeted routing resources. A PLD router is used to route from a target routing resource backwards through the routing fabric of the PLD to the source of an observable net. The net is identified based on the source, and loads of the net are identified as router load targets. The router is then used to route from the target routing resource forwards to one of the loads on the net. This process can be repeated for a list of target routing resources to provide a test design that tests as many of the targeted routing resources as possible. Additional test designs can be created to test remaining target routing resources. In other embodiments, the router routes first forwards, then backwards.
摘要翻译：直接针对PLD中的指定路由资源的方法，例如路由需要测试的资源。使用目标路由资源实现可观察网络的测试设计。 PLD路由器用于从目标路由资源向后路由PLD的路由结构到可观察网络的源。网络基于源标识，网络的负载被标识为路由器负载目标。路由器然后用于从目标路由资源转发到网络上的一个负载。可以针对目标路由资源列表重复此过程，以提供尽可能多的目标路由资源的测试设计。可以创建其他测试设计来测试剩余的目标路由资源。在其他实施例中，路由器首先向前路由，然后向后路由。

2. 发明授权

US07149997B1 Routing with frame awareness to minimize device programming time and test cost 有权
标题翻译：具有框架意识的路由，以最小化设备编程时间和测试成本
公开(公告)号：US07149997B1
公开(公告)日：2006-12-12
申请号：US10966643
申请日：2004-10-15
申请人： Jay T. Young , Jeffrey V. Lindholm , Ian L. McEwen
发明人： Jay T. Young , Jeffrey V. Lindholm , Ian L. McEwen
IPC分类号： G06F17/50 , G06F1/24 , G06F9/45
CPC分类号： G06F17/5077 , G06F17/5054
摘要： A method of routing a design on a programmable logic device (PLD) includes generating a database that identifies the correspondence between routing resources of the PLD and programming frames of the PLD. A first set of programming frames required to implement the logic of the design is identified, and the cost associated with using the first set of programming frames is eliminated. A second set of programming frames that are not used to implement the logic of the design is also identified, and the cost associated with using the second set of programming frames is maximized. Interconnect networks of the design are then routed, taking into account the costing of the programming frames. When a programming frame from the second set is used, the cost associated with using this programming frame is eliminated. This method minimizes used programming frames and maximizes unused programming frames, thus reducing PLD configuration time.
摘要翻译：在可编程逻辑器件（PLD）上路由设计的方法包括生成识别PLD的路由资源与PLD的编程帧之间的对应关系的数据库。识别实现设计逻辑所需的第一组编程框架，消除与使用第一组编程帧相关联的成本。还识别出不用于实现设计逻辑的第二组编程帧，并且与使用第二组编程帧相关联的成本最大化。然后将设计的互连网络路由，同时考虑到编程帧的成本计算。当使用来自第二组的编程帧时，消除了与使用该编程帧相关联的成本。这种方法最大限度地减少了使用的编程帧并使未使用的编程帧最大化，从而减少了PLD配置时间。

3. 发明授权

US06944809B2 Methods of resource optimization in programmable logic devices to reduce test time 有权
标题翻译：可编程逻辑器件资源优化方法，以减少测试时间
公开(公告)号：US06944809B2
公开(公告)日：2005-09-13
申请号：US10214025
申请日：2002-08-06
申请人： Andrew W. Lai , Randy J. Simmons , Teymour M. Mansour , Vincent L. Tong , Jeffrey V. Lindholm , Jay T. Young , William R. Troxel , Sridhar Krishnamurthy
发明人： Andrew W. Lai , Randy J. Simmons , Teymour M. Mansour , Vincent L. Tong , Jeffrey V. Lindholm , Jay T. Young , William R. Troxel , Sridhar Krishnamurthy
IPC分类号： G06F17/50 , G01R31/28
CPC分类号： G06F17/5054
摘要： Methods of optimizing the use of routing resources in programmable logic devices (PLDs) to minimize test time. A set of routing resources is identified that are not used in most designs, and a device model is provided to the user that prevents the use of these resources. Because the routing resources will never be used, they need not be tested by the PLD manufacturer, significantly reducing the test time. For example, each PLD within a PLD family is typically designed using a different number of similar tiles. Thus, smaller PLDs in the family include an unnecessarily large number of routing resources. These excessive routing resources can be disabled during implementation of a design. In another example, each tile along the edges of an array includes routing resources designed primarily to provide access to tiles that are not present. These redundant routing resources can be disabled during implementation of a design.
摘要翻译：优化可编程逻辑器件（PLD）中路由资源使用的方法，以最小化测试时间。识别出在大多数设计中未使用的一组路由资源，并且向用户提供阻止使用这些资源的设备模型。由于路由资源永远不会被使用，所以不需要由PLD制造商进行测试，从而大大减少测试时间。例如，PLD系列中的每个PLD通常使用不同数量的相似瓦片来设计。因此，家族中较小的PLD包括不必要的大量路由资源。这些过度的路由资源可以在实现设计期间被禁用。在另一示例中，沿着阵列的边缘的每个瓦片包括主要用于提供对不存在的瓦片的访问的布线资源。这些冗余路由资源可以在实现设计期间被禁用。

4. 发明授权

US07249335B1 Methods of routing programmable logic devices to minimize programming time 失效
标题翻译：路由可编程逻辑器件以最小化编程时间的方法
公开(公告)号：US07249335B1
公开(公告)日：2007-07-24
申请号：US11590132
申请日：2006-10-31
申请人： Jay T. Young , Jeffrey V. Lindholm , Sridhar Krishnamurthy
发明人： Jay T. Young , Jeffrey V. Lindholm , Sridhar Krishnamurthy
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： Methods of routing a design in a programmable logic device (PLD) to increase the effectiveness of applying a multi-frame write (MFW) compression technique to the resulting configuration bitstream. The methods apply placement patterns and/or routing templates to encourage the inclusion of numbers of duplicated routing paths in the routed design. The duplicated routing paths result in duplicated configuration data. Thus, a configuration bitstream implementing the routed design in the PLD includes numbers of duplicated configuration data frames, and is well-suited to benefit from MFW compression techniques.
摘要翻译：将设计路由到可编程逻辑器件（PLD）中以提高将多帧写入（MFW）压缩技术应用于所得配置比特流的有效性的方法。这些方法应用放置模式和/或路由模板，以鼓励在路由设计中包含多个重复的路由路径。复制的路由路径导致重复的配置数据。因此，在PLD中实现路由设计的配置比特流包括复制的配置数据帧的数量，并且非常适合于受益于MFW压缩技术。

5. 发明授权

US07143384B1 Methods of routing programmable logic devices to minimize programming time 失效
标题翻译：路由可编程逻辑器件以最小化编程时间的方法
公开(公告)号：US07143384B1
公开(公告)日：2006-11-28
申请号：US10716947
申请日：2003-11-18
申请人： Jay T. Young , Jeffrey V. Lindholm , Sridhar Krishnamurthy
发明人： Jay T. Young , Jeffrey V. Lindholm , Sridhar Krishnamurthy
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5077
摘要： Methods of routing a design in a programmable logic device (PLD) to increase the effectiveness of applying a multi-frame write (MFW) compression technique to the resulting configuration bitstream. The methods apply placement patterns and/or routing templates to encourage the inclusion of numbers of duplicated routing paths in the routed design. The duplicated routing paths result in duplicated configuration data. Thus, a configuration bitstream implementing the routed design in the PLD includes numbers of duplicated configuration data frames, and is well-suited to benefit from MFW compression techniques.
摘要翻译：将设计路由到可编程逻辑器件（PLD）中以提高将多帧写入（MFW）压缩技术应用于所得配置比特流的有效性的方法。这些方法应用放置模式和/或路由模板，以鼓励在路由设计中包含多个重复的路由路径。复制的路由路径导致重复的配置数据。因此，在PLD中实现路由设计的配置比特流包括复制的配置数据帧的数量，并且非常适合于受益于MFW压缩技术。

6. 发明授权

US08418221B1 Methods of prioritizing routing resources to generate and evaluate test designs in programmable logic devices 有权
标题翻译：优化路由资源以生成和评估可编程逻辑设备中的测试设计的方法
公开(公告)号：US08418221B1
公开(公告)日：2013-04-09
申请号：US10777421
申请日：2004-02-12
申请人： Jay T. Young , Ian L. McEwen
发明人： Jay T. Young , Ian L. McEwen
IPC分类号： G06F21/00
CPC分类号： G01R31/318516 , G01R31/31704 , G06F17/5054 , G06F17/5077
摘要： Methods of prioritizing untested routing resources in programmable logic devices (PLDs) to generate test suites that include a minimal number of test designs. The untested routing resources are prioritized (e.g., placed into an ordered list) based on a number of untested input or output terminals for each untested resource. The number of untested input or output terminals (whichever is larger) for each routing resource determines the minimum number of additional test designs in which the routing resource must be included. The resulting prioritization can be utilized by a router, for example, to first include in test designs those routing resources that must be included in the largest remaining number of test designs. The described prioritization methods can also be used to select one of two or more test designs that should be included in the overall test suite. In each case, the overall number of test designs is reduced.
摘要翻译：在可编程逻辑器件（PLD）中对未经测试的路由资源进行优先级排序以生成包含最少数量的测试设计的测试套件的方法。未经测试的路由资源基于每个未测试资源的未测试的输入或输出终端的数量被优先排列（例如，放置在有序列表中）。每个路由资源的未测试的输入或输出终端数量（以较大者为准）决定必须包含路由资源的其他测试设计的最小数量。所产生的优先级可由路由器利用，例如，首先在测试设计中包括必须包含在最大剩余数量的测试设计中的路由资源。所描述的优先级方法也可用于选择应包括在整个测试套件中的两个或多个测试设计之一。在每种情况下，测试设计的总数减少。

7. 发明授权

US07480842B1 Method and apparatus for reducing the number of test designs for device testing 有权
标题翻译：减少设备测试设计数量的方法和设备
公开(公告)号：US07480842B1
公开(公告)日：2009-01-20
申请号：US10892603
申请日：2004-07-16
申请人： Jay T. Young , Ian L. McEwen , Reto Stamm
发明人： Jay T. Young , Ian L. McEwen , Reto Stamm
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G06F11/263 , G01R31/31704 , G01R31/318516
摘要： The present invention includes an apparatus and method to optimize a set of test designs to obtain complete coverage while reducing bit stream size for programmable fabric. Test designs are selected that do not result in lost coverage. The method selects a set of test designs, removes the set of test designs, and then determines if coverage is lost. If coverage is lost, the method creates a new set of test designs to test the lost coverage. If the new set of test designs is smaller than the removed set, the new set of test designs is added to the test design suite; otherwise the removed test designs are added back to the test design suite. The decision to add the new test designs or removed test designs is based on a number of criteria including evaluating the number of uniquely tested resources in each test design.
摘要翻译：本发明包括一种用于优化一组测试设计以获得完整覆盖同时减少可编程结构的位流大小的装置和方法。选择的测试设计不会导致覆盖率的损失。该方法选择一组测试设计，删除一组测试设计，然后确定覆盖是否丢失。如果覆盖丢失，该方法将创建一组新的测试设计来测试丢失的覆盖。如果新的一组测试设计小于移除的集合，则将新的测试设计集合添加到测试设计套件中; 否则将删除的测试设计添加回测试设计套件。添加新的测试设计或删除的测试设计的决定基于许多标准，包括评估每个测试设计中唯一测试的资源的数量。

8. 发明授权

US07299430B1 Reducing design execution run time bit stream size for device testing 失效
标题翻译：减少设计执行运行时位流大小进行设备测试
公开(公告)号：US07299430B1
公开(公告)日：2007-11-20
申请号：US11064369
申请日：2005-02-23
申请人： Ian L. McEwen , Jay T. Young
发明人： Ian L. McEwen , Jay T. Young
IPC分类号： G06F17/50 , G01R31/28
CPC分类号： G01R31/318519
摘要： A method of testing a programmable logic device (PLD) can include distinguishing between stages within the design that uniquely test a routing resource and stages that do not. The method also can include un-routing at least a portion of the design corresponding to one or more of the stages that do not uniquely test a routing resource. The stage(s) can be excluded from the design. The portion of the design that was un-routed can be re-routed by passing those stages that do not uniquely test a routing resource.
摘要翻译：测试可编程逻辑器件（PLD）的方法可以包括区分设计中唯一测试路由资源的阶段和不进行路由资源的阶段。该方法还可以包括对与不唯一测试路由资源的一个或多个阶段相对应的设计的至少一部分进行解路由。舞台可以从设计中排除。通过传递不唯一测试路由资源的那些阶段，可以重新路由未路由的设计部分。

9. 发明授权

US07890917B1 Method and apparatus for providing secure intellectual property cores for a programmable logic device 有权
标题翻译：为可编程逻辑器件提供安全的知识产权核心的方法和装置
公开(公告)号：US07890917B1
公开(公告)日：2011-02-15
申请号：US12008848
申请日：2008-01-14
申请人： Jay T. Young , Jeffrey M. Mason
发明人： Jay T. Young , Jeffrey M. Mason
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： Method and apparatus for providing secure intellectual property (IP) cores for a programmable logic device (PLD) are described. An aspect of the invention relates to a method of securely distributing an IP core for PLDs. A circuit design is generated for the IP core, the circuit design being re-locatable in a programmable fabric for PLDs. The circuit design is encoded to produce at least one partial configuration bitstream. Implementation data is generated for utilizing the IP core as a reconfigurable module in top-level circuit designs. The at least one partial configuration bitstream and the implementation data are delivered to users of the PLDs.
摘要翻译：描述了用于为可编程逻辑器件（PLD）提供安全知识产权（IP）内核的方法和装置。本发明的一个方面涉及一种可靠地分配用于PLD的IP核的方法。为IP核生成电路设计，电路设计可重新定位在PLD的可编程结构中。电路设计被编码以产生至少一个部分配置比特流。生成实现数据，以将IP核作为顶级电路设计中的可重新配置模块。将至少一个部分配置比特流和实现数据传送给PLD的用户。

10. 发明授权

US07509617B1 Design methodology to support relocatable bit streams for dynamic partial reconfiguration of FPGAs to reduce bit stream memory requirements 有权
标题翻译：支持可重定位比特流的设计方法，用于FPGA的动态部分重配置，以减少位流内存需求
公开(公告)号：US07509617B1
公开(公告)日：2009-03-24
申请号：US11225248
申请日：2005-09-12
申请人： Jay T. Young
发明人： Jay T. Young
IPC分类号： G06F17/50
CPC分类号： G06F17/5027
摘要： A method for generating a design for an FPGA provides for partial reconfiguration by allowing relocation of the same single bitstream within different areas of the FPGA, reducing overall design time and PROM storage space needed for the design. The design rules for the method include a requirement that the same frames oriented in the same relative location be available in dynamic areas where a bit stream will be located. Further, the rules require the same relative communication interfaces be available between the dynamic areas and static areas when the bit stream is relocated. Additionally the design rules require global resources, such as clock resources used by the static areas remain the same when the bit stream is relocated.
摘要翻译：用于生成FPGA设计的方法通过允许在FPGA的不同区域内重新定位相同的单个比特流来实现部分重新配置，从而减少设计所需的总体设计时间和PROM存储空间。该方法的设计规则包括要求在相同相对位置定向的相同帧在位流将位于的动态区域中可用。此外，当重新定位位流时，规则要求在动态区域和静态区域之间具有相同的相对通信接口。此外，设计规则需要全局资源，例如当位流重新定位时，静态区域使用的时钟资源保持不变。

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