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1. 发明授权

US4996576A Radiation-sensitive device 失效
标题翻译：辐射敏感设备
公开(公告)号：US4996576A
公开(公告)日：1991-02-26
申请号：US355053
申请日：1989-05-15
申请人： William T. Lynch , Lalita Manchanda
发明人： William T. Lynch , Lalita Manchanda
IPC分类号： H01L31/119
CPC分类号： H01L31/119
摘要： A p-channel depletion-mode MOS device is utilized for measuring low levels of ionizing radiation.
摘要翻译： p沟道耗尽型MOS器件用于测量低水平的电离辐射。

2. 发明授权

US4825278A Radiation hardened semiconductor devices 失效
标题翻译：辐射硬化半导体器件
公开(公告)号：US4825278A
公开(公告)日：1989-04-25
申请号：US20771
申请日：1987-03-02
申请人： Steven J. Hillenius , William T. Lynch , Lalita Manchanda
发明人： Steven J. Hillenius , William T. Lynch , Lalita Manchanda
IPC分类号： H01L21/765 , H01L23/58 , H01L23/60 , H01L29/06 , H01L29/40
CPC分类号： H01L29/402 , H01L21/765 , H01L23/585 , H01L23/60 , H01L2924/0002 , Y10S257/906
摘要： Disclosed are semiconductor devices and circuits which are highly resistant to the effects of radiation. A thin conductive layer, which is biased at substrate potential, and a thin oxide are provided under the usual field oxide of the devices. The conductive layer shields the semiconductor substrate from the effects of charge generation in the field oxide due to radiation absorption.
摘要翻译：公开了对辐射效应高度耐受的半导体器件和电路。在器件的通常的场氧化物下方设置偏置于衬底电位的薄导电层和薄氧化物。由于辐射吸收，导电层屏蔽半导体衬底免受场氧化物中的电荷产生的影响。

3. 发明授权

US5373180A Planar isolation technique for integrated circuits 失效
标题翻译：集成电路的平面隔离技术
公开(公告)号：US5373180A
公开(公告)日：1994-12-13
申请号：US121082
申请日：1993-09-14
申请人： Steven J. Hillenius , William T. Lynch , Lalita Manchanda , Mark R. Pinto , Sheila Vaidya
发明人： Steven J. Hillenius , William T. Lynch , Lalita Manchanda , Mark R. Pinto , Sheila Vaidya
IPC分类号： H01L29/73 , H01L21/331 , H01L21/76 , H01L21/762 , H01L21/763 , H01L29/78 , H01L27/04
CPC分类号： H01L21/76224 , H01L21/76205 , H01L21/763
摘要： Through the use of a specifically configured buried dielectric region, devices with strict design rules, e.g., design rules of 0.9 micrometers and less, are significantly improved. In particular, the recessed dielectric region, e.g., field oxide, separating device areas in an integrated circuit, either has a buried conducting shield surrounding the periphery of the oxide or has a configuration such that the upper surface of the dielectric is no more than 20 nm below the upper surface of the silicon forming the device active region. By insuring a suitable configuration, parasitic capacitance resulting in slower operation is considerably reduced while leakage currents are maintained at an acceptable level.
摘要翻译：通过使用特定配置的埋入介质区域，具有严格设计规则（例如0.9微米及更小的设计规则）的器件被显着改进。特别地，集成电路中的凹陷介质区域，例如场氧化物，分离器件区域，或者具有围绕氧化物周围的埋入导电屏蔽层，或具有这样的结构，使得电介质的上表面不超过20 在形成器件有源区的硅的上表面下方。通过确保合适的配置，导致较慢操作的寄生电容显着降低，而漏电流保持在可接受的水平。

4. 发明授权

US5212112A Selective epitaxy of silicon in silicon dioxide apertures with suppression of unwanted formation of facets 失效
标题翻译：硅酮二氧化硅选择性外观与抑制形成面料的抑制
公开(公告)号：US5212112A
公开(公告)日：1993-05-18
申请号：US704749
申请日：1991-05-23
申请人： William T. Lynch
发明人： William T. Lynch
IPC分类号： H01L21/20 , H01L21/336 , H01L21/76 , H01L21/762 , H01L29/78
CPC分类号： H01L21/76294 , H01L21/02381 , H01L21/02532 , H01L21/0262 , H01L21/02639
摘要： In the prior art, selective epitaxial growth (SEG) of semiconductors, performed typically in rectangular windows penetrating through a masking layer located on a major surface of semiconductor substrate, suffers from unwanted facet formation at the corners of the windows--whereby the desirable planar area available for transistor fabrication is reduced. Such facet formation is suppressed--i.e., the area occupied by unwanted facets is reduced--by adding a relatively small lobe penetrating through the masking layer at each corner of each window prior to performing the SEG, whereby transistor packing density can be increased.

5. 发明授权

US4992394A Self aligned registration marks for integrated circuit fabrication 失效
标题翻译：用于集成电路制造的自对准对准标记
公开(公告)号：US4992394A
公开(公告)日：1991-02-12
申请号：US387721
申请日：1989-07-31
申请人： Robert L. Kostelak, Jr. , William T. Lynch , Sheila Vaidya
发明人： Robert L. Kostelak, Jr. , William T. Lynch , Sheila Vaidya
IPC分类号： H01L29/73 , H01L21/027 , H01L21/30 , H01L21/331 , H01L21/8249 , H01L23/544 , H01L27/06 , H01L29/732
CPC分类号： H01L23/544 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , Y10S438/975
摘要： In order to reduce alignment errors arising in the fabrication of semiconductor integrated circuits using electron beam lithography, enhanced registration marks--(i.e., registration marks that are more easily and accurately detectable by the electron beam)--are formed at the edges of oxide layers, located at the surface of a silicon body, by means of forming metal silicide layers having edges coincident with the edges of the oxide layers. Advantageously, the enhancing of the registgration marks by forming the metal silicide is performed subsequent to any high temperature processing steps, whereby the integrity of the marks is maintained.
摘要翻译：为了减少在使用电子束光刻的半导体集成电路的制造中产生的对准误差，在氧化物层的边缘处形成增强的对准标记（即，由电子束更容易和精确地检测的对准标记）通过形成具有与氧化物层的边缘重合的边缘的金属硅化物层，位于硅体的表面。有利的是，在任何高温处理步骤之后执行通过形成金属硅化物来增强注册标记，从而保持标记的完整性。

6. 发明授权

US5848187A Method and apparatus for entering and manipulating spreadsheet cell data 失效
公开(公告)号：US5848187A
公开(公告)日：1998-12-08
申请号：US486733
申请日：1995-06-07
申请人： Daniel Bricklin , William T. Lynch , John Friend
发明人： Daniel Bricklin , William T. Lynch , John Friend
IPC分类号： G06F17/21 , G06F17/24 , G06K9/22 , G06K9/62
CPC分类号： G06F17/246 , G06F17/211 , G06F17/24 , G06K9/00429
摘要： A method for entering and manipulating spreadsheet cell data is described. The present invention provides a method for determining the target cell for written information and for scaling the information to fit within the boundaries of the target cell. A multi-tiered character recognition scheme is used to improve the accuracy and speed of character recognition and translation of handwritten data. The original handwritten data is preserved so that either the translated data or original data may be displayed. The present invention also provides for improved editing of cell entries by allowing a plurality of editing tools to be selected. Manipulation of blocks of data can be accomplished with simple gestures. Arithmetic, statistical and logical functions can be invoked with a single command.

7. 发明授权

US5539214A Quantum bridges fabricated by selective etching of superlattice structures 失效
标题翻译：通过选择性蚀刻超晶格结构制造的量子桥
公开(公告)号：US5539214A
公开(公告)日：1996-07-23
申请号：US384166
申请日：1995-02-06
申请人： William T. Lynch , Kang L. Wang , Martin O. Tanner
发明人： William T. Lynch , Kang L. Wang , Martin O. Tanner
IPC分类号： H01L29/12 , H01L31/0352 , H01L33/04 , H01L33/06 , H01L29/06 , H01L31/0328
CPC分类号： H01L33/06 , B82Y10/00 , B82Y20/00 , H01L29/125 , H01L31/0352 , H01L31/035254 , H01L33/04
摘要： A quantum bridge structure including wires of a semiconductor material such as silicon which are formed by selectively etching a superlattice of alternating layers of at least two semiconductor materials. The quantum bridge is useful as a photo emission device, a photo detector device, and a chemical sensor. The wires exhibit improved electrical conduction properties due to decreased Coulomb scattering.
摘要翻译：包括通过选择性地蚀刻至少两种半导体材料的交替层的超晶格而形成的诸如硅的半导体材料的导线的量子桥结构。量子桥可用作光发射器件，光电检测器件和化学传感器。由于库仑散射减少，电线表现出改善的导电性能。

8. 发明授权

US5432366A P-I-N MOSFET for ULSI applications 失效
标题翻译： P-I-N MOSFET用于ULSI应用
公开(公告)号：US5432366A
公开(公告)日：1995-07-11
申请号：US70715
申请日：1993-05-28
申请人： Sanjay K. Banerjee , Suryanarayana Bhattacharya , William T. Lynch
发明人： Sanjay K. Banerjee , Suryanarayana Bhattacharya , William T. Lynch
IPC分类号： H01L21/336 , H01L29/10 , H01L29/78
CPC分类号： H01L29/66477 , H01L29/1045 , H01L29/41783 , H01L29/66583 , H01L29/66537
摘要： A MOSFET device for ULSI circuits includes a semiconductor body having first and second spaced doped regions of a first conductivity type which function as source and drain regions, a third doped region between the first and second regions of a second conductivity type, and a first intrinsic region between the third doped region and the drain region, a channel of said MOSFET device including the third doped region and said first intrinsic region. Preferably the device further includes a second intrinsic region between the third doped region and the source region, the channel region of the MOSFET device including the third doped region, the first intrinsic region, and the second intrinsic region. The device further includes an insulating layer over the channel region and a gate electrode formed on the insulating layer over the channel region. A source electrode contact, the first doped region, and a drain electrode contact the second doped region. Several processes are described for fabricating the device.
摘要翻译：用于ULSI电路的MOSFET器件包括半导体本体，其具有第一和第二间隔的第一导电类型的掺杂区域，其作为源极和漏极区域，第二和第二导电类型的第一和第二区域之间的第三掺杂区域，所述第三掺杂区域和所述漏极区域之间的区域，所述MOSFET器件的沟道包括所述第三掺杂区域和所述第一本征区域。优选地，该器件还包括在第三掺杂区域和源极区域之间的第二本征区域，MOSFET器件的沟道区域包括第三掺杂区域，第一本征区域和第二本征区域。该器件还包括在沟道区上的绝缘层和形成在沟道区上的绝缘层上的栅电极。源电极接触，第一掺杂区和漏电极接触第二掺杂区。描述了用于制造装置的几个过程。

9. 发明授权

US4824796A Process for manufacturing semiconductor BICMOS device 失效
标题翻译：制造半导体BICMOS器件的工艺
公开(公告)号：US4824796A
公开(公告)日：1989-04-25
申请号：US77953
申请日：1987-07-10
申请人： Tzu-Yin Chiu , Gen M. Chin , Ronald C. Hanson , Maureen Y. Lau , Kwing F. Lee , Mark D. Morris , Alexander M. Voshchenkov , Avinoam Kornblit , Joseph Lebowitz , William T. Lynch
发明人： Tzu-Yin Chiu , Gen M. Chin , Ronald C. Hanson , Maureen Y. Lau , Kwing F. Lee , Mark D. Morris , Alexander M. Voshchenkov , Avinoam Kornblit , Joseph Lebowitz , William T. Lynch
IPC分类号： H01L29/73 , H01L21/225 , H01L21/3215 , H01L21/331 , H01L21/82 , H01L21/8249 , H01L27/06 , H01L29/732 , H01L21/70 , H01L27/00
CPC分类号： H01L29/41783 , H01L21/2257 , H01L21/32155 , H01L21/8249 , H01L27/0623 , Y10S148/009 , Y10S148/01 , Y10S148/124 , Y10S148/151
摘要： A process for creating bipolar and CMOS transistors on a p-type silicon substrate is disclosed. The silicon substrate has typical n+ buried wells and field oxide regions to isolate the individual transistor devices. In accordance with the process, stacks of material are created over the gate elements of the CMOS devices and over the emitter elements of the bipolar transistors. The stacks of material over the gate elements have a silicon dioxide gate layer in contact with the epitaxial layer of the substrate, and the stacks of material over the emitter elements have a polycrystalline silicon layer in contact with the epitaxial layer. Walls of silicon dioxide are created around the stacks in order to insulate the material within the stacks from the material deposited outside of the walls. Polycrystalline silicon in contact with the epitaxial layer is deposited outside the walls surrounding the stacks. All polycrystalline silicon layers in contact with the epitaxial layer are implanted with appropriate dopants such that these layers serve as reservoirs of dopant in order to simultaneously create the source and drain elements of the CMOS devices and the emitter elements of the bipolar devices during a heating step in the process. A tungsten layer is deposited over the polycrystalline layer in order to provide a conductive coupling to aluminum electrodes.
摘要翻译：公开了一种在p型硅衬底上制造双极和CMOS晶体管的工艺。硅衬底具有典型的n +掩埋阱和场氧化物区域以隔离各个晶体管器件。根据该过程，在CMOS器件的栅极元件和双极晶体管的发射极元件之上形成材料堆叠。在栅极元件上的堆叠材料具有与衬底的外延层接触的二氧化硅栅极层，并且在发射极元件上的材料堆叠具有与外延层接触的多晶硅层。在堆叠周围产生二氧化硅壁，以便将堆叠内的材料与沉积在壁外部的材料隔离。与外延层接触的多晶硅沉积在堆叠周围的壁的外部。与外延层接触的所有多晶硅层都注入合适的掺杂剂，使得这些层用作掺杂剂的储存器，以便在加热步骤期间同时产生CMOS器件的源极和漏极元件以及双极器件的发射极元件正在进行中。为了提供与铝电极的导电耦合，在多晶层上沉积钨层。

10. 发明授权

US4822754A Fabrication of FETs with source and drain contacts aligned with the gate electrode 失效
标题翻译：具有与栅电极对准的源极和漏极触点的FET的制造
公开(公告)号：US4822754A
公开(公告)日：1989-04-18
申请号：US619892
申请日：1984-06-12
申请人： William T. Lynch , Frederick Vratny
发明人： William T. Lynch , Frederick Vratny
IPC分类号： H01L21/285 , H01L21/336 , H01L29/417 , H01L29/45 , H01L21/225
CPC分类号： H01L29/66575 , H01L21/28525 , H01L29/41775 , H01L29/41783 , H01L29/456
摘要： A method of fabricating FETs to reduce parasitics. Contact is made to the source and drain regions through a polycrystalline silicon runner which is aligned with the edge of the gate electrode. This is accomplished by providing a multi-level electrode structure including a gate electrode and depositing the polycrystalline silicon layer over the device. The polycrystalline silicon is rendered selectively removable in the portion overlying the gate electrode. When this portion is removed, the remaining polycrystalline is aligned with the gate.
摘要翻译：制造FET以减少寄生效应的方法。通过与栅电极的边缘对准的多晶硅流道对源区和漏区进行接触。这是通过提供一种包括栅电极并在器件上沉积多晶硅层的多电平电极结构来实现的。多晶硅在覆盖栅电极的部分中被选择性地移除。当该部分被去除时，剩余的多晶体与栅极对准。

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