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1. 发明授权

US5539214A Quantum bridges fabricated by selective etching of superlattice structures 失效
标题翻译：通过选择性蚀刻超晶格结构制造的量子桥
公开(公告)号：US5539214A
公开(公告)日：1996-07-23
申请号：US384166
申请日：1995-02-06
申请人： William T. Lynch , Kang L. Wang , Martin O. Tanner
发明人： William T. Lynch , Kang L. Wang , Martin O. Tanner
IPC分类号： H01L29/12 , H01L31/0352 , H01L33/04 , H01L33/06 , H01L29/06 , H01L31/0328
CPC分类号： H01L33/06 , B82Y10/00 , B82Y20/00 , H01L29/125 , H01L31/0352 , H01L31/035254 , H01L33/04
摘要： A quantum bridge structure including wires of a semiconductor material such as silicon which are formed by selectively etching a superlattice of alternating layers of at least two semiconductor materials. The quantum bridge is useful as a photo emission device, a photo detector device, and a chemical sensor. The wires exhibit improved electrical conduction properties due to decreased Coulomb scattering.
摘要翻译：包括通过选择性地蚀刻至少两种半导体材料的交替层的超晶格而形成的诸如硅的半导体材料的导线的量子桥结构。量子桥可用作光发射器件，光电检测器件和化学传感器。由于库仑散射减少，电线表现出改善的导电性能。

2. 发明授权

US5630905A Method of fabricating quantum bridges by selective etching of superlattice structures 失效
标题翻译：通过选择性蚀刻超晶格结构制造量子桥的方法
公开(公告)号：US5630905A
公开(公告)日：1997-05-20
申请号：US465493
申请日：1995-06-05
申请人： William T. Lynch , Kang L. Wang , Martin O. Tanner
发明人： William T. Lynch , Kang L. Wang , Martin O. Tanner
IPC分类号： H01L29/12 , H01L31/0352 , H01L33/04 , H01L33/06 , H01L21/20
CPC分类号： H01L33/06 , B82Y10/00 , B82Y20/00 , H01L29/125 , H01L31/0352 , H01L31/035254 , H01L33/04
摘要： A quantum bridge structure including wires of a semiconductor material such as silicon which are formed by selectively etching a superlattice of alternating layers of at least two semiconductor materials. The quantum bridge is useful as a photo emission device, a photo detector device, and a chemical sensor. The wires exhibit improved electrical conduction properties due to decreased Coulomb scattering.
摘要翻译：包括通过选择性地蚀刻至少两种半导体材料的交替层的超晶格而形成的诸如硅的半导体材料的导线的量子桥结构。量子桥可用作光发射器件，光电检测器件和化学传感器。由于库仑散射减少，电线表现出改善的导电性能。

3. 发明授权

US07535070B2 Spin-wave architectures 有权
标题翻译：旋波架构
公开(公告)号：US07535070B2
公开(公告)日：2009-05-19
申请号：US11668896
申请日：2007-01-30
申请人： Mary M. Eshaghian-Wilner , Alexander Khitun , Kang L. Wang
发明人： Mary M. Eshaghian-Wilner , Alexander Khitun , Kang L. Wang
IPC分类号： H01L45/02
CPC分类号： G11C11/54 , B82Y10/00 , G11C11/14 , H01L29/66984 , H03K19/168 , Y10S977/933
摘要： Nano-scale and multi-scale computational architectures using spin waves as a physical mechanism for device interconnection are provided. Solid-state spin-wave computing devices using nano-scale and multi-scale computational architectures comprised of a plurality of inputs and a plurality of outputs are described where such devices are configured to simultaneously transmit data elements from the inputs to the outputs by using spin-waves of differing frequencies. These devices include but are not limited to a spin-wave crossbar, a spin-wave reconfigurable mesh, a spin-wave fully-interconnected cluster, a hierarchical multi-scale spin-wave crossbar, a hierarchical multi-scale spin-wave reconfigurable mesh and a hierarchical multi-scale spin-wave fully-interconnected cluster.
摘要翻译：提供了使用自旋波作为器件互连的物理机制的纳米级和多尺度计算架构。描述了使用包括多个输入和多个输出的纳米尺度和多尺度计算体系结构的固态自旋波计算设备，其中这样的设备被配置为通过使用旋转从输入到输出同时发送数据元素不同频率的波。这些装置包括但不限于自旋波交叉开关，自旋波可重构网格，自旋波全互连簇，分层多尺度自旋波横截面，分级多尺度自旋波可重构网格以及分层多尺度自旋波全互联集群。

4. 发明申请

US20090096044A1 Spin-Wave Architectures 有权
标题翻译：自旋波建筑
公开(公告)号：US20090096044A1
公开(公告)日：2009-04-16
申请号：US12264560
申请日：2008-11-04
申请人： Mary M. Eshaghian-Wilner , Alexander Khitun , Kang L. Wang
发明人： Mary M. Eshaghian-Wilner , Alexander Khitun , Kang L. Wang
IPC分类号： H01L43/00
CPC分类号： G11C11/54 , B82Y10/00 , G11C11/14 , H01L29/66984 , H03K19/168 , Y10S977/933
摘要： Nano-scale and multi-scale computational architectures using spin waves as a physical mechanism for device interconnection are provided. Solid-state spin-wave computing devices using nano-scale and multi-scale computational architectures comprised of a plurality of inputs and a plurality of outputs are described where such devices are configured to simultaneously transmit data elements from the inputs to the outputs by using spin-waves of differing frequencies. These devices include but are not limited to a spin-wave crossbar, a spin-wave reconfigurable mesh, a spin-wave fully-interconnected cluster, a hierarchical multi-scale spin-wave crossbar, a hierarchical multi-scale spin-wave reconfigurable mesh and a hierarchical multi-scale spin-wave fully-interconnected cluster.
摘要翻译：提供了使用自旋波作为器件互连的物理机制的纳米级和多尺度计算架构。描述了使用包括多个输入和多个输出的纳米尺度和多尺度计算体系结构的固态自旋波计算设备，其中这样的设备被配置为通过使用旋转从输入到输出同时发送数据元素不同频率的波。这些装置包括但不限于自旋波交叉开关，自旋波可重构网格，自旋波全互连簇，分层多尺度自旋波横截面，分级多尺度自旋波可重构网格以及分层多尺度自旋波全互联集群。

5. 发明授权

US5357119A Field effect devices having short period superlattice structures using Si and Ge 失效
标题翻译：具有使用Si和Ge的短周期超晶格结构的场效应器件
公开(公告)号：US5357119A
公开(公告)日：1994-10-18
申请号：US019719
申请日：1993-02-19
申请人： Kang L. Wang , Jin S. Park
发明人： Kang L. Wang , Jin S. Park
IPC分类号： H01L27/092 , H01L27/12
CPC分类号： H01L27/092
摘要： Carrier mobility in a heterojunction field effect device is increased by reducing or eliminating alloy scattering. The active channel region of the field effect device uses alternating layers of pure silicon and germanium which form a short period superlattice with the thickness of each layer in the superlattice being no greater than the critical thickness for maintaining a strained heterojunction. The gate contact of the field effect device can comprise quantum Si/Ge wires which provide quantum confinement in the growth plane, thereby allowing the field effect device to further improve the mobility by restricting phonon scattering. The structure can be used to improve device speed performance.
摘要翻译：通过减少或消除合金散射来增加异质结场效应器件中的载流子迁移率。场效应器件的有源沟道区域使用形成短周期超晶格的纯硅和锗的交替层，超晶格中每层的厚度不大于用于维持应变异质结的临界厚度。场效应器件的栅极接触可以包括在生长平面中提供量子限制的量子Si / Ge线，从而允许场效应器件通过限制声子散射来进一步提高迁移率。该结构可用于提高设备速度性能。

6. 发明授权

US09048329B2 Integrated circuit memory devices having vertical transistor arrays therein and methods of forming same 有权
标题翻译：具有垂直晶体管阵列的集成电路存储器件及其形成方法
公开(公告)号：US09048329B2
公开(公告)日：2015-06-02
申请号：US14024737
申请日：2013-09-12
申请人： Ji-Young Kim , Kang L. Wang , Yong-Jik Park , Jeong-Hee Han , Augustin Jinwoo Hong
发明人： Ji-Young Kim , Kang L. Wang , Yong-Jik Park , Jeong-Hee Han , Augustin Jinwoo Hong
IPC分类号： H01L29/792 , H01L27/115
CPC分类号： H01L29/7926 , H01L27/11575 , H01L27/11578 , H01L27/11582 , H01L29/792
摘要： An integrated circuit device includes a transistor array having a vertical stack of independently controllable gate electrodes therein. A first semiconductor channel region is provided, which extends on a first sidewall of the vertical stack of independently controllable gate electrodes. A first electrically insulating layer is also provided, which extends between the first semiconductor channel region and the first sidewall of the vertical stack of independently controllable gate electrodes. Source and drain regions are provided, which are electrically coupled to first and second ends of the first semiconductor channel region, respectively.
摘要翻译：集成电路器件包括其中具有可独立控制的栅电极的垂直堆叠的晶体管阵列。提供第一半导体沟道区，其在独立可控栅电极的垂直叠层的第一侧壁上延伸。还提供了第一电绝缘层，其在第一半导体沟道区域和独立可控栅电极的垂直叠层的第一侧壁之间延伸。源极和漏极区分别电耦合到第一半导体沟道区的第一和第二端。

7. 发明申请

US20120181593A1 Semiconductor Device 有权
标题翻译：半导体器件
公开(公告)号：US20120181593A1
公开(公告)日：2012-07-19
申请号：US13428706
申请日：2012-03-23
申请人： Ji-Young Kim , Kang L. Wang , Yong-Jik Park , Jeong-Hee Han , Augustin Jinwoo Hong
发明人： Ji-Young Kim , Kang L. Wang , Yong-Jik Park , Jeong-Hee Han , Augustin Jinwoo Hong
IPC分类号： H01L29/78
CPC分类号： H01L27/11578 , H01L21/8221 , H01L27/0688 , H01L27/11575 , H01L27/11582 , H01L29/66833 , H01L29/792 , H01L29/7926
摘要： Provided is a semiconductor device that can include a lower interconnection on a substrate and at least one upper interconnection disposed on the lower interconnection. At least one gate structure can be disposed between the upper interconnection and the lower interconnection, where the gate structure can include a plurality of gate lines that are vertically stacked so that each of the gate lines has a wiring portion that is substantially parallel to an upper surface of the substrate and a contact portion that extends from the wiring portion along a direction penetrating an upper surface of the substrate. At least one semiconductor pattern can connect the upper and lower interconnections.
摘要翻译：提供了一种半导体器件，其可以包括在衬底上的下互连和布置在下互连上的至少一个上互连。至少一个栅极结构可以设置在上部互连和下部互连之间，其中栅极结构可以包括垂直堆叠的多条栅极线，使得每个栅极线具有基本上平行于上部的布线部分所述基板的表面和从所述布线部沿着穿过所述基板的上表面的方向延伸的接触部。至少一个半导体图案可以连接上部和下部互连。

8. 发明申请

US20120028846A1 GAS SENSOR INCORPORATING A POROUS FRAMEWORK 有权
标题翻译：配有多孔框架的气体传感器
公开(公告)号：US20120028846A1
公开(公告)日：2012-02-02
申请号：US13142564
申请日：2009-12-29
申请人： Omar M. Yaghi , Alexander U. Czaja , Bo Wang , Hiroyasu Furukawa , Kosmas Galatsis , Kang L. Wang
发明人： Omar M. Yaghi , Alexander U. Czaja , Bo Wang , Hiroyasu Furukawa , Kosmas Galatsis , Kang L. Wang
IPC分类号： C40B60/12 , G01N30/96 , G01N33/00
CPC分类号： G01N33/50 , B01J20/226 , G01N27/125 , G01N33/004
摘要： The disclosure provides sensor for gas sensing including CO2 gas sensors comprising a porous framework sensing area for binding an analyte gas.
摘要翻译：本公开提供了用于气体感测的传感器，包括CO 2气体传感器，其包括用于结合分析物气体的多孔框架感测区

9. 发明授权

US07547932B2 Vertical gate-depleted single electron transistor 有权
标题翻译：垂直栅极耗尽的单电子晶体管
公开(公告)号：US07547932B2
公开(公告)日：2009-06-16
申请号：US10302635
申请日：2002-11-22
申请人： Yaohui Zhang , Filipp A. Baron , Kang L. Wang
发明人： Yaohui Zhang , Filipp A. Baron , Kang L. Wang
IPC分类号： H01L27/108
CPC分类号： B82Y10/00 , H01L29/7613 , H01L29/812
摘要： A vertical gate-depleted single electron transistor (SET) is fabricated on a conducting or insulating substrate. A plurality of lightly doped basic materials and tunneling barriers are fabricated on top of a substrate, wherein at least two of the layers of basic materials sandwich the layers of tunneling barriers and at least two of the layers of tunneling barriers sandwich at least one of the layers of basic materials. A mesa is fabricated on top of the layers of basic materials and tunneling barriers, and has an undercut shape. An ohmic contact is fabricated on top of the mesa, and one or more gate Schottky contacts are fabricated on top of the layers of lightly doped basic materials and tunneling barriers. A quantum dot is induced by gate depletion, when a source voltage is set as zero, a drain voltage is set to be less than 0.1, and a gate voltage is set to be negative. The depletion region expands toward the center of the device and forms a lateral confinement to the quantum well, wherein a quantum dot is obtained. Because the size of the quantum dot is so small, the Coulomb charging energy achieved is large enough to let the device operate at room temperature.
摘要翻译：在导电或绝缘基板上制造垂直栅极耗尽的单电子晶体管（SET）。在衬底的顶部上制造多个轻掺杂的基本材料和隧道势垒，其中至少两层基本材料层夹着隧道势垒的层，并且至少两层隧穿势垒夹着至少一层层的基本材料。在基础材料和隧道屏障层之上制造台面，并具有底切形状。在台面的顶部制造欧姆接触，并且在轻掺杂的基础材料和隧道势垒的层之上制造一个或多个栅极肖特基接触。当栅极耗尽时，源极电压被设置为零，漏极电压被设定为小于0.1，栅极电压被设定为负值，就会产生量子点。耗尽区朝向器件的中心扩展，并形成量子阱的侧向约束，其中获得量子点。因为量子点的尺寸如此之小，所以实现的库仑充电能够足够大以使器件在室温下工作。

10. 发明授权

US5023879A Optically pumped step quantum well IR source 失效
标题翻译：光泵浦步长量子阱IR源
公开(公告)号：US5023879A
公开(公告)日：1991-06-11
申请号：US514853
申请日：1990-04-26
申请人： Kang L. Wang , Perng-Fei Yuh
发明人： Kang L. Wang , Perng-Fei Yuh
IPC分类号： H01S5/04 , H01S5/30 , H01S5/343
CPC分类号： B82Y20/00 , H01S5/30 , H01S5/34313 , H01S5/041 , H01S5/3432
摘要： An optically pumped semiconductor laser comprises multiple asymmetric quantum well structures. Using the structures described herein, the selection rules for additional optical transitions can be made possible and three or four level lasers can be obtained. A population inversion can be achieved by optical pumping for lasing for those not allowed in a simple quantum well.
摘要翻译：光泵浦半导体激光器包括多个非对称量子阱结构。使用本文所述的结构，可以实现用于附加光学转换的选择规则，并且可以获得三个或四个等级的激光器。通过对于在简单量子阱中不允许的激光进行激光的光泵浦，可以实现种群反演。

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