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1. 发明授权

US4825278A Radiation hardened semiconductor devices 失效
标题翻译：辐射硬化半导体器件
公开(公告)号：US4825278A
公开(公告)日：1989-04-25
申请号：US20771
申请日：1987-03-02
申请人： Steven J. Hillenius , William T. Lynch , Lalita Manchanda
发明人： Steven J. Hillenius , William T. Lynch , Lalita Manchanda
IPC分类号： H01L21/765 , H01L23/58 , H01L23/60 , H01L29/06 , H01L29/40
CPC分类号： H01L29/402 , H01L21/765 , H01L23/585 , H01L23/60 , H01L2924/0002 , Y10S257/906
摘要： Disclosed are semiconductor devices and circuits which are highly resistant to the effects of radiation. A thin conductive layer, which is biased at substrate potential, and a thin oxide are provided under the usual field oxide of the devices. The conductive layer shields the semiconductor substrate from the effects of charge generation in the field oxide due to radiation absorption.
摘要翻译：公开了对辐射效应高度耐受的半导体器件和电路。在器件的通常的场氧化物下方设置偏置于衬底电位的薄导电层和薄氧化物。由于辐射吸收，导电层屏蔽半导体衬底免受场氧化物中的电荷产生的影响。

2. 发明授权

US5373180A Planar isolation technique for integrated circuits 失效
标题翻译：集成电路的平面隔离技术
公开(公告)号：US5373180A
公开(公告)日：1994-12-13
申请号：US121082
申请日：1993-09-14
申请人： Steven J. Hillenius , William T. Lynch , Lalita Manchanda , Mark R. Pinto , Sheila Vaidya
发明人： Steven J. Hillenius , William T. Lynch , Lalita Manchanda , Mark R. Pinto , Sheila Vaidya
IPC分类号： H01L29/73 , H01L21/331 , H01L21/76 , H01L21/762 , H01L21/763 , H01L29/78 , H01L27/04
CPC分类号： H01L21/76224 , H01L21/76205 , H01L21/763
摘要： Through the use of a specifically configured buried dielectric region, devices with strict design rules, e.g., design rules of 0.9 micrometers and less, are significantly improved. In particular, the recessed dielectric region, e.g., field oxide, separating device areas in an integrated circuit, either has a buried conducting shield surrounding the periphery of the oxide or has a configuration such that the upper surface of the dielectric is no more than 20 nm below the upper surface of the silicon forming the device active region. By insuring a suitable configuration, parasitic capacitance resulting in slower operation is considerably reduced while leakage currents are maintained at an acceptable level.
摘要翻译：通过使用特定配置的埋入介质区域，具有严格设计规则（例如0.9微米及更小的设计规则）的器件被显着改进。特别地，集成电路中的凹陷介质区域，例如场氧化物，分离器件区域，或者具有围绕氧化物周围的埋入导电屏蔽层，或具有这样的结构，使得电介质的上表面不超过20 在形成器件有源区的硅的上表面下方。通过确保合适的配置，导致较慢操作的寄生电容显着降低，而漏电流保持在可接受的水平。

3. 发明授权

US5063422A Devices having shallow junctions 失效
标题翻译：器件具有浅结
公开(公告)号：US5063422A
公开(公告)日：1991-11-05
申请号：US515550
申请日：1990-04-26
申请人： Steven J. Hillenius , Joseph Lebowitz , Ruichen Liu , William T. Lynch
发明人： Steven J. Hillenius , Joseph Lebowitz , Ruichen Liu , William T. Lynch
IPC分类号： H01L21/225 , H01L21/8238 , H01L27/092 , H01L29/08 , H01L29/36
CPC分类号： H01L29/0847 , H01L21/2257 , H01L21/823814 , H01L27/0921 , H01L29/36 , H01L27/0928
摘要： In CMOS based integrated circuits, stricter design rules require source and drain junctions shallower than 2500 .ANG.. By using a specific device configuration, a shallow junction is obtainable while resistance to latch-up is improved and other electrical properties, e.g., low leakage current, are maintained. To achieve this result the p-channel device should have an activation energy of the junction reverse leakage current region less than 1.12 eV, with a junction dopant region shallower than 1200 .ANG. and a monotonically decreasing junction dopant profile.
摘要翻译：在基于CMOS的集成电路中，更严格的设计规则要求源和漏接点比2500 ANGSTROM浅。通过使用特定的器件配置，可以获得浅结，同时提高了闩锁的阻力，并且保持了其他电特性，例如低漏电流。为了实现这一结果，p沟道器件应该具有小于1.12eV的结反向泄漏电流区域的激活能，其中掺杂剂区域比1200安培浅和单调递减的掺杂剂分布。

4. 发明授权

US5642014A Self-powered device 失效
标题翻译：自供电设备
公开(公告)号：US5642014A
公开(公告)日：1997-06-24
申请号：US534356
申请日：1995-09-27
申请人： Steven J. Hillenius
发明人： Steven J. Hillenius
IPC分类号： G21H1/06 , H01L21/822 , H01L27/04 , B01J19/00 , G21D7/00
CPC分类号： G21H1/06
摘要： The invention provides a self-powered device having at least one substrate, at least one radioactive power source formed over the substrate, and integrated circuits formed over the substrate. The radioactive power source includes a first active layer of a first conductivity type, a second active layer of a second conductivity type. The first and second active layers form a depletion layer. A tritium containing layer is provided which supplies beta particles that penetrates the depletion layer generating electron-hole pairs. The electron-hole pairs are swept by the electric field in the depletion layer producing an electric current.
摘要翻译：本发明提供了一种自供电装置，其具有至少一个基板，在基板上形成的至少一个放射源，以及形成在基板上的集成电路。放射性电源包括第一导电类型的第一有源层和第二导电类型的第二有源层。第一和第二活性层形成耗尽层。提供含氚层，其提供穿透耗尽层的β粒子，产生电子 - 空穴对。电子 - 空穴对被消耗层中的电场扫过，产生电流。

5. 发明授权

US4935376A Making silicide gate level runners 失效
标题翻译：制作硅化物浇口水平赛跑者
公开(公告)号：US4935376A
公开(公告)日：1990-06-19
申请号：US420207
申请日：1989-10-12
申请人： Steven J. Hillenius , Kuo-Hua Lee , Chih-Yuan Lu , Janmye Sung
发明人： Steven J. Hillenius , Kuo-Hua Lee , Chih-Yuan Lu , Janmye Sung
IPC分类号： H01L29/78 , H01L21/28 , H01L21/3205 , H01L21/336 , H01L21/768
CPC分类号： H01L21/76889 , H01L21/28052 , H01L21/28123
摘要： Integrated circuits are fabricated with thick self-aligned silicide runners on the field oxide by etching back the first dielectric to expose patterned polysilicon on the field oxide and then forming a silicide on the patterned polysilicon.

6. 发明授权

US4554726A CMOS Integrated circuit technology utilizing dual implantation of slow and fast diffusing donor ions to form the n-well 失效
标题翻译： CMOS集成电路技术，利用双重注入慢速和快速扩散的供体离子形成n阱
公开(公告)号：US4554726A
公开(公告)日：1985-11-26
申请号：US601353
申请日：1984-04-17
申请人： Steven J. Hillenius , Louis C. Parrillo
发明人： Steven J. Hillenius , Louis C. Parrillo
IPC分类号： H01L21/76 , H01L21/265 , H01L21/266 , H01L21/762 , H01L21/8234 , H01L21/8238 , H01L27/08 , H01L27/088 , H01L27/092 , H01L29/78 , H01L21/22
CPC分类号： H01L21/823892 , H01L21/76221 , H01L27/0928 , Y10S148/053 , Y10S148/07 , Y10S148/082 , Y10S148/117
摘要： To minimize the number of independent masking operations in the manufacture of a CMOS integrated circuit device using twin tub technology, the n-tub is made by separate phosphorus and arsenic implants through a common mask, and the p-tub is made by two separate boron implants through a common mask, complementary to that used for forming the n-tub. One of the boron implants occurs before, the other after, the drive-in heating step. After tub formation, further movement of the implanted ions is kept small by use of a high pressure process for growing the field oxide and by only limited further heating. Transistors are then formed in the tubs.
摘要翻译：为了最小化使用双桶技术的CMOS集成电路器件的制造中的独立掩蔽操作的数量，n型槽由通过共用掩模的分开的磷和砷植入物制成，并且p型桶由两个分开的硼制成植入物通过一个通用的面罩，与用于形成n型浴缸的补充剂相辅相成。其中一个硼植入物在之前发生，另一个之后，进入加热步骤。在桶形成之后，通过使用用于生长场氧化物的高压工艺和仅有限的进一步加热，注入离子的进一步运动保持较小。然后在桶中形成晶体管。

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