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1. 发明授权

US09048329B2 Integrated circuit memory devices having vertical transistor arrays therein and methods of forming same 有权
标题翻译：具有垂直晶体管阵列的集成电路存储器件及其形成方法
公开(公告)号：US09048329B2
公开(公告)日：2015-06-02
申请号：US14024737
申请日：2013-09-12
申请人： Ji-Young Kim , Kang L. Wang , Yong-Jik Park , Jeong-Hee Han , Augustin Jinwoo Hong
发明人： Ji-Young Kim , Kang L. Wang , Yong-Jik Park , Jeong-Hee Han , Augustin Jinwoo Hong
IPC分类号： H01L29/792 , H01L27/115
CPC分类号： H01L29/7926 , H01L27/11575 , H01L27/11578 , H01L27/11582 , H01L29/792
摘要： An integrated circuit device includes a transistor array having a vertical stack of independently controllable gate electrodes therein. A first semiconductor channel region is provided, which extends on a first sidewall of the vertical stack of independently controllable gate electrodes. A first electrically insulating layer is also provided, which extends between the first semiconductor channel region and the first sidewall of the vertical stack of independently controllable gate electrodes. Source and drain regions are provided, which are electrically coupled to first and second ends of the first semiconductor channel region, respectively.
摘要翻译：集成电路器件包括其中具有可独立控制的栅电极的垂直堆叠的晶体管阵列。提供第一半导体沟道区，其在独立可控栅电极的垂直叠层的第一侧壁上延伸。还提供了第一电绝缘层，其在第一半导体沟道区域和独立可控栅电极的垂直叠层的第一侧壁之间延伸。源极和漏极区分别电耦合到第一半导体沟道区的第一和第二端。

2. 发明申请

US20120181593A1 Semiconductor Device 有权
标题翻译：半导体器件
公开(公告)号：US20120181593A1
公开(公告)日：2012-07-19
申请号：US13428706
申请日：2012-03-23
申请人： Ji-Young Kim , Kang L. Wang , Yong-Jik Park , Jeong-Hee Han , Augustin Jinwoo Hong
发明人： Ji-Young Kim , Kang L. Wang , Yong-Jik Park , Jeong-Hee Han , Augustin Jinwoo Hong
IPC分类号： H01L29/78
CPC分类号： H01L27/11578 , H01L21/8221 , H01L27/0688 , H01L27/11575 , H01L27/11582 , H01L29/66833 , H01L29/792 , H01L29/7926
摘要： Provided is a semiconductor device that can include a lower interconnection on a substrate and at least one upper interconnection disposed on the lower interconnection. At least one gate structure can be disposed between the upper interconnection and the lower interconnection, where the gate structure can include a plurality of gate lines that are vertically stacked so that each of the gate lines has a wiring portion that is substantially parallel to an upper surface of the substrate and a contact portion that extends from the wiring portion along a direction penetrating an upper surface of the substrate. At least one semiconductor pattern can connect the upper and lower interconnections.
摘要翻译：提供了一种半导体器件，其可以包括在衬底上的下互连和布置在下互连上的至少一个上互连。至少一个栅极结构可以设置在上部互连和下部互连之间，其中栅极结构可以包括垂直堆叠的多条栅极线，使得每个栅极线具有基本上平行于上部的布线部分所述基板的表面和从所述布线部沿着穿过所述基板的上表面的方向延伸的接触部。至少一个半导体图案可以连接上部和下部互连。

3. 发明申请

US20120028846A1 GAS SENSOR INCORPORATING A POROUS FRAMEWORK 有权
标题翻译：配有多孔框架的气体传感器
公开(公告)号：US20120028846A1
公开(公告)日：2012-02-02
申请号：US13142564
申请日：2009-12-29
申请人： Omar M. Yaghi , Alexander U. Czaja , Bo Wang , Hiroyasu Furukawa , Kosmas Galatsis , Kang L. Wang
发明人： Omar M. Yaghi , Alexander U. Czaja , Bo Wang , Hiroyasu Furukawa , Kosmas Galatsis , Kang L. Wang
IPC分类号： C40B60/12 , G01N30/96 , G01N33/00
CPC分类号： G01N33/50 , B01J20/226 , G01N27/125 , G01N33/004
摘要： The disclosure provides sensor for gas sensing including CO2 gas sensors comprising a porous framework sensing area for binding an analyte gas.
摘要翻译：本公开提供了用于气体感测的传感器，包括CO 2气体传感器，其包括用于结合分析物气体的多孔框架感测区

4. 发明授权

US07547932B2 Vertical gate-depleted single electron transistor 有权
标题翻译：垂直栅极耗尽的单电子晶体管
公开(公告)号：US07547932B2
公开(公告)日：2009-06-16
申请号：US10302635
申请日：2002-11-22
申请人： Yaohui Zhang , Filipp A. Baron , Kang L. Wang
发明人： Yaohui Zhang , Filipp A. Baron , Kang L. Wang
IPC分类号： H01L27/108
CPC分类号： B82Y10/00 , H01L29/7613 , H01L29/812
摘要： A vertical gate-depleted single electron transistor (SET) is fabricated on a conducting or insulating substrate. A plurality of lightly doped basic materials and tunneling barriers are fabricated on top of a substrate, wherein at least two of the layers of basic materials sandwich the layers of tunneling barriers and at least two of the layers of tunneling barriers sandwich at least one of the layers of basic materials. A mesa is fabricated on top of the layers of basic materials and tunneling barriers, and has an undercut shape. An ohmic contact is fabricated on top of the mesa, and one or more gate Schottky contacts are fabricated on top of the layers of lightly doped basic materials and tunneling barriers. A quantum dot is induced by gate depletion, when a source voltage is set as zero, a drain voltage is set to be less than 0.1, and a gate voltage is set to be negative. The depletion region expands toward the center of the device and forms a lateral confinement to the quantum well, wherein a quantum dot is obtained. Because the size of the quantum dot is so small, the Coulomb charging energy achieved is large enough to let the device operate at room temperature.
摘要翻译：在导电或绝缘基板上制造垂直栅极耗尽的单电子晶体管（SET）。在衬底的顶部上制造多个轻掺杂的基本材料和隧道势垒，其中至少两层基本材料层夹着隧道势垒的层，并且至少两层隧穿势垒夹着至少一层层的基本材料。在基础材料和隧道屏障层之上制造台面，并具有底切形状。在台面的顶部制造欧姆接触，并且在轻掺杂的基础材料和隧道势垒的层之上制造一个或多个栅极肖特基接触。当栅极耗尽时，源极电压被设置为零，漏极电压被设定为小于0.1，栅极电压被设定为负值，就会产生量子点。耗尽区朝向器件的中心扩展，并形成量子阱的侧向约束，其中获得量子点。因为量子点的尺寸如此之小，所以实现的库仑充电能够足够大以使器件在室温下工作。

5. 发明授权

US5023879A Optically pumped step quantum well IR source 失效
标题翻译：光泵浦步长量子阱IR源
公开(公告)号：US5023879A
公开(公告)日：1991-06-11
申请号：US514853
申请日：1990-04-26
申请人： Kang L. Wang , Perng-Fei Yuh
发明人： Kang L. Wang , Perng-Fei Yuh
IPC分类号： H01S5/04 , H01S5/30 , H01S5/343
CPC分类号： B82Y20/00 , H01S5/30 , H01S5/34313 , H01S5/041 , H01S5/3432
摘要： An optically pumped semiconductor laser comprises multiple asymmetric quantum well structures. Using the structures described herein, the selection rules for additional optical transitions can be made possible and three or four level lasers can be obtained. A population inversion can be achieved by optical pumping for lasing for those not allowed in a simple quantum well.
摘要翻译：光泵浦半导体激光器包括多个非对称量子阱结构。使用本文所述的结构，可以实现用于附加光学转换的选择规则，并且可以获得三个或四个等级的激光器。通过对于在简单量子阱中不允许的激光进行激光的光泵浦，可以实现种群反演。

6. 发明申请

US20110018051A1 Integrated Circuit Memory Devices Having Vertical Transistor Arrays Therein and Methods of Forming Same 有权
标题翻译：具有垂直晶体管阵列的集成电路存储器件及其形成方法相同
公开(公告)号：US20110018051A1
公开(公告)日：2011-01-27
申请号：US12816771
申请日：2010-06-16
申请人： Ji-Young Kim , Kang L. Wang , Yong-Jik Park , Jeong-Hee Han , Augustin Jinwoo Hong
发明人： Ji-Young Kim , Kang L. Wang , Yong-Jik Park , Jeong-Hee Han , Augustin Jinwoo Hong
IPC分类号： H01L27/115
CPC分类号： H01L29/7926 , H01L27/11575 , H01L27/11578 , H01L27/11582 , H01L29/792
摘要： An integrated circuit device includes a transistor array having a vertical stack of independently controllable gate electrodes therein. A first semiconductor channel region is provided, which extends on a first sidewall of the vertical stack of independently controllable gate electrodes. A first electrically insulating layer is also provided, which extends between the first semiconductor channel region and the first sidewall of the vertical stack of independently controllable gate electrodes. Source and drain regions are provided, which are electrically coupled to first and second ends of the first semiconductor channel region, respectively.
摘要翻译：集成电路器件包括其中具有可独立控制的栅电极的垂直堆叠的晶体管阵列。提供第一半导体沟道区，其在独立可控栅电极的垂直叠层的第一侧壁上延伸。还提供了第一电绝缘层，其在第一半导体沟道区域和独立可控栅电极的垂直叠层的第一侧壁之间延伸。源极和漏极区分别电耦合到第一半导体沟道区的第一和第二端。

7. 发明申请

US20100308391A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20100308391A1
公开(公告)日：2010-12-09
申请号：US12481403
申请日：2009-06-09
申请人： Ji-Young Kim , Kang L. Wang , Yong-Jik Park , Jeong-Hee Han , Augustin Jinwoo Hong
发明人： Ji-Young Kim , Kang L. Wang , Yong-Jik Park , Jeong-Hee Han , Augustin Jinwoo Hong
IPC分类号： H01L29/792
CPC分类号： H01L27/11578 , H01L21/8221 , H01L27/0688 , H01L27/11575 , H01L27/11582 , H01L29/66833 , H01L29/792 , H01L29/7926
摘要： Provided are a semiconductor device and a method of fabricating the same. At least one mold structure defining at least one first opening is formed on a substrate, wherein the mold structure comprises first mold patterns and second mold patterns that are sequentially and alternatingly stacked. Thereafter, side surfaces of the first mold patterns are selectively etched to form undercut regions between the second mold patterns. Then, a semiconductor layer is formed to cover a surface of the mold structure where the undercut regions are formed, and gate patterns are formed, which fill respective undercut regions where the semiconductor layer is formed.
摘要翻译：提供半导体器件及其制造方法。在衬底上形成限定至少一个第一开口的至少一个模具结构，其中模具结构包括顺序地和交替地堆叠的第一模具图案和第二模具图案。此后，选择性地蚀刻第一模具图案的侧表面以在第二模具图案之间形成底切区域。然后，形成半导体层以覆盖形成底切区域的模具结构的表面，形成栅极图案，填充形成半导体层的各个底切区域。

8. 发明申请

US20090127543A1 VERTICAL GATE-DEPLETED SINGLE ELECTRON TRANSISTOR 有权
标题翻译：垂直门式单电子晶体管
公开(公告)号：US20090127543A1
公开(公告)日：2009-05-21
申请号：US10302635
申请日：2002-11-22
申请人： Yaohui Zhang , Filipp A. Baron , Kang L. Wang
发明人： Yaohui Zhang , Filipp A. Baron , Kang L. Wang
IPC分类号： H01L29/66 , H01L21/20
CPC分类号： B82Y10/00 , H01L29/7613 , H01L29/812
摘要： A vertical gate-depleted single electron transistor (SET) is fabricated on a conducting or insulating substrate. A plurality of lightly doped basic materials and tunneling barriers are fabricated on top of a substrate, wherein at least two of the layers of basic materials sandwich the layers of tunneling barriers and at least two of the layers of tunneling barriers sandwich at least one of the layers of basic materials. A mesa is fabricated on top of the layers of basic materials and tunneling barriers, and has an undercut shape. An ohmic contact is fabricated on top of the mesa, and one or more gate Schottky contacts are fabricated on top of the layers of lightly doped basic materials and tunneling barriers. A quantum dot is induced by gate depletion, when a source voltage is set as zero, a drain voltage is set to be less than 0.1, and a gate voltage is set to be negative. The depletion region expands toward the center of the device and forms a lateral confinement to the quantum well, wherein a quantum dot is obtained. Because the size of the quantum dot is so small, the Coulomb charging energy achieved is large enough to let the device operate at room temperature.
摘要翻译：在导电或绝缘基板上制造垂直栅极耗尽的单电子晶体管（SET）。在衬底的顶部上制造多个轻掺杂的基本材料和隧道势垒，其中至少两层基本材料层夹着隧道势垒的层，并且至少两层隧穿势垒夹着至少一层层的基本材料。在基础材料和隧道屏障层之上制造台面，并具有底切形状。在台面的顶部制造欧姆接触，并且在轻掺杂的基础材料和隧道势垒的层之上制造一个或多个栅极肖特基接触。当栅极耗尽时，源极电压被设置为零，漏极电压被设定为小于0.1，栅极电压被设定为负值，就会产生量子点。耗尽区朝向器件的中心扩展，并形成量子阱的侧向约束，其中获得量子点。因为量子点的尺寸如此之小，所以实现的库仑充电能够足够大以使器件在室温下工作。

9. 发明授权

US07528456B1 Nano-scale computational architectures with spin wave bus 有权
标题翻译：具有自旋波总线的纳米级计算架构
公开(公告)号：US07528456B1
公开(公告)日：2009-05-05
申请号：US11365794
申请日：2006-03-01
申请人： Alexander Khitun , Roman P. Ostroumov , Kang L. Wang
发明人： Alexander Khitun , Roman P. Ostroumov , Kang L. Wang
IPC分类号： H01L45/02
CPC分类号： H03K19/18 , Y10S977/933
摘要： New kinds of nano-scale computational architectures using spin waves as a physical mechanism for device interconnection are described. A method for operating a logic device having a spin wave bus includes the step of receiving an input signal representing information. A spin wave is excited with the information coded in an aspect of the spin wave in response to receiving the input signal. The spin wave is propagated through a spin wave bus having an associated polarization. The information associated with the spin wave is determined in response to propagating the spin wave through the spin wave bus.
摘要翻译：描述了使用自旋波作为器件互连的物理机制的新型纳米级计算架构。一种用于操作具有自旋波母线的逻辑器件的方法包括接收表示信息的输入信号的步骤。响应于接收输入信号，在自旋波的方面编码的信息激发自旋波。自旋波通过具有相关偏振的自旋波母线传播。响应于通过自旋波母线传播自旋波而确定与自旋波相关联的信息。

10. 发明授权

US07427754B2 Telegraph signal microscopy device and method 有权
标题翻译：电报信号显微镜装置及方法
公开(公告)号：US07427754B2
公开(公告)日：2008-09-23
申请号：US11279540
申请日：2006-04-12
申请人： Kang L. Wang , Fei Liu
发明人： Kang L. Wang , Fei Liu
IPC分类号： G01N23/00
CPC分类号： G01Q60/48 , G01Q70/12 , Y10S977/84 , Y10S977/849 , Y10S977/86 , Y10S977/875 , Y10S977/876
摘要： A microscope device includes a probe having a dielectric material with a first side and a second side. First and second electrodes are disposed on the first side of the dielectric material. A nanotube connects the first and second electrodes. A gate electrode is disposed on the second side (e.g., backside) of the dielectric material. The device includes a stage adapted for holding a sample. The stage and probe are moveable with respect to one another such that the sample can be brought in close proximity to the nanotube. The device further includes current measurement circuitry for measuring current (e.g., Random Telegraph Signals) passing through the nanotube. The microscope device is able to identify and characterize single defects on the molecular or atomic scale. The probe device may be combined with spin resonance and/or optical systems such that the detection/mapping/manipulate of single spin and single photon could be achieved.
摘要翻译：显微镜装置包括具有第一侧和第二侧的电介质材料的探针。第一和第二电极设置在电介质材料的第一侧上。纳米管连接第一和第二电极。栅电极设置在电介质材料的第二侧（例如背面）上。该装置包括适于容纳样品的台。阶段和探针可以相对于彼此移动，使得样品可以靠近纳米管。该装置还包括用于测量通过纳米管的电流（例如，随机电报信号）的电流测量电路。显微镜装置能够识别和表征分子或原子尺度上的单个缺陷。探针装置可以与自旋共振和/或光学系统组合，使得可以实现单个旋转和单个光子的检测/映射/操纵。

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