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1. 发明授权

US07098676B2 Multi-functional structure for enhanced chip manufacturibility and reliability for low k dielectrics semiconductors and a crackstop integrity screen and monitor 失效
标题翻译：多功能结构，用于增强低k电介质半导体的芯片制造和可靠性，以及裂纹完整性屏幕和监视器
公开(公告)号：US07098676B2
公开(公告)日：2006-08-29
申请号：US10338931
申请日：2003-01-08
申请人： William F. Landers , Thomas M. Shaw , Diana Llera-Hurlburt , Scott W. Crowder , Vincent J. McGahay , Sandra G. Malhotra , Charles R. Davis , Ronald D. Goldblatt , Brett H. Engel
发明人： William F. Landers , Thomas M. Shaw , Diana Llera-Hurlburt , Scott W. Crowder , Vincent J. McGahay , Sandra G. Malhotra , Charles R. Davis , Ronald D. Goldblatt , Brett H. Engel
IPC分类号： G01R27/08 , G01R31/26 , H01L31/07 , H01L23/58
CPC分类号： H01L23/585 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： An on-chip redundant crack termination barrier structure, or crackstop, provides a barrier for preventing defects, cracks, delaminations, and moisture/oxidation contaminants from reaching active circuit regions. Conductive materials in the barrier structure design permits wiring the barriers out to contact pads and device pins for coupling a monitor device to the chip for monitoring barrier integrity.
摘要翻译：片上冗余裂纹终止阻挡结构或裂缝挡板为防止缺陷，裂纹，脱层和水分/氧化污染物到达有源电路区域提供了屏障。阻挡结构设计中的导电材料允许将屏障布线到接触垫和器件引脚上，用于将监测器件耦合到芯片以监测屏障完整性。

2. 发明授权

US06395164B1 Copper seed layer repair technique using electroless touch-up 失效
标题翻译：铜种子层修复技术采用化学镀
公开(公告)号：US06395164B1
公开(公告)日：2002-05-28
申请号：US09414224
申请日：1999-10-07
申请人： Panayotis Andricacos , James E. Fluegel , John G. Gaudiello , Ronald D. Goldblatt , Sandra G. Malhotra , Milan Paunovic
发明人： Panayotis Andricacos , James E. Fluegel , John G. Gaudiello , Ronald D. Goldblatt , Sandra G. Malhotra , Milan Paunovic
IPC分类号： C25D712
CPC分类号： H01L21/76868 , C23C18/161 , C23C18/1653 , C25D7/123 , H01L21/288 , H01L21/76843 , H01L21/76873
摘要： An electroless touch-up process for repairing copper metallization deposited in dual damascene structures with high aspect ratios. An initial copper strike layer is produced by directional deposition techniques such that discontinuous sidewall coverage occurs. An evolutionary electroless touch-up process then proceeds to conformally grow the copper layer on all surfaces. The result of the evolutionary process is to produce a continuous copper strike layer that can be used with conventional electroplating techniques.
摘要翻译：用于修复沉积在具有高纵横比的双镶嵌结构中的铜金属化的无电镀修补方法。通过定向沉积技术产生初始铜击穿层，从而发生不连续的侧壁覆盖。然后进行进化的无电触摸处理以在所有表面上保形地生长铜层。进化过程的结果是产生可与常规电镀技术一起使用的连续铜击穿层。

3. 发明申请

US20140080282A1 Leakage reduction in DRAM MIM capacitors 有权
公开(公告)号：US20140080282A1
公开(公告)日：2014-03-20
申请号：US13621910
申请日：2012-09-18
申请人： Tony P. Chiang , Wim Y. Deweerd , Sandra G. Malhotra
发明人： Tony P. Chiang , Wim Y. Deweerd , Sandra G. Malhotra
IPC分类号： H01L21/02
CPC分类号： H01L29/92 , H01L27/10852 , H01L28/40
摘要： A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high-k phase of a subsequently deposited dielectric layer. The high-k dielectric layer includes a doped material that can be crystallized after a subsequent annealing treatment. An amorphous blocking is formed on the dielectric layer. The thickness of the blocking layer is chosen such that the blocking layer remains amorphous after a subsequent annealing treatment. A second electrode layer compatible with the blocking layer is formed on the blocking layer.

4. 发明授权

US08193090B2 Formation of a masking layer on a dielectric region to facilitate formation of a capping layer on electrically conductive regions separated by the dielectric region 有权
标题翻译：在电介质区域上形成掩模层，以便在由电介质区域分隔的导电区域上形成覆盖层
公开(公告)号：US08193090B2
公开(公告)日：2012-06-05
申请号：US13192777
申请日：2011-07-28
申请人： David E. Lazovsky , Sandra G. Malhotra , Thomas R. Boussie
发明人： David E. Lazovsky , Sandra G. Malhotra , Thomas R. Boussie
IPC分类号： H01L21/44
CPC分类号： H01L21/7685 , B82Y30/00 , H01L21/02118 , H01L21/02167 , H01L21/0217 , H01L21/02203 , H01L21/288 , H01L21/31 , H01L21/76834
摘要： A masking layer is formed on a dielectric region of an electronic device so that, during subsequent formation of a capping layer on electrically conductive regions of the electronic device that are separated by the dielectric region, the masking layer inhibits formation of capping layer material on or in the dielectric region. The capping layer can be formed selectively on the electrically conductive regions or non-selectively; in either case (particularly in the latter), capping layer material formed over the dielectric region can subsequently be removed, thus ensuring that capping layer material is formed only on the electrically conductive regions. Silane-based materials, such as silane-based SAMs, can be used to form the masking layer. The capping layer can be formed of an electrically conductive material (e.g., a cobalt alloy, a nickel alloy, tungsten, tantalum, tantalum nitride), a semiconductor material, or an electrically insulative material, and can be formed using any appropriate process, including conventional deposition processes such as electroless deposition, chemical vapor deposition, physical vapor deposition or atomic layer deposition.
摘要翻译：在电子器件的电介质区域上形成掩模层，使得在随后在由电介质区域分离的电子器件的导电区域上形成覆盖层时，掩模层阻止在其上形成覆盖层材料在电介质区域。可以选择性地在导电区域或非选择性地形成覆盖层; 在任一情况下（特别是在后者中），可以随后去除在电介质区域上形成的覆盖层材料，从而确保覆盖层材料仅在导电区域上形成。可以使用诸如硅烷基SAM之类的硅烷基材料来形成掩模层。覆盖层可以由导电材料（例如，钴合金，镍合金，钨，钽，氮化钽），半导体材料或电绝缘材料形成，并且可以使用任何适当的工艺形成，包括常规沉积工艺如无电沉积，化学气相沉积，物理气相沉积或原子层沉积。

5. 发明申请

US20090014878A1 STRUCTURE AND METHOD OF FORMING ELECTRODEPOSITED CONTACTS 有权
标题翻译：形成电沉积联系的结构和方法
公开(公告)号：US20090014878A1
公开(公告)日：2009-01-15
申请号：US12130381
申请日：2008-05-30
申请人： Cyril Cabral, JR. , Hariklia Deligianni , Randolph F. Knarr , Sandra G. Malhotra , Stephen Rossnagel , Xiaoyan Shao , Anna Topol , Philippe M. Vereecken
发明人： Cyril Cabral, JR. , Hariklia Deligianni , Randolph F. Knarr , Sandra G. Malhotra , Stephen Rossnagel , Xiaoyan Shao , Anna Topol , Philippe M. Vereecken
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L23/485 , H01L21/2885 , H01L21/76843 , H01L21/76846 , H01L21/76877 , H01L23/53252 , H01L2924/0002 , H01L2924/00
摘要： A contact metallurgy structure comprising a patterned dielectric layer having cavities on a substrate; a silicide or germanide layer such as of cobalt and/or nickel located at the bottom of cavities; a contact layer comprising Ti or Ti/TiN located on top of the dielectric layer and inside the cavities and making contact to the silicide or germanide layer on the bottom; a diffusion barrier layer located on top of the contact layer and inside the cavities; optionally a seed layer for plating located on top of the barrier layer; a metal fill layer in vias is provided along with a method of fabrication. The metal fill layer is electrodeposited with at least one member selected from the group consisting of copper, rhodium, ruthenium, iridium, molybdenum, gold, silver, nickel, cobalt, silver, gold, cadmium and zinc and alloys thereof. When the metal fill layer is rhodium, ruthenium, or iridium, an effective diffusion barrier layer is not required between the fill metal and the dielectric. When the barrier layer is platable, such as ruthenium, rhodium, platinum, or iridium, the seed layer is not required.
摘要翻译：一种接触式冶金结构，包括在基底上具有空腔的图案化电介质层; 位于空腔底部的硅化物或锗化物层，例如钴和/或镍; 接触层，其包含位于介电层顶部并且在空腔内并与底部的硅化物或锗化物层接触的Ti或Ti / TiN; 位于所述接触层顶部和所述空腔内的扩散阻挡层; 可选地，位于阻挡层顶部的用于电镀的种子层; 提供通孔中的金属填充层以及制造方法。金属填充层用选自铜，铑，钌，铱，钼，金，银，镍，钴，银，金，镉和锌中的至少一种电池和其合金电沉积。当金属填充层是铑，钌或铱时，在填充金属和电介质之间不需要有效的扩散阻挡层。当阻挡层是可镀的，例如钌，铑，铂或铱时，不需要种子层。

6. 发明申请

US20080278990A1 RESISTIVE-SWITCHING NONVOLATILE MEMORY ELEMENTS 有权
标题翻译：电阻开关非易失性存储器元件
公开(公告)号：US20080278990A1
公开(公告)日：2008-11-13
申请号：US12114667
申请日：2008-05-02
申请人： Pragati Kumar , Sandra G. Malhotra , Sean Barstow , Tony Chiang
发明人： Pragati Kumar , Sandra G. Malhotra , Sean Barstow , Tony Chiang
IPC分类号： G11C11/00 , H01L21/16
CPC分类号： H01L45/1253 , G11C13/0007 , G11C13/003 , G11C2213/32 , G11C2213/51 , G11C2213/52 , G11C2213/56 , G11C2213/71 , G11C2213/72 , G11C2213/74 , G11C2213/76 , G11C2213/79 , H01L27/2409 , H01L27/2463 , H01L29/861 , H01L45/04 , H01L45/1233 , H01L45/145 , H01L45/146 , H01L45/1608 , H01L45/165
摘要： Nonvolatile memory elements are provided that have resistive switching metal oxides. The nonvolatile memory elements may be formed in one or more layers on an integrated circuit. Each memory element may have a first conductive layer, a metal oxide layer, and a second conductive layer. Electrical devices such as diodes may be coupled in series with the memory elements. The first conductive layer may be formed from a metal nitride. The metal oxide layer may contain the same metal as the first conductive layer. The metal oxide may form an ohmic contact or a Schottky contact with the first conductive layer. The second conductive layer may form an ohmic contact or a Schottky contact with the metal oxide layer. The first conductive layer, the metal oxide layer, and the second conductive layer may include sublayers. The second conductive layer may include an adhesion or barrier layer and a workfunction control layer.
摘要翻译：提供具有电阻开关金属氧化物的非易失性存储元件。非易失性存储元件可以形成在集成电路上的一个或多个层中。每个存储元件可以具有第一导电层，金属氧化物层和第二导电层。诸如二极管的电气设备可以与存储器元件串联耦合。第一导电层可以由金属氮化物形成。金属氧化物层可以包含与第一导电层相同的金属。金属氧化物可以与第一导电层形成欧姆接触或肖特基接触。第二导电层可以与金属氧化物层形成欧姆接触或肖特基接触。第一导电层，金属氧化物层和第二导电层可以包括子层。第二导电层可以包括粘合或阻挡层和功函数控制层。

7. 发明授权

US07064064B2 Copper recess process with application to selective capping and electroless plating 有权
标题翻译：铜凹槽工艺，适用于选择性封盖和无电镀
公开(公告)号：US07064064B2
公开(公告)日：2006-06-20
申请号：US11058783
申请日：2005-02-16
申请人： Shyng-Tsong Chen , Timothy J. Dalton , Kenneth M. Davis , Chao-Kun Hu , Fen F. Jamin , Steffen K. Kaldor , Mahadevaiyer Krishnan , Kaushik Kumar , Michael F. Lofaro , Sandra G. Malhotra , Chandrasekhar Narayan , David L. Rath , Judith M. Rubino , Katherine L. Saenger , Andrew H. Simon , Sean P. E. Smith , Wei-tsu Tseng
发明人： Shyng-Tsong Chen , Timothy J. Dalton , Kenneth M. Davis , Chao-Kun Hu , Fen F. Jamin , Steffen K. Kaldor , Mahadevaiyer Krishnan , Kaushik Kumar , Michael F. Lofaro , Sandra G. Malhotra , Chandrasekhar Narayan , David L. Rath , Judith M. Rubino , Katherine L. Saenger , Andrew H. Simon , Sean P. E. Smith , Wei-tsu Tseng
IPC分类号： H01L21/44
CPC分类号： H01L21/76849 , H01L21/76834 , H01L21/76847 , H01L21/76883 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit structure is disclosed that has a layer of logical and functional devices and an interconnection layer above the layer of logical and functional devices. The interconnection layer has a substrate, conductive features within the substrate and caps positioned only above the conductive features.
摘要翻译：公开了一种集成电路结构，其具有逻辑和功能器件层以及逻辑和功能器件层之上的互连层。互连层具有衬底，衬底内的导电特征和仅位于导电特征之上的盖。

8. 发明授权

US06924223B2 Method of forming a metal layer using an intermittent precursor gas flow process 有权
标题翻译：使用间歇性前体气体流动方法形成金属层的方法
公开(公告)号：US06924223B2
公开(公告)日：2005-08-02
申请号：US10673646
申请日：2003-09-30
申请人： Hideaki Yamasaki , Tsukasa Matsuda , Atsushi Gomi , Tatsuo Hatano , Mitsuhiro Tachibana , Koumei Matsuzava , Yumiko Kawano , Gert J Leusink , Fenton R McFeely , Sandra G. Malhotra , Andrew H Simon , John J Yurkas
发明人： Hideaki Yamasaki , Tsukasa Matsuda , Atsushi Gomi , Tatsuo Hatano , Mitsuhiro Tachibana , Koumei Matsuzava , Yumiko Kawano , Gert J Leusink , Fenton R McFeely , Sandra G. Malhotra , Andrew H Simon , John J Yurkas
IPC分类号： C23C16/04 , C23C16/16 , C23C16/44 , C23C16/455 , H01L21/285 , H01L21/768 , H01L21/44
CPC分类号： C23C16/45523 , C23C16/045 , C23C16/16 , C23C16/4408 , H01L21/28556 , H01L21/76843 , H01L21/76876 , H01L21/76877
摘要： A method is provided for forming a metal layer on a substrate using an intermittent precursor gas flow process. The method includes exposing the substrate to a reducing gas while exposing the substrate to pulses of a metal-carbonyl precursor gas. The process is carried out until a metal layer with desired thickness is formed on the substrate. The metal layer can be formed on a substrate, or alternately, the metal layer can be formed on a metal nucleation layer.
摘要翻译：提供了一种使用间歇式前体气体流动方法在基板上形成金属层的方法。该方法包括将衬底暴露于还原气体，同时将衬底暴露于羰基金属前体气体的脉冲。进行该过程，直到在基底上形成具有所需厚度的金属层。金属层可以形成在基板上，或者可以在金属成核层上形成金属层。

9. 发明授权

US6090722A Process for fabricating a semiconductor structure having a self-aligned spacer 有权
标题翻译：具有自对准间隔物的半导体结构的制造方法
公开(公告)号：US6090722A
公开(公告)日：2000-07-18
申请号：US225595
申请日：1999-01-06
申请人： Michael Armacost , Sandra G. Malhotra , Tina Wagner , Richard Wise
发明人： Michael Armacost , Sandra G. Malhotra , Tina Wagner , Richard Wise
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/311 , H01L21/336 , H01L21/60 , H01L29/78 , H01L21/469
CPC分类号： H01L21/76829 , H01L21/31116 , H01L21/76804 , H01L21/76897 , H01L2924/0002
摘要： A self-aligned dielectric spacer is etched by providing capped gate structure along a second layer of dielectric material located above the gate cap material. Dopant material at an increased doping level is provided in the second layer of dielectric material where the self-aligned spacer is to be located. The second layer of dielectric material is then etched selective to the dopant to define the self-aligned dielectric spacer.
摘要翻译：通过沿位于栅极帽材料上方的第二介电材料层提供封盖栅极结构来蚀刻自对准电介质间隔物。增加掺杂浓度的掺杂剂材料被提供在第二绝缘材料层中，其中定位的自对准间隔物。然后将第二层电介质材料选择性地蚀刻到掺杂剂以限定自对准电介质间隔物。

10. 发明授权

US08367463B2 Methods for forming resistive-switching metal oxides for nonvolatile memory elements 有权
标题翻译：用于形成用于非易失性存储元件的电阻式开关金属氧化物的方法
公开(公告)号：US08367463B2
公开(公告)日：2013-02-05
申请号：US13111230
申请日：2011-05-19
申请人： Pragati Kumar , Sandra G. Malhotra , Sean Barstow , Tony Chiang
发明人： Pragati Kumar , Sandra G. Malhotra , Sean Barstow , Tony Chiang
IPC分类号： H01L21/00 , H01L21/16 , H01L21/20 , H01L21/36
CPC分类号： H01L45/1625 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1641
摘要： Nonvolatile memory elements are provided that have resistive switching metal oxides. The nonvolatile memory elements may be formed from resistive-switching metal oxide layers. Metal oxide layers may be formed using sputter deposition at relatively low sputtering powers, relatively low duty cycles, and relatively high sputtering gas pressures. Dopants may be incorporated into a base oxide layer at an atomic concentration that is less than the solubility limit of the dopant in the base oxide. At least one oxidation state of the metal in the base oxide is preferably different than at least one oxidation sate of the dopant. The ionic radius of the dopant and the ionic radius of the metal may be selected to be close to each other. Annealing and oxidation operations may be performed on the resistive switching metal oxides. Bistable metal oxides with relatively large resistivities and large high-state-to-low state resistivity ratios may be produced.
摘要翻译：提供具有电阻开关金属氧化物的非易失性存储元件。非易失性存储元件可以由电阻式开关金属氧化物层形成。金属氧化物层可以使用相对低的溅射功率，相对低的占空比和较高的溅射气体压力的溅射沉积形成。掺杂剂可以以小于基底氧化物中的掺杂剂的溶解度极限的原子浓度结合到基底氧化物层中。基底氧化物中金属的至少一种氧化态优选不同于掺杂剂的至少一种氧化态。可以选择掺杂剂的离子半径和金属的离子半径彼此接近。可以对电阻式开关金属氧化物进行退火和氧化操作。可以制造具有相对较大的电阻率和大的高 - 低 - 电阻率比的双稳态金属氧化物。

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