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1. 发明申请

US20180331922A1 METHODS AND SYSTEMS FOR TIME-BASED BINNING OF NETWORK TRAFFIC 审中-公开
公开(公告)号：US20180331922A1
公开(公告)日：2018-11-15
申请号：US15593768
申请日：2017-05-12
申请人： Pragati Kumar Dhingra , Priyanka Bhaskar , Sucheta Dahiya , Devang Sethi , Mohit Gupta
发明人： Pragati Kumar Dhingra , Priyanka Bhaskar , Sucheta Dahiya , Devang Sethi , Mohit Gupta
IPC分类号： H04L12/26 , G06F3/06
CPC分类号： G06F3/067 , H04L43/026 , H04L43/062 , H04L47/30
摘要： In various embodiments, network-traffic records overlapping multiple binning windows are prorated such that partial records are stored in each binning window of overlap. In addition, the full, non-prorated record is stored in at least one of the binning windows.

2. 发明授权

US08828821B2 Fabrication of semiconductor stacks with ruthenium-based materials 有权
标题翻译：用钌基材料制造半导体叠层
公开(公告)号：US08828821B2
公开(公告)日：2014-09-09
申请号：US13395071
申请日：2009-09-18
申请人： Hanhong Chen , Nobumichi Fuchigami , Imran Hashim , Pragati Kumar , Sandra Malhotra , Sunil Shanker
发明人： Hanhong Chen , Nobumichi Fuchigami , Imran Hashim , Pragati Kumar , Sandra Malhotra , Sunil Shanker
IPC分类号： H01L21/8242 , H01L21/02 , C23C16/455 , C23C16/02 , H01L27/108 , H01L49/02 , C23C16/40
CPC分类号： C23C16/45531 , C23C16/0272 , C23C16/0281 , C23C16/405 , H01L21/02186 , H01L21/02194 , H01L21/02197 , H01L21/0228 , H01L21/02304 , H01L27/10852 , H01L28/40 , H01L28/65 , H01L28/75
摘要： This disclosure provides a method of fabricating a semiconductor stack and associated device such as a capacitor and DRAM cell. In particular, a bottom electrode upon which a dielectric layer is to be grown may have a ruthenium-based surface. Lattice matching of the ruthenium surface with the dielectric layer (e.g., titanium oxide, strontium titanate or barium strontium titanate) helps promote the growth of rutile-phase titanium oxide, thereby leading to higher dielectric constant and lower effective oxide thickness. The ruthenium-based material also provides a high work function material, leading to lower leakage. To mitigate nucleation delay associated with the use of ruthenium, an adherence or glue layer based in titanium may be employed. A pretreatment process may be further employed so as to increase effective capacitor plate area, and thus promote even further improvements in dielectric constant and effective oxide thickness (“EOT”).
摘要翻译：本公开提供了制造半导体堆叠和相关设备（诸如电容器和DRAM单元）的方法。特别地，要生长电介质层的底部电极可以具有钌基表面。钌表面与电介质层的晶格匹配（例如氧化钛，钛酸锶钛酸钡或钛酸钡锶）有助于促进金红石相二氧化钛的生长，从而导致更高的介电常数和更低的有效氧化物厚度。钌基材料还提供高功函数材料，导致较低的泄漏。为了减轻与使用钌有关的成核延迟，可以采用基于钛的粘附层或胶层。可以进一步采用预处理工艺，以增加有效的电容器板面积，从而进一步提高介电常数和有效的氧化物厚度（“EOT”）。

3. 发明授权

US08481384B2 Method for producing MIM capacitors with high K dielectric materials and non-noble electrodes 有权
标题翻译：用于制造具有高K电介质材料和非贵金属电极的MIM电容器的方法
公开(公告)号：US08481384B2
公开(公告)日：2013-07-09
申请号：US13032739
申请日：2011-02-23
申请人： Hanhong Chen , Pragati Kumar
发明人： Hanhong Chen , Pragati Kumar
IPC分类号： H01L21/00
CPC分类号： H01L28/60 , H01L28/40
摘要： A method of producing a Metal-Insulator-Metal (MIM) capacitor stack through doping to achieve low current leakage and low equivalent oxide thickness is disclosed. A high K dielectric material is deposited on a non-noble electrode; the dielectric material is doped with oxides from group IIA. The dopant increases the barrier height of metal/insulator interface and neutralizes free electrons in dielectric material, therefore reduces the leakage current of MIM capacitor. The electrode may also be doped to increase work function while maintaining a rutile crystalline structure. The method thereby enhances the performance of DRAM MIM capacitor.
摘要翻译：公开了一种通过掺杂制造金属 - 绝缘体 - 金属（MIM）电容器堆叠以实现低电流泄漏和低等效氧化物厚度的方法。高K电介质材料沉积在非贵金属电极上; 电介质材料掺杂有IIA族的氧化物。掺杂剂增加了金属/绝缘体界面的势垒高度，并且中和了介电材料中的自由电子，从而降低了MIM电容器的漏电流。电极也可以掺杂以增加功函数，同时保持金红石晶体结构。该方法从而增强了DRAM MIM电容器的性能。

4. 发明授权

US08294219B2 Nonvolatile memory element including resistive switching metal oxide layers 有权
标题翻译：非易失性存储元件包括电阻式开关金属氧化物层
公开(公告)号：US08294219B2
公开(公告)日：2012-10-23
申请号：US12179538
申请日：2008-07-24
申请人： Sandra G. Malhotra , Pragati Kumar , Sean Barstow , Tony Chiang , Prashant B. Phatak , Wen Wu , Sunil Shanker
发明人： Sandra G. Malhotra , Pragati Kumar , Sean Barstow , Tony Chiang , Prashant B. Phatak , Wen Wu , Sunil Shanker
IPC分类号： H01L21/02
CPC分类号： H01L45/1608 , H01L27/2418 , H01L27/2463 , H01L45/08 , H01L45/1233 , H01L45/145 , H01L45/146 , H01L45/1625 , H01L45/1641
摘要： Nonvolatile memory elements that are based on resistive switching memory element layers are provided. A nonvolatile memory element may have a resistive switching metal oxide layer. The resistive switching metal oxide layer may have one or more layers of oxide. A resistive switching metal oxide may be doped with a dopant that increases its melting temperature and enhances its thermal stability. Layers may be formed to enhance the thermal stability of the nonvolatile memory element. An electrode for a nonvolatile memory element may contain a conductive layer and a buffer layer.
摘要翻译：提供了基于电阻式开关存储元件层的非易失性存储元件。非易失性存储元件可以具有电阻性开关金属氧化物层。电阻式开关金属氧化物层可以具有一层或多层氧化物。电阻式开关金属氧化物可以掺杂有增加其熔融温度并增强其热稳定性的掺杂剂。可以形成层以增强非易失性存储元件的热稳定性。用于非易失性存储元件的电极可以包含导电层和缓冲层。

5. 发明授权

US08278735B2 Yttrium and titanium high-k dielectric films 有权
标题翻译：钇和钛高k电介质膜
公开(公告)号：US08278735B2
公开(公告)日：2012-10-02
申请号：US12901239
申请日：2010-10-08
申请人： Imran Hashim , Indranil De , Tony Chiang , Edward Haywood , Hanhong Chen , Nobi Fuchigami , Pragati Kumar , Sandra Malhotra , Sunil Shanker
发明人： Imran Hashim , Indranil De , Tony Chiang , Edward Haywood , Hanhong Chen , Nobi Fuchigami , Pragati Kumar , Sandra Malhotra , Sunil Shanker
IPC分类号： H01L21/02
CPC分类号： H01L28/40 , C23C14/083 , C23C14/3464 , C23C16/405 , C23C16/45531 , H01L21/02186 , H01L21/02192 , H01L21/02194 , H01L21/02266 , H01L21/0228
摘要： This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on yttrium and titanium, to have a high dielectric constant and low leakage characteristic and (b) related devices and structures. An oxide layer having both yttrium and titanium may be fabricated either as an amorphous oxide or as an alternating series of monolayers. In several embodiments, the oxide is characterized by a yttrium contribution to total metal that is specifically controlled. The oxide layer can be produced as the result of a reactive process, if desired, via either a PVD process or, alternatively, via an atomic layer deposition process that employs specific precursor materials to allow for a common process temperature window for both titanium and yttrium reactions.
摘要翻译：本公开内容提供（a）制造基于钇和钛的氧化物层（例如，电介质层）的方法，以具有高介电常数和低泄漏特性，以及（b）相关的器件和结构。具有钇和钛的氧化物层可以制成无定形氧化物或交替的单层系列。在几个实施方案中，氧化物的特征在于对特定控制的总金属的钇贡献。如果需要，可以通过PVD工艺或者通过使用特定的前体材料以允许钛和钇的共同工艺温度窗口的原子层沉积工艺，作为反应过程的结果来生产氧化物层反应。

6. 发明申请

US20120149209A1 PROCESS SEQUENCING FOR HPC ALD SYSTEM 审中-公开
标题翻译： HPC ALD系统的过程顺序
公开(公告)号：US20120149209A1
公开(公告)日：2012-06-14
申请号：US12967278
申请日：2010-12-14
申请人： Ed Haywood , Pragati Kumar
发明人： Ed Haywood , Pragati Kumar
IPC分类号： H01L21/02
CPC分类号： C23C16/04 , C23C16/45525 , C23C16/45544
摘要： A combinatorial processing method is provided. The combinatorial processing method includes providing a flow of fluid over segregated sectors of a substrate to process the segregated sectors of the substrate in parallel without significantly exposing any section to a reagent without first applying a film and without subjecting any section to the same process step at the same time. Differently processed, segregated sectors may be generated in parallel.
摘要翻译：提供组合处理方法。组合处理方法包括在衬底的分离的扇区上提供流体流，以平行地处理衬底的偏析部分，而不会在不首先施加膜的情况下将任何部分显着地暴露于试剂，而不会使任何部分经受相同的工艺步骤同一时间。可以并行生成不同处理的隔离扇区。

7. 发明授权

US08053364B2 Closed-loop sputtering controlled to enhance electrical characteristics in deposited layer 有权
标题翻译：控制闭环溅射以增强沉积层中的电特性
公开(公告)号：US08053364B2
公开(公告)日：2011-11-08
申请号：US12243322
申请日：2008-10-01
申请人： Wayne French , Pragati Kumar , Prashant Phatak , Tony Chiang
发明人： Wayne French , Pragati Kumar , Prashant Phatak , Tony Chiang
IPC分类号： H01L21/44 , C23C14/00
CPC分类号： C23C14/083 , C23C14/0042 , C23C14/54 , H01L27/2409 , H01L27/2463 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/1625 , H01L45/1641 , H01L45/165
摘要： This disclosure provides a method of fabricating a semiconductor device layer and an associated memory cell. Empirical data may be used to generate a hysteresis curve associated with metal oxide deposition for a metal-insulator-metal structure, with curve measurements reflecting variance of a desired electrical property as a function of cathode voltage used during a sputtering process that uses a biased target. By generating at least one voltage level to be used during the sputtering process, where the voltage reflects a suitable value for the electrical property from among the values obtainable in mixed-mode deposition, a semiconductor device layer may be produced with improved characteristics and durability. A multistable memory cell or array of such cells manufactured according to this process can, for a set of given materials (e.g., metals and oxygen source), be fabricated to have minimal leakage or “off” current characteristics (Ileak or Ioff, respectively) or a maximum ratio of “on” current to “off” current (Ion/Ioff).
摘要翻译：本公开提供了制造半导体器件层和相关联的存储单元的方法。经验数据可用于产生与金属 - 绝缘体 - 金属结构的金属氧化物沉积相关联的滞后曲线，曲线测量反映了在使用偏置目标的溅射过程期间所使用的阴极电压的期望电特性的变化。通过在溅射过程中产生要使用的至少一个电压电平，其中电压从混合模式沉积中可获得的值中反映适合的电特性值，可以制造具有改进的特性和耐久性的半导体器件层。对于一组给定的材料（例如金属和氧源），可以制造这样的电池的多电平存储器单元或阵列，以便具有最小的泄漏或“截止”电流特性（分别为Ileak或Ioff）或“关”电流与“关”电流（Ion / Ioff）的最大比例。

8. 发明申请

US20110203085A1 TITANIUM-BASED HIGH-K DIELECTRIC FILMS 有权
标题翻译：基于钛的高K电介质膜
公开(公告)号：US20110203085A1
公开(公告)日：2011-08-25
申请号：US13100538
申请日：2011-05-04
申请人： Hanhong Chen , Pragati Kumar , Sunil Shanker , Edward Haywood , Sandra Malhotra , Imran Hashim , Nobi Fuchigami , Prashant Phatak , Monica Mathur
发明人： Hanhong Chen , Pragati Kumar , Sunil Shanker , Edward Haywood , Sandra Malhotra , Imran Hashim , Nobi Fuchigami , Prashant Phatak , Monica Mathur
IPC分类号： H01G7/00
CPC分类号： H01G4/1218 , C23C16/405 , C23C16/45531 , C23C16/56 , H01G4/33 , H01L21/02186 , H01L21/022 , H01L21/0228 , H01L21/02312 , H01L21/02337 , H01L21/3141 , H01L21/3142 , H01L28/40
摘要： This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on titanium oxide, to suppress the formation of anatase-phase titanium oxide and (b) related devices and structures. A metal-insulator-metal (“MIM”) stack is formed using an ozone pretreatment process of a bottom electrode (or other substrate) followed by an ALD process to form a TiO2 dielectric, rooted in the use of an amide-containing precursor. Following the ALD process, an oxidizing anneal process is applied in a manner is hot enough to heal defects in the TiO2 dielectric and reduce interface states between TiO2 and electrode; the anneal temperature is selected so as to not be so hot as to disrupt BEL surface roughness. Further process variants may include doping the titanium oxide, pedestal heating during the ALD process to 275-300 degrees Celsius, use of platinum or ruthenium for the BEL, and plural reagent pulses of ozone for each ALD process cycle. The process provides high deposition rates, and the resulting MIM structure has substantially no x-ray diffraction peaks associated with anatase-phase titanium oxide.
摘要翻译：本公开内容提供（a）制造基于氧化钛的氧化物层（例如电介质层）的方法，以抑制锐钛矿相氧化钛的形成和（b）相关的器件和结构。使用底部电极（或其他基底）的臭氧预处理随后进行ALD工艺来形成金属 - 绝缘体 - 金属（“MIM”）堆叠，以形成根植于含酰胺前体的TiO 2电介质。在ALD工艺之后，氧化退火工艺的应用热度足以愈合TiO2电介质中的缺陷，并降低TiO2和电极之间的界面态; 选择退火温度以使其不那么热，以致破坏BEL表面粗糙度。进一步的工艺变型可以包括在ALD工艺期间掺杂氧化钛，基座加热至275-300摄氏度，对于BEL使用铂或钌，对于每个ALD工艺循环使用多个试剂脉冲的臭氧。该方法提供高沉积速率，并且所得MIM结构基本上没有与锐钛矿相氧化钛相关的x射线衍射峰。

9. 发明申请

US20090273087A1 CLOSED-LOOP SPUTTERING CONTROLLED TO ENHANCE ELECTRICAL CHARACTERISTICS IN DEPOSITED LAYER 有权
标题翻译：控制加密环境中的电气特性的隐蔽环
公开(公告)号：US20090273087A1
公开(公告)日：2009-11-05
申请号：US12243322
申请日：2008-10-01
申请人： Wayne French , Pragati Kumar , Prashant Phatak , Tony Chiang
发明人： Wayne French , Pragati Kumar , Prashant Phatak , Tony Chiang
IPC分类号： H01L23/48 , C23C14/34
CPC分类号： C23C14/083 , C23C14/0042 , C23C14/54 , H01L27/2409 , H01L27/2463 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/1625 , H01L45/1641 , H01L45/165
摘要： This disclosure provides a method of fabricating a semiconductor device layer and an associated memory cell. Empirical data may be used to generate a hysteresis curve associated with metal oxide deposition for a metal-insulator-metal structure, with curve measurements reflecting variance of a desired electrical property as a function of cathode voltage used during a sputtering process that uses a biased target. By generating at least one voltage level to be used during the sputtering process, where the voltage reflects a suitable value for the electrical property from among the values obtainable in mixed-mode deposition, a semiconductor device layer may be produced with improved characteristics and durability. A multistable memory cell or array of such cells manufactured according to this process can, for a set of given materials (e.g., metals and oxygen source), be fabricated to have minimal leakage or “off” current characteristics (Ileak or Ioff, respectively) or a maximum ratio of “on” current to “off” current (Ion/Ioff).
摘要翻译：本公开提供了制造半导体器件层和相关联的存储单元的方法。经验数据可用于产生与金属 - 绝缘体 - 金属结构的金属氧化物沉积相关联的滞后曲线，曲线测量反映了在使用偏置目标的溅射过程期间所使用的阴极电压的期望电特性的变化。通过在溅射过程中产生要使用的至少一个电压电平，其中电压从混合模式沉积中可获得的值中反映适合的电特性值，可以制造具有改进的特性和耐久性的半导体器件层。对于一组给定的材料（例如金属和氧源），可以制造这样的电池的多电平存储器单元或阵列，以便具有最小的泄漏或“截止”电流特性（分别为Ileak或Ioff）或“关”电流与“关”电流（Ion / Ioff）的最大比例。

10. 发明申请

US20180332100A1 SCALED IN-ORDER RECORD INPUT INGESTION FOR FILE-BASED STREAMS IN MULTI-THREADED ENVIRONMENTS 审中-公开
公开(公告)号：US20180332100A1
公开(公告)日：2018-11-15
申请号：US15593791
申请日：2017-05-12
申请人： Priyanka Bhaskar , Sucheta Dahiya , Pragati Kumar Dhingra , Mohit Gupta , Devang Sethi
发明人： Priyanka Bhaskar , Sucheta Dahiya , Pragati Kumar Dhingra , Mohit Gupta , Devang Sethi
IPC分类号： H04L29/08
摘要： In various embodiments, streaming data records, files or file segments transmitted from multiple resources in a multi-threaded environment are sorted into one or more time windows via use of one or more execution threads; the records, files or file segments in each time window are displayed, analyzed or delivered to various applications or destinations.

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