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1. 发明申请

US20060031279A1 Highly parallel structure for fast multi cycle binary and decimal adder unit 审中-公开
标题翻译：用于快速多周期二进制和十进制加法器单元的高度并行结构
公开(公告)号：US20060031279A1
公开(公告)日：2006-02-09
申请号：US11175489
申请日：2005-07-06
申请人： Wilhelm Haller , Wen Li , Michael Kelly , Holger Wetter
发明人： Wilhelm Haller , Wen Li , Michael Kelly , Holger Wetter
IPC分类号： G06F7/50
CPC分类号： G06F7/494 , G06F7/508 , G06F7/575 , G06F2207/4924
摘要： An adder circuit for adding two binary or two decimal operands A and B in which the carries are calculated directly from the input operands A and B without including the plus 6 or minus 6 operations into the carry calculation. For all timing critical functions the reduced input data set, i.e., valid decimal data can be used and the non-existing decimal numbers (10 to 15) need not be excluded by separate check logic any more. This reduces the complexity of the logic functions.
摘要翻译：一个加法器电路，用于将两个二进制或两个十进制操作数A和B相加，其中运算由输入操作数A和B直接计算而不加加6或减6运算到进位计算中。对于所有时序关键功能，可以使用简化的输入数据集，即有效的十进制数据，并且不需要单独的检查逻辑排除不存在的十进制数（10至15）。这降低了逻辑功能的复杂性。

2. 发明授权

US5944772A Combined adder and logic unit 失效
标题翻译：组合加法器和逻辑单元
公开(公告)号：US5944772A
公开(公告)日：1999-08-31
申请号：US970076
申请日：1997-11-13
申请人： Juergen Haas , Wilhelm Haller , Ulrich Krauch , Thomas Ludwig , Holger Wetter
发明人： Juergen Haas , Wilhelm Haller , Ulrich Krauch , Thomas Ludwig , Holger Wetter
IPC分类号： G06F7/50 , G06F7/575
CPC分类号： G06F7/575 , G06F7/507 , G06F7/508
摘要： A combined adder and logic unit having a reduced operation delay of arithmetic and logic operations, and providing an improved fan in and reduced wiring delays and capacity if implemented in the arithmetic and logic section of a microprocessor chip. The unit comprises a carry network (30) connected to operand inputs for generating carry-out signals of the byte positions (By0-By7) and further comprises a pre-sum logic (32) having a bit function generator (42) and a sum generator (45, 46, 48). Said bit function generator derives from the operands Ai and Bi bit functions Gi, Pi which are provided as logic function output and as input to said sum generator for producing preliminary arithmetic functions (SUM0, SUM1) to anticipate carry-in signals of one or zero. A result selector (70) is controlled by a byte position carry-out signal (Cy55) from the carry network means and by operation control signals to select from the output of said pre-sum logic one of the arithmetic functions (SUM0, SUM1) or one of the logic functions as result of the unit operation.
摘要翻译：组合加法器和逻辑单元具有减小的运算和逻辑运算的运算延迟，并且如果在微处理器芯片的算术和逻辑部分中实现，则提供改进的风扇并降低布线延迟和容量。该单元包括连接到操作数输入的进位网络（30），用于产生字节位置（By0-By7）的进位信号，并且还包括具有位函数发生器（42）的和和逻辑（32）和总和发电机（45,46,48）。所述比特函数发生器从作为逻辑功能输出提供的操作数Ai和Bi比特函数Gi，Pi导出，并作为用于产生预计算函数（SUM0，SUM1）的所述和发生器的输入，以预期一或零的进位信号。结果选择器（70）由来自携带网络装置的字节位置执行输出信号（Cy55）和操作控制信号控制，以从所述算术功能（SUM0，SUM1）之一的所述并行逻辑逻辑的输出中进行选择，或作为单元操作的结果的逻辑功能之一。

3. 发明授权

US08286115B2 Fast routing of custom macros 有权
标题翻译：快速路由自定义宏
公开(公告)号：US08286115B2
公开(公告)日：2012-10-09
申请号：US12330664
申请日：2008-12-09
申请人： Holger Wetter , Maarten Boersma , Wilhelm Haller , Armin Windschiegl
发明人： Holger Wetter , Maarten Boersma , Wilhelm Haller , Armin Windschiegl
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F2217/66
摘要： A system for creating layout and wiring diagrams for an integrated circuit (IC) includes a placement engine configured to receive a hierarchical schematic and to create a placed layout. The system also includes a flat layout engine configured to receive the hierarchical schematic and to create a flat layout and a back annotation engine coupled to the placement engine and the flat layout engine, the back annotation engine configured to receive the hierarchical placed layout and the flat unplaced layout and to create a flat placed layout there from.
摘要翻译：一种用于创建集成电路（IC）的布局和接线图的系统包括配置成接收分级示意图并且创建放置的布局的布置引擎。该系统还包括平面布局引擎，其被配置为接收分级示意图并且创建耦合到放置引擎和平面布局引擎的平面布局和后注释引擎，后注释引擎被配置为接收分层放置的布局和平面未布置的布局，并从中创建一个平放布局。

4. 发明申请

US20100146471A1 FAST ROUTING OF CUSTOM MACROS 有权
标题翻译：快速路由自定义宏
公开(公告)号：US20100146471A1
公开(公告)日：2010-06-10
申请号：US12330664
申请日：2008-12-09
申请人： Holger Wetter , Maarten Boersma , Wilhelm Haller , Armin Windschiegl
发明人： Holger Wetter , Maarten Boersma , Wilhelm Haller , Armin Windschiegl
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F2217/66
摘要： A system for creating layout and wiring diagrams for an integrated circuit (IC) includes a placement engine configured to receive a hierarchical schematic and to create a placed layout. The system also includes a flat layout engine configured to receive the hierarchical schematic and to create a flat layout and a back annotation engine coupled to the placement engine and the flat layout engine, the back annotation engine configured to receive the hierarchical placed layout and the flat unplaced layout and to create a flat placed layout there from.
摘要翻译：一种用于创建集成电路（IC）的布局和接线图的系统包括配置成接收分级示意图并且创建放置的布局的布置引擎。该系统还包括平面布局引擎，其被配置为接收分级示意图并且创建耦合到放置引擎和平面布局引擎的平面布局和后注释引擎，后注释引擎被配置为接收分层放置的布局和平面未布置的布局，并从中创建一个平放布局。

5. 发明授权

US5928319A Combined binary/decimal adder unit 失效
标题翻译：组合二进制/十进制加法器单元
公开(公告)号：US5928319A
公开(公告)日：1999-07-27
申请号：US969244
申请日：1997-11-13
申请人： Wilhelm Haller , Ulrich Krauch , Thomas Ludwig , Holger Wetter
发明人： Wilhelm Haller , Ulrich Krauch , Thomas Ludwig , Holger Wetter
IPC分类号： G06F7/491 , G06F7/50
CPC分类号： G06F7/4912 , G06F7/507
摘要： A combined binary/decimal adder unit reduces the operation delay ine processing binary coded decimal operands and permit an increased cycle rate of a processor unit in which the combined binary/decimal adder unit is utilized. Pre-sums are generated for each decimal digit position in parallel to the generation and distribution of the carries over the total of decimal digit positions of the adder unit. The pre-sums anticipate the carry-in of the decimal positions and the need to perform six corrections after the carry-out signal of the highest decimal digit position has been generated. The carry-out signal of each decimal digit position is used in combination with operation control signals to select the correct pre-sum of the digit position.
摘要翻译：组合的二进制/十进制加法器单元减少了处理二进制编码十进制操作数的操作延迟，并且允许使用组合的二进制/十进制加法单元的处理器单元的增加的周期速率。对于加法器单元的十进制位数的总和的并行生成和分配，对于每个十进制数位置产生预和。预计总和预期小数位置的进位，并且在产生了最高十进制位数的进位信号之后需要进行六次校正。每个十进制位数的进位信号与操作控制信号组合使用，以选择数位位置的正确预置。

6. 发明授权

US06292819B1 Binary and decimal adder unit 有权
标题翻译：二进制和十进制加法器单元
公开(公告)号：US06292819B1
公开(公告)日：2001-09-18
申请号：US09235028
申请日：1999-01-21
申请人： Wolfgang Bultmann , Wilhelm Haller , Holger Wetter , Alexander Wörner
发明人： Wolfgang Bultmann , Wilhelm Haller , Holger Wetter , Alexander Wörner
IPC分类号： G06F750
CPC分类号： G06F7/494 , G06F7/507 , G06F2207/4924
摘要： A binary and decimal adder unit uses a pre-sum logic for generating pre-sums of the operands A, B under the presumption of one and zero carry inputs into the decimal digit position, and also uses a digits carry network for generating binary carries within the decimal digit positions and a high order carry out signal of said plurality of decimal digits. Each decimal digit position of said adder unit provides a six correction and a pre-sum selection. The pre-sum logic comprises a carry prediction logic for generating decimal digit position carry out signals on the presumption of a zero carry input and of a one carry input into the decimal digit. In response to gating signals derived from the carry out signals of the carry prediction logic and operation control signals a pre-selection is performed for selecting a qualified pre-sum generated on the presumption of a zero carry input into the decimal digit, and for selecting a qualified pre-sum generated on the presumption of a one carry input into the decimal digit. The pre-selection of the qualified pre-sums is performed for all decimal digit positions in parallel to the generation and distribution of the carries in the digits carry network over the total of decimal digit positions. The pre-sum selection logic further comprises a two way selector which is responsive to a digit carry-in signal from the digits carry network for selecting one the qualified pre-sums as the correct sum of the digit position. According to one embodiment of the invention, the pre-sum logic generates six corrected pre-sums which are included in the pre-selection of qualified pre-sums.
摘要翻译：二进制和十进制加法器单元使用预和逻辑来在将一个和零个进位输入推定为小数位置的情况下产生操作数A，B的前置和，并且还使用位数进位网络来产生二进制运算所述十进位数字位置和所述多个十进制数字的高阶进位信号。所述加法器单元的每个十进位数位置提供六次校正和一个预先和选择。前和逻辑包括进位预测逻辑，用于在零进位输入和一个进位输入到十进制数的推定中产生十位数位置执行信号。响应于来自进位预测逻辑的执行信号和操作控制信号的门控信号，执行预选择，以选择在零进位输入的推定中产生的合格的前置和十进制数，并且用于选择根据对十进制数字的一个进位输入的推定产生合格的预先和。对所有十进制数字位置进行合并预分配的预先选择，并行执行数字携带网络中携带的数据的生成和分配，总数小数位数。预和选择逻辑还包括双向选择器，其响应于来自数字携带网络的数字进位信号，用于选择一个合格的前置和作为数字位置的正确和。根据本发明的一个实施例，预先和逻辑产生六个经校正的前置和，其被包括在预先选择合格的前提中。

7. 发明授权

US08560983B2 Incorporating synthesized netlists as subcomponents in a hierarchical custom design 失效
标题翻译：将综合网表列入分层定制设计中的子组件
公开(公告)号：US08560983B2
公开(公告)日：2013-10-15
申请号：US13312108
申请日：2011-12-06
申请人： Uwe Brandt , Thomas M. Makowski , Christoph Wandel , Holger Wetter
发明人： Uwe Brandt , Thomas M. Makowski , Christoph Wandel , Holger Wetter
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/505
摘要： Mechanisms are provided for generating a physical layout of an integrated circuit design. A logic description of the integrated circuit design is received that comprises a first logic description of an irregular logic block of the integrated circuit design and a second logic description of a regular logic block of the integrated circuit design. A manual design of the regular logic block of the integrated circuit design is performed based on user input and an automated design of the irregular logic block of the integrated circuit design is performed without user input. The manual design of the regular logic block and the automated design of the irregular logic block are then integrated into the integrated circuit design to generate a hybrid integrated circuit design.
摘要翻译：提供用于生成集成电路设计的物理布局的机制。接收集成电路设计的逻辑描述，其包括集成电路设计的不规则逻辑块的第一逻辑描述和集成电路设计的规则逻辑块的第二逻辑描述。基于用户输入执行集成电路设计的常规逻辑块的手动设计，并且在不进行用户输入的情况下执行集成电路设计的不规则逻辑块的自动设计。然后将常规逻辑块的手动设计和不规则逻辑块的自动设计集成到集成电路设计中以产生混合集成电路设计。

8. 发明申请

US20090135961A1 System and Method for Scanning Sequential Logic Elements 有权
标题翻译：用于扫描顺序逻辑元件的系统和方法
公开(公告)号：US20090135961A1
公开(公告)日：2009-05-28
申请号：US12273985
申请日：2008-11-19
申请人： Tobias Gemmeke , Dieter Wendel , Holger Wetter , Jens Leenstra
发明人： Tobias Gemmeke , Dieter Wendel , Holger Wetter , Jens Leenstra
IPC分类号： H04L27/06
CPC分类号： G01R31/318536
摘要： System and Method for Scanning Sequential Logic Elements A digital system and method for scanning sequential logic elements are disclosed. The digital system may comprise a plurality of sequential logic elements subdivided into power domains, wherein at least one of the power domains is power gated; a scan chain configured for processing a scan data sequence; a scan enable switch configured for controlling a scan mode; and at least one shadow engine, wherein the at least one shadow engine comprises a control circuit. At least some of the power domains may be interconnected to the scan chain with the scan enable switch, and the scan enable switch may control the scan mode by asserting a scan enable signal. The at least one power gated power domain with one or more sequential logic elements to be power gated may be bypassed via the at least one shadow engine.
摘要翻译：用于扫描顺序逻辑元件的系统和方法公开了用于扫描顺序逻辑元件的数字系统和方法。数字系统可以包括被分成多个功率域的多个顺序逻辑元件，其中至少一个功率域是功率选通; 配置用于处理扫描数据序列的扫描链; 配置成用于控制扫描模式的扫描使能开关; 和至少一个阴影引擎，其中所述至少一个阴影引擎包括控制电路。至少一些功率域可以与扫描使能开关互连到扫描链，并且扫描使能开关可以通过断言扫描使能信号来控制扫描模式。可以经由至少一个阴影引擎绕过具有一个或多个顺序逻辑元件以供电门控的至少一个电源门控功率域。

9. 发明授权

US07913132B2 System and method for scanning sequential logic elements 有权
标题翻译：用于扫描顺序逻辑元件的系统和方法
公开(公告)号：US07913132B2
公开(公告)日：2011-03-22
申请号：US12273985
申请日：2008-11-19
申请人： Tobias Gemmeke , Dieter Wendel , Holger Wetter , Jens Leenstra
发明人： Tobias Gemmeke , Dieter Wendel , Holger Wetter , Jens Leenstra
IPC分类号： G01R31/28
CPC分类号： G01R31/318536
摘要： A digital system and method for scanning sequential logic elements are disclosed. The digital system may comprise a plurality of sequential logic elements subdivided into power domains, wherein at least one of the power domains is power gated; a scan chain configured for processing a scan data sequence; a scan enable switch configured for controlling a scan mode; and at least one shadow engine, wherein the at least one shadow engine comprises a control circuit. At least some of the power domains may be interconnected to the scan chain with the scan enable switch, and the scan enable switch may control the scan mode by asserting a scan enable signal. The at least one power gated power domain with one or more sequential logic elements to be power gated may be bypassed via the at least one shadow engine.
摘要翻译：公开了用于扫描顺序逻辑元件的数字系统和方法。数字系统可以包括被分成多个功率域的多个顺序逻辑元件，其中至少一个功率域是功率选通; 配置用于处理扫描数据序列的扫描链; 配置成用于控制扫描模式的扫描使能开关; 和至少一个阴影引擎，其中所述至少一个阴影引擎包括控制电路。至少一些功率域可以与扫描使能开关互连到扫描链，并且扫描使能开关可以通过断言扫描使能信号来控制扫描模式。可以经由至少一个阴影引擎绕过具有一个或多个顺序逻辑元件以供电门控的至少一个电源门控功率域。

10. 发明授权

US07873687B2 Method for calculating a result of a division with a floating point unit with fused multiply-add 失效
标题翻译：用融合乘法运算用浮点单位进行除法的结果的方法
公开(公告)号：US07873687B2
公开(公告)日：2011-01-18
申请号：US11458405
申请日：2006-07-19
申请人： Guenter Gerwig , Holger Wetter
发明人： Guenter Gerwig , Holger Wetter
IPC分类号： G06F7/487
CPC分类号： G06F7/4873 , G06F7/5443
摘要： The invention proposes a Floating Point Unit with fused multiply-add, with one addend Method for calculating a result of a division with an A-register and a B-register for two multiplicand operands and a C-register for an addend operand, wherein a divide processor using a subtractive method for calculation with a divisor register and a partial remainder register and a multiplier associated to an subtractor uses the C-register as input, wherein while loading the fraction of the dividend through the divisor register into the partial remainder register of the divide processor a calculated shifting is applied for alignment by using the multiplier associated to the subtractor.
摘要翻译：本发明提出了一种具有融合乘法运算的浮点单元，具有一个附加方法，用于计算用于两个被乘数操作数的A寄存器和B寄存器的分频结果，以及用于加数操作数的C寄存器，其中a 用除法寄存器和部分余数寄存器进行计算的减法方法来分割处理器，与减法器相关联的乘法器使用C寄存器作为输入，其中通过除数寄存器将除数的分数加载到部分余数寄存器分频处理器通过使用与减法器相关联的乘法器来应用计算的移位用于对准。

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