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1. 发明申请

US20110320514A1 DECIMAL ADDER WITH END AROUND CARRY 失效
标题翻译：十进制添加剂，带有附件
公开(公告)号：US20110320514A1
公开(公告)日：2011-12-29
申请号：US12822919
申请日：2010-06-24
申请人： Steven R. Carlough , Adam B. Collura , Klaus M. Kroener , Silvia M. Mueller
发明人： Steven R. Carlough , Adam B. Collura , Klaus M. Kroener , Silvia M. Mueller
IPC分类号： G06F7/485
CPC分类号： G06F7/494 , G06F7/508
摘要： Binary code decimal (BCD) arithmetic add/subtract operations on two BCD numbers independent of which BCD number is of a greater magnitude include, responsive to the BCD arithmetic add/subtract operation being a subtract operation, performing a BCD arithmetic subtraction operation on a first BCD number and a second BCD number, the first BCD number having a first magnitude and the second BCD number having a second magnitude. The first magnitude is greater than, equal to, or less than the second magnitude. The performing includes: in parallel to a carry generation, partial sums or partial differences of the first and second BCD numbers are computer such that a final result in signed magnitude form is selectable from the partial sums or differences based on carry information without any post processing steps.
摘要翻译：对于与BCD数量不同的两个BCD号码的二进制码十进制（BCD）算术加法/减法操作包括响应于BCD算术加/减操作作为减法运算，对第一个BCD运算执行BCD运算减法运算 BCD号和第二BCD号，第一BCD号具有第一幅值，第二BCD号具有第二幅值。第一幅度大于等于或小于第二幅度。执行包括：与进位生成并行，第一和第二BCD号码的部分和或部分差异是计算机，使得基于携带信息的部分和或差异可以从签名幅度形式中选择最终结果，而不进行任何后处理脚步。

2. 发明授权

US4638450A Equal nine apparatus for supporting absolute value subtracts on decimal operands of unequal length 失效
标题翻译：用于支持绝对值相等的九个装置减去不等长度的十进制操作数
公开(公告)号：US4638450A
公开(公告)日：1987-01-20
申请号：US537751
申请日：1983-09-30
申请人： Brian L. Stoffers
发明人： Brian L. Stoffers
IPC分类号： G06F7/494 , G06F7/50 , G06F7/38
CPC分类号： G06F7/494 , G06F2207/4924 , G06F7/4991
摘要： A data processing system having a central processing unit (CPU) capable of performing binary and decimal arithmetic software instructions is disclosed. The CPU includes a microprocessor which executes the binary arithmetic software instructions under firmware control. Also disclosed is apparatus utilizing a programmable memory and logic circuits that are used to subtract two operands and to generate and temporarily store a digit equal nine indication when the result of subtracting the two operands has a value of nine.
摘要翻译：公开了一种具有能够执行二进制和十进制算术软件指令的中央处理单元（CPU）的数据处理系统。 CPU包括在固件控制下执行二进制算术软件指令的微处理器。还公开了利用可编程存储器和逻辑电路的装置，当减去两个操作数的结果为9时，用于减去两个操作数并产生和临时存储数字相等的九个指示。

3. 发明授权

US4139894A Multi-digit arithmetic logic circuit for fast parallel execution 失效
标题翻译：用于快速并行执行的多位算术逻辑电路
公开(公告)号：US4139894A
公开(公告)日：1979-02-13
申请号：US769414
申请日：1977-02-17
申请人： Jogchum Reitsma
发明人： Jogchum Reitsma
IPC分类号： G06F7/493 , G06F7/494 , G06F7/50 , G06F7/507 , G06F7/575
CPC分类号： G06F7/494 , G06F7/507 , G06F7/575 , G06F2207/3876 , G06F2207/4924
摘要： A simple and fast arithmetic member for multi-digit numbers. For each digit a module is provided which receives the digits of corresponding significance and which first forms two output carry signals therefrom, i.e. one as if the relevant module always receives an input carry signal (E) and one as if this module never receives an input carry signal (D). Between successive modules each time functionally identical configurations of logic elements are connected which, under the control of the input carry signal to the module (Ci) of next-lower significance, the two output carry signals (Di, Ei) thereof, and an enable signal, forms the input carry signal for the stage of next-higher significance (C(i+1)) in accordance with the formulaC (i + 1) = Di + Ei.multidot.Ci.
摘要翻译：一个简单而快速的算术成员，用于多位数字。对于每个数字，提供接收相应重要性的数字的模块，并且其首先形成两个输出进位信号，即，如同相关模块总是接收输入进位信号（E）一样，并且一个如同该模块从未接收到输入进位信号（D）。在连续的模块之间，每次连接功能相同的逻辑元件配置时，在输入进位信号的控制下连接到下一个有效位的模块（Ci），其两个输出进位信号（Di，Ei）和一个使能信号，根据公式C（i + 1）= Di + EixCi，形成下一更高有效级（C（i + 1））阶段的输入进位信号。

4. 发明授权

US4041290A Microprogram controlled binary decimal coded byte operator device 失效
标题翻译：微程序控制二进制十进制编码字节操作装置
公开(公告)号：US4041290A
公开(公告)日：1977-08-09
申请号：US539034
申请日：1975-01-06
申请人： Jean-Louis Fressineau , Maurice Hubert
发明人： Jean-Louis Fressineau , Maurice Hubert
IPC分类号： G06F7/494 , G06F7/50 , G06F9/30 , G06F7/38
CPC分类号： G06F7/494 , G06F9/30025 , G06F2207/3828 , G06F2207/4924
摘要： A microprogram controlled operator device is described which processes bytes each of which is comprised of an equal number of binary-coded decimal figures. The device comprises first and second byte stores each of a multi-byte capacity, a logical and arithmetical operator circuit having inputs connected to read-out outputs of said stores and having an output to a buffer register and code handling organization, preferably further enabling "raw" byte inputting. An output of the code handling organization is connected to an input of a byte code processing arrangement which includes a multiplexer circuit having outputs to write-in inputs of the first and second stores and having further inputs connected to external data supplying means and to read-out outputs from the said stores. The organization further has an output to the external equipment wherein said device is connected.
摘要翻译：描述了一种微程序控制的操作装置，其处理每个由相等数量的二进制编码的十进制数字组成的字节。该设备包括第一和第二字节存储多字节容量，逻辑和算术运算器电路，其具有连接到所述存储器的读出输出并具有到缓冲寄存器和代码处理组织的输出的输入，优选地进一步启用“ 原始“字节输入。代码处理组织的输出连接到字节代码处理装置的输入，该字节代码处理装置包括具有输出到第一和第二存储的写入输入的多路复用器电路，并具有连接到外部数据提供装置的另外的输入，从所述商店输出。该组织还具有连接到所述设备的外部设备的输出。

5. 发明授权

US3711693A Modular bcd and binary arithmetic and logical system 失效
标题翻译：模块BCD和二进制算术和逻辑系统
公开(公告)号：US3711693A
公开(公告)日：1973-01-16
申请号：US3711693D
申请日：1971-06-30
申请人： HONEYWELL INF SYSTEMS
发明人： DAHL J
IPC分类号： G06F7/494 , G06F7/50 , G06F7/575
CPC分类号： G06F7/494 , G06F7/508 , G06F7/575 , G06F2207/3836 , G06F2207/4921
摘要： An arithmetic and logical unit for receiving four bit portions (quartets) of two input operands, a carry-in and several function control signals generates selectively several functions of the operands, including decimal and binary addition and subtraction functions or a desired logical function and provides carry lookahead and carry signals. A set of conversion gates selectively provides either a true or an excess-6 form of the first operand quartet while a complementation set of gates selectively provides a true or 1''s complement form of the second operand quartet. Bit pairs, from the corresponding positions in the resulting quartets, are combined to produce elementary logical functions, including the AND, inclusive OR and exclusive OR functions. In parallel, these elementary functions, an input carry bit, a set of carry look-ahead gates, a set of adder gates and a pair of control signals respectively provide carry signals and the selected function of the operands. A set of decimal correction gates, responsive to the carry signals, are used to correct the adder gate output for decimal addition and subtraction, when necessary.
摘要翻译：用于接收两个输入操作数的四位部分（四重）的算术和逻辑单元，进位和几个功能控制信号选择性地产生操作数的几个功能，包括十进制和二进制加法和减法功能或期望的逻辑功能，并且提供携带预先携带信号。一组转换门选择性地提供第一操作数四重奏的真或多余形式，而互补组门选择性地提供第二操作数四重奏的真或1的补码形式。来自所产生的四重奏中的相应位置的位对被组合以产生基本逻辑功能，包括AND，包含OR和异或功能。并行地，这些基本功能，输入进位，一组进位先行门，一组加法器门和一对控制信号分别提供进位信号和所选择的操作数的功能。根据需要，一组十进制校正门响应进位信号，用于校正加法器门输出以进行十进制加减。

6. 发明授权

US3535502A Multiple input binary adder 失效
标题翻译：多输入二进制表
公开(公告)号：US3535502A
公开(公告)日：1970-10-20
申请号：US3535502D
申请日：1967-11-15
申请人： IBM
发明人： CLAPPER GENUNG L
IPC分类号： G06F7/50 , G06F7/509 , G06F7/385
CPC分类号： G06F7/509 , G06F7/494 , G06F2207/4814 , G06F2207/4922 , G06F2207/4924

7. 发明授权

US3508037A Decimal add/subtract circuitry 失效
标题翻译： DECIMAL ADD / SUBTRACT CIRCUITRY
公开(公告)号：US3508037A
公开(公告)日：1970-04-21
申请号：US3508037D
申请日：1967-01-30
申请人： SPERRY RAND CORP
发明人： COLLINS DAVID M , IVERSON GARY J
IPC分类号： G06F7/494 , G06F7/50 , G06F7/385
CPC分类号： G06F7/494 , G06F2207/4924

8. 发明授权

US3375357A Automatic subtracting device 失效
标题翻译：自动减法装置
公开(公告)号：US3375357A
公开(公告)日：1968-03-26
申请号：US50072865
申请日：1965-10-22
申请人： BERKEL PATENT NV
发明人： LAUNCELOT DEKKER , RYAN JR LEROY J
IPC分类号： G01G23/16 , G06F7/494 , G06F7/50
CPC分类号： G06F7/494 , G01G23/163 , G06F2207/4924

9. 发明授权

US2943790A Arithmetic device 失效
公开(公告)号：US2943790A
公开(公告)日：1960-07-05
申请号：US55827056
申请日：1956-01-10
申请人： CURTISS WRIGHT CORP
发明人： EVELYN BEREZIN , PHYLLIS HERSH
IPC分类号： G06F7/494 , G06F7/50
CPC分类号： G06F7/494 , G06F2207/4921

10. 发明授权

US2798667A Code converter system 失效
标题翻译：代码转换器系统
公开(公告)号：US2798667A
公开(公告)日：1957-07-09
申请号：US33757253
申请日：1953-02-18
申请人： RCA CORP
发明人： SPIELBERG ARNOLD M , SUBLETTE IVAN H
IPC分类号： G06F7/491 , G06F7/50
CPC分类号： G06F7/4912 , G06F7/494 , G06F2207/49105

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