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1. 发明授权

US5944772A Combined adder and logic unit 失效
标题翻译：组合加法器和逻辑单元
公开(公告)号：US5944772A
公开(公告)日：1999-08-31
申请号：US970076
申请日：1997-11-13
申请人： Juergen Haas , Wilhelm Haller , Ulrich Krauch , Thomas Ludwig , Holger Wetter
发明人： Juergen Haas , Wilhelm Haller , Ulrich Krauch , Thomas Ludwig , Holger Wetter
IPC分类号： G06F7/50 , G06F7/575
CPC分类号： G06F7/575 , G06F7/507 , G06F7/508
摘要： A combined adder and logic unit having a reduced operation delay of arithmetic and logic operations, and providing an improved fan in and reduced wiring delays and capacity if implemented in the arithmetic and logic section of a microprocessor chip. The unit comprises a carry network (30) connected to operand inputs for generating carry-out signals of the byte positions (By0-By7) and further comprises a pre-sum logic (32) having a bit function generator (42) and a sum generator (45, 46, 48). Said bit function generator derives from the operands Ai and Bi bit functions Gi, Pi which are provided as logic function output and as input to said sum generator for producing preliminary arithmetic functions (SUM0, SUM1) to anticipate carry-in signals of one or zero. A result selector (70) is controlled by a byte position carry-out signal (Cy55) from the carry network means and by operation control signals to select from the output of said pre-sum logic one of the arithmetic functions (SUM0, SUM1) or one of the logic functions as result of the unit operation.
摘要翻译：组合加法器和逻辑单元具有减小的运算和逻辑运算的运算延迟，并且如果在微处理器芯片的算术和逻辑部分中实现，则提供改进的风扇并降低布线延迟和容量。该单元包括连接到操作数输入的进位网络（30），用于产生字节位置（By0-By7）的进位信号，并且还包括具有位函数发生器（42）的和和逻辑（32）和总和发电机（45,46,48）。所述比特函数发生器从作为逻辑功能输出提供的操作数Ai和Bi比特函数Gi，Pi导出，并作为用于产生预计算函数（SUM0，SUM1）的所述和发生器的输入，以预期一或零的进位信号。结果选择器（70）由来自携带网络装置的字节位置执行输出信号（Cy55）和操作控制信号控制，以从所述算术功能（SUM0，SUM1）之一的所述并行逻辑逻辑的输出中进行选择，或作为单元操作的结果的逻辑功能之一。

2. 发明授权

US5928319A Combined binary/decimal adder unit 失效
标题翻译：组合二进制/十进制加法器单元
公开(公告)号：US5928319A
公开(公告)日：1999-07-27
申请号：US969244
申请日：1997-11-13
申请人： Wilhelm Haller , Ulrich Krauch , Thomas Ludwig , Holger Wetter
发明人： Wilhelm Haller , Ulrich Krauch , Thomas Ludwig , Holger Wetter
IPC分类号： G06F7/491 , G06F7/50
CPC分类号： G06F7/4912 , G06F7/507
摘要： A combined binary/decimal adder unit reduces the operation delay ine processing binary coded decimal operands and permit an increased cycle rate of a processor unit in which the combined binary/decimal adder unit is utilized. Pre-sums are generated for each decimal digit position in parallel to the generation and distribution of the carries over the total of decimal digit positions of the adder unit. The pre-sums anticipate the carry-in of the decimal positions and the need to perform six corrections after the carry-out signal of the highest decimal digit position has been generated. The carry-out signal of each decimal digit position is used in combination with operation control signals to select the correct pre-sum of the digit position.
摘要翻译：组合的二进制/十进制加法器单元减少了处理二进制编码十进制操作数的操作延迟，并且允许使用组合的二进制/十进制加法单元的处理器单元的增加的周期速率。对于加法器单元的十进制位数的总和的并行生成和分配，对于每个十进制数位置产生预和。预计总和预期小数位置的进位，并且在产生了最高十进制位数的进位信号之后需要进行六次校正。每个十进制位数的进位信号与操作控制信号组合使用，以选择数位位置的正确预置。

3. 发明申请

US20090112963A1 METHOD TO PERFORM A SUBTRACTION OF TWO OPERANDS IN A BINARY ARITHMETIC UNIT PLUS ARITHMETIC UNIT TO PERFORM SUCH A METHOD 审中-公开
标题翻译：在二进制算术加法算术单元中执行两个运算符的执行的方法来执行这种方法
公开(公告)号：US20090112963A1
公开(公告)日：2009-04-30
申请号：US11926582
申请日：2007-10-29
申请人： Wilhelm Haller , Guenter Mayer , Veit Gernhoefer , Ulrich Krauch , Simon Fabel
发明人： Wilhelm Haller , Guenter Mayer , Veit Gernhoefer , Ulrich Krauch , Simon Fabel
IPC分类号： G06F7/508
CPC分类号： G06F7/507
摘要： A method, circuit apparatus, and a design structure on which the circuit resides, is provided to perform a subtraction of two operands in a binary arithmetic unit by subdividing two operands into groups of equal numbers of bits, generating, by appropriate arithmetic operations, pairs of intermediate results for the particular groups of bits of the two operands comprising the same bit positions, respectively. A first intermediate result of each pair of intermediate results is generated under the assumption of a carry-in of ‘0’ and a second intermediate result of each pair of intermediate results is generated under the assumption of a carry-in of ‘1’. The correct intermediate result of each particular pair of intermediate results from each group of bits is selected, and the result of the subtraction of the two operands is generated by an appropriate merging of the selected correct intermediate results.
摘要翻译：提供电路所在的方法，电路装置和设计结构，以通过将两个操作数细分为相等位数的组来执行二进制运算单元中的两个操作数的减法，通过适当的算术运算生成对分别包含相同比特位置的两个操作数的特定的比特组的中间结果。每个中间结果对的第一个中间结果是在“0”的进位假设下产生的，并且每个中间结果对的第二个中间结果在“1”的进位假设下生成。选择来自每组比特的每个特定中间结果对的正确的中间结果，并且通过适当地合并所选择的正确的中间结果来生成两个操作数的减法的结果。

4. 发明申请

US20130227250A1 SIMD ACCELERATOR FOR DATA COMPARISON 审中-公开
标题翻译：用于数据比较的SIMD加速器
公开(公告)号：US20130227250A1
公开(公告)日：2013-08-29
申请号：US13405021
申请日：2012-02-24
申请人： Wilhelm Haller , Ulrich Krauch , Kurt Lind , Friedrich Schroeder , Alexander Woerner
发明人： Wilhelm Haller , Ulrich Krauch , Kurt Lind , Friedrich Schroeder , Alexander Woerner
IPC分类号： G06F9/30 , G06F9/345 , G06F9/302
CPC分类号： G06F9/30021 , G06F9/30018 , G06F9/3887
摘要： Some example embodiments include an apparatus for comparing a first operand to a second operand. The apparatus includes a SIMD accelerator configured to compare first multiple parts (e.g., bytes) of first operand to second multiple parts (e.g., bytes) of the second operand. The SIMD accelerator includes a ones' complement subtraction logic and a twos' complement logic configured to perform logic operations on the multiple parts of the first operand and the multiple parts of the second operand to generate a group of carry out and propagate data across bits of the multiple parts. At least a portion of the group of carry out and propagate data is reused in the group of logic operations.
摘要翻译：一些示例性实施例包括用于将第一操作数与第二操作数进行比较的装置。该装置包括配置为将第一操作数的第一多个部分（例如，字节）与第二操作数的第二多个部分（例如，字节）进行比较的SIMD加速器。 SIMD加速器包括一个补码减法逻辑和二进制补码逻辑，其被配置为对第一操作数的多个部分和第二操作数的多个部分执行逻辑运算，以生成一组进位和传播数据多部分。该组执行和传播数据的至少一部分在逻辑操作组中被重用。

5. 发明申请

US20080177816A1 Method And Decimal Arithmetic Logic Unit Structure To Generate A Magnitude Result of a Mathematic 失效
标题翻译：方法和十进制算术逻辑单元结构生成数学的幅度结果
公开(公告)号：US20080177816A1
公开(公告)日：2008-07-24
申请号：US12013905
申请日：2008-01-14
申请人： Wilhelm Haller , Ulrich Krauch , Guenter Mayer , Eric M. Schwarz
发明人： Wilhelm Haller , Ulrich Krauch , Guenter Mayer , Eric M. Schwarz
IPC分类号： G06F7/491
CPC分类号： G06F7/4912
摘要： A method to generate a magnitude result of a mathematic operation of two decimal operands within one cycle in a decimal arithmetic logic unit structure, wherein the decimal operands are in hexadecimal sign magnitude format.
摘要翻译：一种在十进制算术逻辑单元结构中产生一个周期内的两个十进制操作数的数学运算的幅度结果的方法，其中十进制操作数是十六进制符号幅度格式。

6. 发明授权

US08612500B2 Method and decimal arithmetic logic unit structure to generate a magnitude result of a mathematic 失效
标题翻译：方法和十进制算术逻辑单元结构，产生一个数学的幅度结果
公开(公告)号：US08612500B2
公开(公告)日：2013-12-17
申请号：US12013905
申请日：2008-01-14
申请人： Wilhelm Haller , Ulrich Krauch , Guenter Mayer , Eric M. Schwarz
发明人： Wilhelm Haller , Ulrich Krauch , Guenter Mayer , Eric M. Schwarz
IPC分类号： G06F15/00 , G06F7/50
CPC分类号： G06F7/4912
摘要： A method to generate a magnitude result of a mathematic operation of two decimal operands within one cycle in a decimal arithmetic logic unit structure, wherein the decimal operands are in hexadecimal sign magnitude format.
摘要翻译：一种在十进制算术逻辑单元结构中产生一个周期内的两个十进制操作数的数学运算的幅度结果的方法，其中十进制操作数是十六进制符号幅度格式。

7. 发明申请

US20080071852A1 METHOD TO PERFORM A SUBTRACTION OF TWO OPERANDS IN A BINARY ARITHMETIC UNIT PLUS ARITHMETIC UNIT TO PERFORM SUCH A METHOD 审中-公开
标题翻译：在二进制算术加法算术单元中执行两个运算符的执行的方法来执行这种方法
公开(公告)号：US20080071852A1
公开(公告)日：2008-03-20
申请号：US11855658
申请日：2007-09-14
申请人： Wilhelm Haller , Guenter Mayer , Veit Gernhoefer , Ulrich Krauch , Simon Fabel
发明人： Wilhelm Haller , Guenter Mayer , Veit Gernhoefer , Ulrich Krauch , Simon Fabel
IPC分类号： G06F7/50
CPC分类号： G06F7/507
摘要： A method and apparatus is provided to perform a subtraction of two operands in a binary arithmetic unit by subdividing two operands into groups of equal numbers of bits, generating, by appropriate arithmetic operations, pairs of intermediate results for the particular groups of bits of the two operands comprising the same bit positions, respectively. A first intermediate result of each pair of intermediate results is generated under the assumption of a carry-in of ‘0’ and a second intermediate result of each pair of intermediate results is generated under the assumption of a carry-in of ‘1’. The correct intermediate result of each particular pair of intermediate results from each group of bits is selected, and the result of the subtraction of the two operands is generated by an appropriate merging of the selected correct intermediate results.
摘要翻译：提供了一种方法和装置，用于通过将两个操作数细分成相等位数的组来执行二进制运算单元中的两个操作数的减法，通过适当的算术运算，生成两个特定的位组的中间结果对分别包括相同位位置的操作数。每个中间结果对的第一个中间结果是在“0”的进位假设下产生的，并且每个中间结果对的第二个中间结果在“1”的进位假设下生成。选择来自每组比特的每个特定中间结果对的正确的中间结果，并且通过适当地合并所选择的正确的中间结果来生成两个操作数的减法的结果。

8. 发明授权

US08286115B2 Fast routing of custom macros 有权
标题翻译：快速路由自定义宏
公开(公告)号：US08286115B2
公开(公告)日：2012-10-09
申请号：US12330664
申请日：2008-12-09
申请人： Holger Wetter , Maarten Boersma , Wilhelm Haller , Armin Windschiegl
发明人： Holger Wetter , Maarten Boersma , Wilhelm Haller , Armin Windschiegl
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F2217/66
摘要： A system for creating layout and wiring diagrams for an integrated circuit (IC) includes a placement engine configured to receive a hierarchical schematic and to create a placed layout. The system also includes a flat layout engine configured to receive the hierarchical schematic and to create a flat layout and a back annotation engine coupled to the placement engine and the flat layout engine, the back annotation engine configured to receive the hierarchical placed layout and the flat unplaced layout and to create a flat placed layout there from.
摘要翻译：一种用于创建集成电路（IC）的布局和接线图的系统包括配置成接收分级示意图并且创建放置的布局的布置引擎。该系统还包括平面布局引擎，其被配置为接收分级示意图并且创建耦合到放置引擎和平面布局引擎的平面布局和后注释引擎，后注释引擎被配置为接收分层放置的布局和平面未布置的布局，并从中创建一个平放布局。

9. 发明申请

US20100146471A1 FAST ROUTING OF CUSTOM MACROS 有权
标题翻译：快速路由自定义宏
公开(公告)号：US20100146471A1
公开(公告)日：2010-06-10
申请号：US12330664
申请日：2008-12-09
申请人： Holger Wetter , Maarten Boersma , Wilhelm Haller , Armin Windschiegl
发明人： Holger Wetter , Maarten Boersma , Wilhelm Haller , Armin Windschiegl
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F2217/66
摘要： A system for creating layout and wiring diagrams for an integrated circuit (IC) includes a placement engine configured to receive a hierarchical schematic and to create a placed layout. The system also includes a flat layout engine configured to receive the hierarchical schematic and to create a flat layout and a back annotation engine coupled to the placement engine and the flat layout engine, the back annotation engine configured to receive the hierarchical placed layout and the flat unplaced layout and to create a flat placed layout there from.
摘要翻译：一种用于创建集成电路（IC）的布局和接线图的系统包括配置成接收分级示意图并且创建放置的布局的布置引擎。该系统还包括平面布局引擎，其被配置为接收分级示意图并且创建耦合到放置引擎和平面布局引擎的平面布局和后注释引擎，后注释引擎被配置为接收分层放置的布局和平面未布置的布局，并从中创建一个平放布局。

10. 发明申请

US20060031279A1 Highly parallel structure for fast multi cycle binary and decimal adder unit 审中-公开
标题翻译：用于快速多周期二进制和十进制加法器单元的高度并行结构
公开(公告)号：US20060031279A1
公开(公告)日：2006-02-09
申请号：US11175489
申请日：2005-07-06
申请人： Wilhelm Haller , Wen Li , Michael Kelly , Holger Wetter
发明人： Wilhelm Haller , Wen Li , Michael Kelly , Holger Wetter
IPC分类号： G06F7/50
CPC分类号： G06F7/494 , G06F7/508 , G06F7/575 , G06F2207/4924
摘要： An adder circuit for adding two binary or two decimal operands A and B in which the carries are calculated directly from the input operands A and B without including the plus 6 or minus 6 operations into the carry calculation. For all timing critical functions the reduced input data set, i.e., valid decimal data can be used and the non-existing decimal numbers (10 to 15) need not be excluded by separate check logic any more. This reduces the complexity of the logic functions.
摘要翻译：一个加法器电路，用于将两个二进制或两个十进制操作数A和B相加，其中运算由输入操作数A和B直接计算而不加加6或减6运算到进位计算中。对于所有时序关键功能，可以使用简化的输入数据集，即有效的十进制数据，并且不需要单独的检查逻辑排除不存在的十进制数（10至15）。这降低了逻辑功能的复杂性。

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