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1. 发明授权

US06292819B1 Binary and decimal adder unit 有权
标题翻译：二进制和十进制加法器单元
公开(公告)号：US06292819B1
公开(公告)日：2001-09-18
申请号：US09235028
申请日：1999-01-21
申请人： Wolfgang Bultmann , Wilhelm Haller , Holger Wetter , Alexander Wörner
发明人： Wolfgang Bultmann , Wilhelm Haller , Holger Wetter , Alexander Wörner
IPC分类号： G06F750
CPC分类号： G06F7/494 , G06F7/507 , G06F2207/4924
摘要： A binary and decimal adder unit uses a pre-sum logic for generating pre-sums of the operands A, B under the presumption of one and zero carry inputs into the decimal digit position, and also uses a digits carry network for generating binary carries within the decimal digit positions and a high order carry out signal of said plurality of decimal digits. Each decimal digit position of said adder unit provides a six correction and a pre-sum selection. The pre-sum logic comprises a carry prediction logic for generating decimal digit position carry out signals on the presumption of a zero carry input and of a one carry input into the decimal digit. In response to gating signals derived from the carry out signals of the carry prediction logic and operation control signals a pre-selection is performed for selecting a qualified pre-sum generated on the presumption of a zero carry input into the decimal digit, and for selecting a qualified pre-sum generated on the presumption of a one carry input into the decimal digit. The pre-selection of the qualified pre-sums is performed for all decimal digit positions in parallel to the generation and distribution of the carries in the digits carry network over the total of decimal digit positions. The pre-sum selection logic further comprises a two way selector which is responsive to a digit carry-in signal from the digits carry network for selecting one the qualified pre-sums as the correct sum of the digit position. According to one embodiment of the invention, the pre-sum logic generates six corrected pre-sums which are included in the pre-selection of qualified pre-sums.
摘要翻译：二进制和十进制加法器单元使用预和逻辑来在将一个和零个进位输入推定为小数位置的情况下产生操作数A，B的前置和，并且还使用位数进位网络来产生二进制运算所述十进位数字位置和所述多个十进制数字的高阶进位信号。所述加法器单元的每个十进位数位置提供六次校正和一个预先和选择。前和逻辑包括进位预测逻辑，用于在零进位输入和一个进位输入到十进制数的推定中产生十位数位置执行信号。响应于来自进位预测逻辑的执行信号和操作控制信号的门控信号，执行预选择，以选择在零进位输入的推定中产生的合格的前置和十进制数，并且用于选择根据对十进制数字的一个进位输入的推定产生合格的预先和。对所有十进制数字位置进行合并预分配的预先选择，并行执行数字携带网络中携带的数据的生成和分配，总数小数位数。预和选择逻辑还包括双向选择器，其响应于来自数字携带网络的数字进位信号，用于选择一个合格的前置和作为数字位置的正确和。根据本发明的一个实施例，预先和逻辑产生六个经校正的前置和，其被包括在预先选择合格的前提中。

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