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1. 发明申请

US20050055597A1 Clock tuning device and method 失效
标题翻译：时钟调谐装置及方法
公开(公告)号：US20050055597A1
公开(公告)日：2005-03-10
申请号：US10933896
申请日：2004-09-03
申请人： Wen-Shiung Weng , Chi-Kung Kuan , Sheng-Kai Chen , Ming-Chun Chang , Yi-Shu Chang
发明人： Wen-Shiung Weng , Chi-Kung Kuan , Sheng-Kai Chen , Ming-Chun Chang , Yi-Shu Chang
IPC分类号： G06F1/04 , G06F1/08
CPC分类号： G06F1/08
摘要： A clock tuning device and method for executing overclocking operations on plural elements disposed on a motherboard. The clock tuning device includes a phase-locked loop for outputting a plurality of clock signals to the elements, and a control circuit for controlling the phase-locked loop to adjust the frequencies of the clock signals, so as to execute the overclocking operations on the elements, respectively. The method includes the steps of: increasing the frequency of a first clock signal until one of the elements can't work normally due to an utmost frequency of the first clock signal; resetting all the elements and operating the element corresponding to the first signal according to a safe frequency of the first clock signal; and repeating the above steps to perform overclocking operation on each of the other elements.
摘要翻译：一种用于对设置在母板上的多个元件执行超频操作的时钟调谐装置和方法。时钟调谐装置包括用于向元件输出多个时钟信号的锁相环，以及用于控制锁相环以调整时钟信号的频率的控制电路，以便对该时钟信号执行超频操作元素。该方法包括以下步骤：增加第一时钟信号的频率，直到其中一个元件由于第一时钟信号的最大频率而不能正常工作; 根据第一时钟信号的安全频率，复位所有元件并对与第一信号相对应的元件进行操作; 并重复上述步骤对每个其他元件执行超频操作。

2. 发明授权

US07249275B2 Clock generating device and method for executing overclocking operation 失效
标题翻译：用于执行超频操作的时钟产生装置和方法
公开(公告)号：US07249275B2
公开(公告)日：2007-07-24
申请号：US10933896
申请日：2004-09-03
申请人： Wen-Shiung Weng , Chi-Kung Kuan , Sheng-Kai Chen , Ming-Chun Chang , Yi-Shu Chang
发明人： Wen-Shiung Weng , Chi-Kung Kuan , Sheng-Kai Chen , Ming-Chun Chang , Yi-Shu Chang
IPC分类号： G06F1/10
CPC分类号： G06F1/08
摘要： A clock tuning device and method for executing overclocking operations on plural elements disposed on a motherboard. The clock tuning device includes a phase-locked loop for outputting a plurality of clock signals to the elements, and a control circuit for controlling the phase-locked loop to adjust the frequencies of the clock signals, so as to execute the overclocking operations on the elements, respectively. The method includes the steps of: increasing the frequency of a first clock signal until one of the elements can't work normally due to an utmost frequency of the first clock signal; resetting all the elements and operating the element corresponding to the first signal according to a safe frequency of the first clock signal; and repeating the above steps to perform overclocking operation on each of the other elements.
摘要翻译：一种用于对设置在母板上的多个元件执行超频操作的时钟调谐装置和方法。时钟调谐装置包括用于向元件输出多个时钟信号的锁相环，以及用于控制锁相环以调整时钟信号的频率的控制电路，以便对该时钟信号执行超频操作元素。该方法包括以下步骤：增加第一时钟信号的频率，直到其中一个元件由于第一时钟信号的最大频率而不能正常工作; 根据第一时钟信号的安全频率，复位所有元件并对与第一信号相对应的元件进行操作; 并重复上述步骤对每个其他元件执行超频操作。

3. 发明授权

US07084687B2 Phase swallow device and signal generator using the same 有权
标题翻译：相位吞咽装置和信号发生器使用相同
公开(公告)号：US07084687B2
公开(公告)日：2006-08-01
申请号：US10896118
申请日：2004-07-22
申请人： Wen-Shiung Weng , Ming-Chun Chang , Chi-Kung Kuan , Yi-Shu Chang , Kuo-Lin Tai
发明人： Wen-Shiung Weng , Ming-Chun Chang , Chi-Kung Kuan , Yi-Shu Chang , Kuo-Lin Tai
IPC分类号： G06F1/04
CPC分类号： G06F1/10 , H03L7/00
摘要： A signal generator for generating a clock with lower jitter. The signal generator includes a multi-phase clock generator for generating a plurality of multi-phase reference clocks with same frequency, a multiplexer for selecting one reference clock as an output clock according to a phase selecting signal, a phase-swallow control unit having a comparator for comparing a swallow value with a reference value out of order and outputting the comparing result as a swallow control signal, and a clock selector for receiving the swallow control signal and generating the phase selecting signal. Because the reference value is provided by a counter in bit-reversed, the swallow control signal is dispersed smoothly and the jitter of the output clock is reduced.
摘要翻译：用于产生具有较低抖动的时钟的信号发生器。信号发生器包括用于产生具有相同频率的多个多相参考时钟的多相时钟发生器，用于根据相位选择信号选择一个参考时钟作为输出时钟的多路复用器，具有相位选择信号的相位控制单元比较器，用于将吞咽值与参考值进行比较，并输出比较结果作为吞咽控制信号;以及时钟选择器，用于接收吞咽控制信号并产生相位选择信号。由于参考值由位反转的计数器提供，所以吞咽控制信号平滑地分散，并且输出时钟的抖动减小。

4. 发明申请

US20050017771A1 Phase swallow device and signal generator using the same 有权
标题翻译：相位吞咽装置和信号发生器使用相同
公开(公告)号：US20050017771A1
公开(公告)日：2005-01-27
申请号：US10896118
申请日：2004-07-22
申请人： Wen-Shiung Weng , Ming-Chun Chang , Chi-Kung Kuan , Yi-Shu Chang , Kuo-Lin Tai
发明人： Wen-Shiung Weng , Ming-Chun Chang , Chi-Kung Kuan , Yi-Shu Chang , Kuo-Lin Tai
IPC分类号： G06F1/10 , H03L7/00
CPC分类号： G06F1/10 , H03L7/00
摘要： A signal generator for generating a clock with lower jitter. The signal generator includes a multi-phase clock generator for generating a plurality of multi-phase reference clocks with same frequency, a multiplexer for selecting one reference clock as an output clock according to a phase selecting signal, a phase-swallow control unit having a comparator for comparing a swallow value with a reference value out of order and outputting the comparing result as a swallow control signal, and a clock selector for receiving the swallow control signal and generating the phase selecting signal. Because the reference value is provided by a counter in bit-reversed, the swallow control signal is dispersed smoothly and the jitter of the output clock is reduced.
摘要翻译：用于产生具有较低抖动的时钟的信号发生器。信号发生器包括用于产生具有相同频率的多个多相参考时钟的多相时钟发生器，用于根据相位选择信号选择一个参考时钟作为输出时钟的多路复用器，具有相位选择信号的相位控制单元比较器，用于将吞咽值与参考值进行比较，并输出比较结果作为吞咽控制信号;以及时钟选择器，用于接收吞咽控制信号并产生相位选择信号。由于参考值由位反转的计数器提供，所以吞咽控制信号平滑地分散，并且输出时钟的抖动减小。

5. 发明授权

US08222962B2 High-resolution digitally controlled oscillator and method thereof 有权
标题翻译：高分辨率数字控制振荡器及其方法
公开(公告)号：US08222962B2
公开(公告)日：2012-07-17
申请号：US12115081
申请日：2008-05-05
申请人： Chia-Liang Lin , Chi-Kung Kuan
发明人： Chia-Liang Lin , Chi-Kung Kuan
IPC分类号： H03B5/12 , H03C3/09
CPC分类号： H03B5/1228 , H03B5/1212 , H03B5/1221 , H03B5/1253 , H03B2200/005
摘要： A digitally controlled oscillator provides high resolution in frequency tuning by using a digitally controlled capacitive network that includes a tunable capacitive circuit, a first capacitor and a second capacitor. The tunable capacitive circuit generates a variable capacitance according to a digital control word. The first capacitor is coupled in an electrically parallel configuration with the tunable capacitive circuit. The second capacitor is coupled in an electrically serial configuration with a combination of the first capacitor and the tunable capacitive circuit. The first capacitor and the second capacitor are sized such that an effective capacitance of the digitally controlled capacitor network has a step size that is a fraction of a step size of the variable capacitance in response to an incremental change in the digital control word.
摘要翻译：数字控制振荡器通过使用包含可调谐电容电路，第一电容器和第二电容器的数字控制电容网络来提供高分辨率的频率调谐。可调谐电容电路根据数字控制字产生可变电容。第一电容器与可调谐电容电路以电并联结构耦合。第二电容器以电串联配置与第一电容器和可调谐电容电路的组合耦合。第一电容器和第二电容器的尺寸使得数字控制电容器网络的有效电容具有响应于数字控制字的增量变化的可变电容的步长的一部分的步长。

6. 发明申请

US20080094145A1 HYBRID PHASE-LOCKED LOOP 有权
标题翻译：混合锁相环
公开(公告)号：US20080094145A1
公开(公告)日：2008-04-24
申请号：US11874209
申请日：2007-10-18
申请人： Chi-Kung Kuan , Yu-Pin Chou , Yi-Teng Chen
发明人： Chi-Kung Kuan , Yu-Pin Chou , Yi-Teng Chen
IPC分类号： H03L7/087 , H03L7/00
CPC分类号： H03L7/087 , H03L7/081 , H03L7/1976 , H03L7/23
摘要： A phase-locked loop (PLL) including a digital PFD, a digital loop filter, a decision circuit, a fractional-N PLL, and a frequency divider is provided. The digital PFD generates a first detection signal according to the phase error or frequency difference between an input signal and a feedback signal. The digital loop filter generates a first control signal according to the first detection signal. The decision circuit generates a divisor value according to the first control signal. The fractional-N PLL generates an oscillation signal according to the divisor value and a reference signal. The frequency divider divides the oscillation signal to produce the feedback signal. The fractional-N PLL includes a fractional-N frequency divider for generating a frequency-divided signal for use in tracking the reference signal according to the divisor value by employing phase swallow means.
摘要翻译：提供了包括数字PFD，数字环路滤波器，判决电路，分数N PLL和分频器的锁相环（PLL）。数字PFD根据输入信号和反馈信号之间的相位误差或频率差产生第一检测信号。数字环路滤波器根据第一检测信号产生第一控制信号。决定电路根据第一控制信号产生除数值。分数N PLL根据除数值和参考信号产生振荡信号。分频器分频振荡信号产生反馈信号。分数N PLL包括分数N分频器，用于通过采用相位吞吐装置，根据除数值产生用于跟踪参考信号的分频信号。

7. 发明授权

US07257729B2 System and method for processing an instruction according to a clock and adjusting the phase of the clock according to the instruction 有权
标题翻译：根据指令处理指令的系统和方法，并根据指令调整时钟的相位
公开(公告)号：US07257729B2
公开(公告)日：2007-08-14
申请号：US10907054
申请日：2005-03-18
申请人： Chao-Cheng Lee , Yi-Chih Huang , Chi-Kung Kuan
发明人： Chao-Cheng Lee , Yi-Chih Huang , Chi-Kung Kuan
IPC分类号： G06F1/00 , G06F5/06
CPC分类号： G06F9/3867 , G06F1/08 , G06F9/30181
摘要： A processor with an adjustable operating frequency and method thereof. The pipeline processor includes a clock providing module for providing a reference clock, and a processing core coupled to the clock providing module for processing a first instruction according to the reference clock. The clock providing module contains a multi-phase clock generator for generating a plurality of original clocks with different phases, and a phase selector for selecting an original clock to generate the reference clock according to the first instruction.
摘要翻译：具有可调工作频率的处理器及其方法。流水线处理器包括用于提供参考时钟的时钟提供模块和耦合到时钟提供模块的处理核心，用于根据参考时钟处理第一指令。时钟提供模块包括用于产生具有不同相位的多个原始时钟的多相时钟发生器，以及用于根据第一指令选择原始时钟以生成参考时钟的相位选择器。

8. 发明申请

US20130177325A1 Method and Apparatus of Automatic Power Control for Burst Mode Laser Transmitter 有权
标题翻译：爆破模式激光发射机自动功率控制方法与装置
公开(公告)号：US20130177325A1
公开(公告)日：2013-07-11
申请号：US13347875
申请日：2012-01-11
申请人： Chi-Kung Kuan , Gerchih Chou , Chia-Liang Lin
发明人： Chi-Kung Kuan , Gerchih Chou , Chia-Liang Lin
IPC分类号： H04B10/04
CPC分类号： H04B10/564 , H01S5/0427 , H01S5/06808 , H01S5/06832
摘要： An apparatus of automatic power control for burst mode laser transmitter and method are provided. In one implementation a method includes: generating an output current with a modulation pattern determined by a transmit data and a transmit enable signal, and a modulation level determined by a first control code and a second control code, wherein a light signal is generated in response to the output current; generating a first decision based on a comparison between a photodiode current and the first reference current, a second decision based on a comparison between the photodiode current and the second reference current, wherein the photodiode current is generated in accordance to the light signal; and generating the first control code and the second control code in response to the first decision and the second decision.
摘要翻译：提供了一种用于突发模式激光发射机的自动功率控制装置和方法。在一个实施方式中，一种方法包括：利用由发送数据和发送使能信号确定的调制模式以及由第一控制码和第二控制码确定的调制电平来产生输出电流，其中响应于产生光信号到输出电流; 基于光电二极管电流和第一参考电流之间的比较产生第一决策，基于光电二极管电流和第二参考电流之间的比较的第二决定，其中根据光信号产生光电二极管电流; 以及响应于所述第一判定和所述第二判定产生所述第一控制码和所述第二控制码。

9. 发明授权

US07545299B2 Analog front end device 有权
标题翻译：模拟前端设备
公开(公告)号：US07545299B2
公开(公告)日：2009-06-09
申请号：US11902663
申请日：2007-09-24
申请人： Jui-Yuan Tsai , Chi-Kung Kuan
发明人： Jui-Yuan Tsai , Chi-Kung Kuan
IPC分类号： H03M1/62
CPC分类号： H03M1/1028 , G09G5/006 , H03M1/123 , H04N9/642
摘要： The invention discloses an analog front end device includes a calibration unit and at least a conversion circuit. The conversion circuit includes a clamper, a multiplexer, an voltage buffer and an analog to digital converter. The clamper receives an image signal and resets the DC voltage level of the image signal to generate a clamped signal. The multiplexer receives the clamped signal and a test signal and outputs the clamped signal or the test signal according to a selecting signal. The voltage buffer amplifies the clamped signal or the test signal to generate a buffer signal. The analog to digital converter converts the buffer signal into a digital signal. The calibration unit generates a gain correction value according to the test signal and calibrates the gain offset of the digital signal according to the gain correction value.
摘要翻译：本发明公开了一种模拟前端装置，包括校准单元和至少一个转换电路。转换电路包括钳位器，复用器，电压缓冲器和模数转换器。夹持器接收图像信号并重置图像信号的直流电压电平以产生钳位信号。复用器接收钳位信号和测试信号，并根据选择信号输出钳位信号或测试信号。电压缓冲器放大钳位信号或测试信号以产生缓冲信号。模数转换器将缓冲器信号转换为数字信号。校准单元根据测试信号产生增益校正值，并根据增益校正值校准数字信号的增益偏移。

10. 发明申请

US20080094113A1 Fraction-N Frequency Divider and Method Thereof 有权
标题翻译：分数N分频器及其方法
公开(公告)号：US20080094113A1
公开(公告)日：2008-04-24
申请号：US11876760
申请日：2007-10-22
申请人： Chi-Kung Kuan
发明人： Chi-Kung Kuan
IPC分类号： H03B19/00
CPC分类号： H03K5/1506 , H03K5/1565 , H03K23/68 , H03L7/06
摘要： A fraction-N frequency divider includes a multi-phase clock generator, a first phase selector, a second phase selector, a glitch-free multiplexer, a control circuit, and a counter. The multi-phase clock generator is used for generating a plurality of clock signals with different phases. The first phase selector selects one of the clock signals as a first clock signal according to a first phase selecting signal. The second phase selector selects one of the clock signals as a second clock signal according to a second phase selecting signal. The glitch-free multiplexer is used for selectively outputting one of the first and second clock signals. The control circuit generates the first and second phase selecting signals and controls the clock switching timing of the glitch-free multiplexer according to a divisor setting. The counter is used for generating a frequency-divided signal according to the output of the glitch-free multiplexer.
摘要翻译：分数N分频器包括多相时钟发生器，第一相位选择器，第二相位选择器，无毛刺多路复用器，控制电路和计数器。多相时钟发生器用于产生具有不同相位的多个时钟信号。第一相位选择器根据第一相位选择信号选择一个时钟信号作为第一时钟信号。第二相位选择器根据第二相位选择信号选择一个时钟信号作为第二时钟信号。无毛刺多路复用器用于选择性地输出第一和第二时钟信号之一。控制电路产生第一和第二相位选择信号，并根据除数设置来控制无毛刺多路复用器的时钟切换定时。计数器用于根据无毛刺多路复用器的输出产生分频信号。

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