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1. 发明授权

US07249275B2 Clock generating device and method for executing overclocking operation 失效
标题翻译：用于执行超频操作的时钟产生装置和方法
公开(公告)号：US07249275B2
公开(公告)日：2007-07-24
申请号：US10933896
申请日：2004-09-03
申请人： Wen-Shiung Weng , Chi-Kung Kuan , Sheng-Kai Chen , Ming-Chun Chang , Yi-Shu Chang
发明人： Wen-Shiung Weng , Chi-Kung Kuan , Sheng-Kai Chen , Ming-Chun Chang , Yi-Shu Chang
IPC分类号： G06F1/10
CPC分类号： G06F1/08
摘要： A clock tuning device and method for executing overclocking operations on plural elements disposed on a motherboard. The clock tuning device includes a phase-locked loop for outputting a plurality of clock signals to the elements, and a control circuit for controlling the phase-locked loop to adjust the frequencies of the clock signals, so as to execute the overclocking operations on the elements, respectively. The method includes the steps of: increasing the frequency of a first clock signal until one of the elements can't work normally due to an utmost frequency of the first clock signal; resetting all the elements and operating the element corresponding to the first signal according to a safe frequency of the first clock signal; and repeating the above steps to perform overclocking operation on each of the other elements.
摘要翻译：一种用于对设置在母板上的多个元件执行超频操作的时钟调谐装置和方法。时钟调谐装置包括用于向元件输出多个时钟信号的锁相环，以及用于控制锁相环以调整时钟信号的频率的控制电路，以便对该时钟信号执行超频操作元素。该方法包括以下步骤：增加第一时钟信号的频率，直到其中一个元件由于第一时钟信号的最大频率而不能正常工作; 根据第一时钟信号的安全频率，复位所有元件并对与第一信号相对应的元件进行操作; 并重复上述步骤对每个其他元件执行超频操作。

2. 发明申请

US20050055597A1 Clock tuning device and method 失效
标题翻译：时钟调谐装置及方法
公开(公告)号：US20050055597A1
公开(公告)日：2005-03-10
申请号：US10933896
申请日：2004-09-03
申请人： Wen-Shiung Weng , Chi-Kung Kuan , Sheng-Kai Chen , Ming-Chun Chang , Yi-Shu Chang
发明人： Wen-Shiung Weng , Chi-Kung Kuan , Sheng-Kai Chen , Ming-Chun Chang , Yi-Shu Chang
IPC分类号： G06F1/04 , G06F1/08
CPC分类号： G06F1/08
摘要： A clock tuning device and method for executing overclocking operations on plural elements disposed on a motherboard. The clock tuning device includes a phase-locked loop for outputting a plurality of clock signals to the elements, and a control circuit for controlling the phase-locked loop to adjust the frequencies of the clock signals, so as to execute the overclocking operations on the elements, respectively. The method includes the steps of: increasing the frequency of a first clock signal until one of the elements can't work normally due to an utmost frequency of the first clock signal; resetting all the elements and operating the element corresponding to the first signal according to a safe frequency of the first clock signal; and repeating the above steps to perform overclocking operation on each of the other elements.
摘要翻译：一种用于对设置在母板上的多个元件执行超频操作的时钟调谐装置和方法。时钟调谐装置包括用于向元件输出多个时钟信号的锁相环，以及用于控制锁相环以调整时钟信号的频率的控制电路，以便对该时钟信号执行超频操作元素。该方法包括以下步骤：增加第一时钟信号的频率，直到其中一个元件由于第一时钟信号的最大频率而不能正常工作; 根据第一时钟信号的安全频率，复位所有元件并对与第一信号相对应的元件进行操作; 并重复上述步骤对每个其他元件执行超频操作。

3. 发明授权

US07084687B2 Phase swallow device and signal generator using the same 有权
标题翻译：相位吞咽装置和信号发生器使用相同
公开(公告)号：US07084687B2
公开(公告)日：2006-08-01
申请号：US10896118
申请日：2004-07-22
申请人： Wen-Shiung Weng , Ming-Chun Chang , Chi-Kung Kuan , Yi-Shu Chang , Kuo-Lin Tai
发明人： Wen-Shiung Weng , Ming-Chun Chang , Chi-Kung Kuan , Yi-Shu Chang , Kuo-Lin Tai
IPC分类号： G06F1/04
CPC分类号： G06F1/10 , H03L7/00
摘要： A signal generator for generating a clock with lower jitter. The signal generator includes a multi-phase clock generator for generating a plurality of multi-phase reference clocks with same frequency, a multiplexer for selecting one reference clock as an output clock according to a phase selecting signal, a phase-swallow control unit having a comparator for comparing a swallow value with a reference value out of order and outputting the comparing result as a swallow control signal, and a clock selector for receiving the swallow control signal and generating the phase selecting signal. Because the reference value is provided by a counter in bit-reversed, the swallow control signal is dispersed smoothly and the jitter of the output clock is reduced.
摘要翻译：用于产生具有较低抖动的时钟的信号发生器。信号发生器包括用于产生具有相同频率的多个多相参考时钟的多相时钟发生器，用于根据相位选择信号选择一个参考时钟作为输出时钟的多路复用器，具有相位选择信号的相位控制单元比较器，用于将吞咽值与参考值进行比较，并输出比较结果作为吞咽控制信号;以及时钟选择器，用于接收吞咽控制信号并产生相位选择信号。由于参考值由位反转的计数器提供，所以吞咽控制信号平滑地分散，并且输出时钟的抖动减小。

4. 发明申请

US20050017771A1 Phase swallow device and signal generator using the same 有权
标题翻译：相位吞咽装置和信号发生器使用相同
公开(公告)号：US20050017771A1
公开(公告)日：2005-01-27
申请号：US10896118
申请日：2004-07-22
申请人： Wen-Shiung Weng , Ming-Chun Chang , Chi-Kung Kuan , Yi-Shu Chang , Kuo-Lin Tai
发明人： Wen-Shiung Weng , Ming-Chun Chang , Chi-Kung Kuan , Yi-Shu Chang , Kuo-Lin Tai
IPC分类号： G06F1/10 , H03L7/00
CPC分类号： G06F1/10 , H03L7/00
摘要： A signal generator for generating a clock with lower jitter. The signal generator includes a multi-phase clock generator for generating a plurality of multi-phase reference clocks with same frequency, a multiplexer for selecting one reference clock as an output clock according to a phase selecting signal, a phase-swallow control unit having a comparator for comparing a swallow value with a reference value out of order and outputting the comparing result as a swallow control signal, and a clock selector for receiving the swallow control signal and generating the phase selecting signal. Because the reference value is provided by a counter in bit-reversed, the swallow control signal is dispersed smoothly and the jitter of the output clock is reduced.
摘要翻译：用于产生具有较低抖动的时钟的信号发生器。信号发生器包括用于产生具有相同频率的多个多相参考时钟的多相时钟发生器，用于根据相位选择信号选择一个参考时钟作为输出时钟的多路复用器，具有相位选择信号的相位控制单元比较器，用于将吞咽值与参考值进行比较，并输出比较结果作为吞咽控制信号;以及时钟选择器，用于接收吞咽控制信号并产生相位选择信号。由于参考值由位反转的计数器提供，所以吞咽控制信号平滑地分散，并且输出时钟的抖动减小。

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