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1. 发明申请

US20090153791A1 Chip on film structure 有权
标题翻译：片上胶片结构
公开(公告)号：US20090153791A1
公开(公告)日：2009-06-18
申请号：US12222354
申请日：2008-08-07
申请人： Ke-Chih Chang , Chih-Hsiang Yang , Sheng-Kai Hsu , Yi-Chih Huang , Ying-Chao Chen
发明人： Ke-Chih Chang , Chih-Hsiang Yang , Sheng-Kai Hsu , Yi-Chih Huang , Ying-Chao Chen
IPC分类号： G02F1/1345
CPC分类号： H05K1/0268 , G02F1/13452 , H01L23/4985 , H01L2924/0002 , H05K1/0393 , H05K1/117 , H05K3/0052 , H05K3/361 , H05K2201/09727 , H05K2201/10681 , H05K2203/175 , H01L2924/00
摘要： The chip on film structure for a liquid crystal display is disclosed. The chip on film structure includes a film substrate, a driver chip disposed on the film substrate, a plurality of the input pad, and a plurality of output pads. The input pads and the output pads are disposed on two opposite sides of the driver chip, and are electrically connect to the driver chip respectively. Each input pad comprises an extending portion extending from the input pads to a first cutting edge respectively, and a width of the extending portion is thinner than a width of the input pad, and the extending portions are cut along the first cutting edge.
摘要翻译：公开了一种用于液晶显示器的薄膜结构芯片。薄膜晶片上的芯片包括薄膜基板，设置在薄膜基板上的驱动芯片，多个输入焊盘和多个输出焊盘。输入焊盘和输出焊盘设置在驱动器芯片的两个相对的两侧，分别电连接到驱动器芯片。每个输入焊盘包括从输入焊盘分别延伸到第一切割刃的延伸部分，并且延伸部分的宽度比输入焊盘的宽度薄，并且延伸部分沿着第一切割刃切割。

2. 发明申请

US20080136456A1 Sampling circuit and sampling method thereof 审中-公开
标题翻译：采样电路及其采样方法
公开(公告)号：US20080136456A1
公开(公告)日：2008-06-12
申请号：US11953883
申请日：2007-12-11
申请人： Yi-Lin Chen , Yi-Chih Huang
发明人： Yi-Lin Chen , Yi-Chih Huang
IPC分类号： G01R29/02
CPC分类号： G01R31/31727 , G01R31/3016 , G01R31/31725
摘要： A sampling circuit includes a sampling unit, a first delay chain, an inverter, and a second delay chain. The sampling unit detects edge triggers of a first delayed signal and a second delayed signal for sampling input data to generate output data signal; the first delay chain is coupled to the sampling unit for delaying a sampling clock signal to output the first delayed signal; the inverter inverts the sampling clock signal to generate an inverted sampling clock signal; and the second delay chain is coupled to the inverter and the sampling unit for delaying the inverted sampling clock signal to output the second delayed signal.
摘要翻译：采样电路包括采样单元，第一延迟链，反相器和第二延迟链。采样单元检测第一延迟信号的边沿触发和用于采样输入数据的第二延迟信号以产生输出数据信号; 第一延迟链耦合到采样单元，用于延迟采样时钟信号以输出第一延迟信号; 逆变器反相采样时钟信号产生反相采样时钟信号; 并且第二延迟链耦合到反相器和采样单元，用于延迟反相采样时钟信号以输出第二延迟信号。

3. 发明申请

US20070245052A1 SYSTEM AND METHOD FOR BANDWIDTH SHARING IN BUSSES 审中-公开
标题翻译：系统中的带宽共享系统和方法
公开(公告)号：US20070245052A1
公开(公告)日：2007-10-18
申请号：US11735976
申请日：2007-04-16
申请人： Jing Jung HUANG , Yi Chih HUANG
发明人： Jing Jung HUANG , Yi Chih HUANG
IPC分类号： G06F13/36
CPC分类号： G06F13/364
摘要： A system for bandwidth sharing in busses comprises a shared bus, a timer for counting a predetermined period of time, a real-time master having a priority for using the shared bus, and a central processing unit having a priority higher than that of the real-time master for using the shared bus, wherein the central processing unit sends a predetermined number of bus request signals within the predetermined period of time for requesting the right for using the shared bus to transmit data. The present invention also provides a method for bandwidth sharing in busses.
摘要翻译：用于总线中带宽共享的系统包括共享总线，用于对预定时间段进行计数的定时器，具有使用共享总线的优先级的实时主机，以及具有比实际高的优先级的中央处理单元用于使用共享总线的时间主机，其中中央处理单元在预定时间段内发送预定数量的总线请求信号，以请求使用共享总线发送数据的权利。本发明还提供了一种用于总线中带宽共享的方法。

4. 发明授权

US07890786B2 Memory controller and signal synchronizing method thereof 有权
标题翻译：存储器控制器及其信号同步方法
公开(公告)号：US07890786B2
公开(公告)日：2011-02-15
申请号：US11948800
申请日：2007-11-30
申请人： Yi Lin Chen , Yi Chih Huang
发明人： Yi Lin Chen , Yi Chih Huang
IPC分类号： G06F1/04
CPC分类号： G06F13/1689
摘要： A memory controller includes an output buffer for receiving a clock signal and outputting the clock signal to an external memory; and a replica buffer for receiving the clock signal and outputting the clock signal to a counting circuit; wherein the replica buffer and the output buffer have the same delay time such that the clock signal received by the counting circuit can be synchronized with that received by the external memory, and therefore the counting circuit can accurately count to a predetermined time according to the clock signal and output an enabling signal to enable a data control signal. The present invention further provides a signal synchronizing method for the memory controller.
摘要翻译：存储器控制器包括用于接收时钟信号并将时钟信号输出到外部存储器的输出缓冲器; 以及用于接收时钟信号并将时钟信号输出到计数电路的副本缓冲器; 其中复制缓冲器和输出缓冲器具有相同的延迟时间，使得由计数电路接收的时钟信号可以与由外部存储器接收的时钟信号同步，因此计数电路可以根据时钟精确地计数到预定时间信号并输出使能信号以启用数据控制信号。本发明还提供了一种用于存储器控制器的信号同步方法。

5. 发明授权

US07779227B2 Memory management apparatus and method for optical storage system 有权
标题翻译：光存储系统的内存管理装置和方法
公开(公告)号：US07779227B2
公开(公告)日：2010-08-17
申请号：US11838235
申请日：2007-08-14
申请人： Hui-Huang Chang , Yi-Chih Huang , Feng-Cheng Liu
发明人： Hui-Huang Chang , Yi-Chih Huang , Feng-Cheng Liu
IPC分类号： G06F12/00
CPC分类号： G06F12/02 , G11B27/322 , G11B2220/2562
摘要： A memory management apparatus and a related method thereof for accessing digital versatile disc(DVD) data stored in a memory device are disclosed. The memory management apparatus includes an address mapping module, coupled to a bus, for receiving a logic address from the bus and for generating a physical address according to the logic address, and an access control module, coupled to the address mapping module and the memory device, for accessing the digital versatile disc data according to the physical address.
摘要翻译：公开了一种用于访问存储在存储器件中的数字通用盘（DVD）数据的存储器管理装置及其相关方法。存储器管理装置包括地址映射模块，其耦合到总线，用于从总线接收逻辑地址并根据逻辑地址生成物理地址;访问控制模块，耦合到地址映射模块和存储器装置，用于根据物理地址访问数字通用盘数据。

6. 发明申请

US20080133959A1 MEMORY CONTROLLER AND SIGNAL SYNCHRONIZING METHOD THEREOF 有权
标题翻译：内存控制器及其信号同步方法
公开(公告)号：US20080133959A1
公开(公告)日：2008-06-05
申请号：US11948800
申请日：2007-11-30
申请人： Yi Lin Chen , Yi Chih Huang
发明人： Yi Lin Chen , Yi Chih Huang
IPC分类号： G06F1/06
CPC分类号： G06F13/1689
摘要： A memory controller includes an output buffer for receiving a clock signal and outputting the clock signal to an external memory; and a replica buffer for receiving the clock signal and outputting the clock signal to a counting circuit; wherein the replica buffer and the output buffer have the same delay time such that the clock signal received by the counting circuit can be synchronized with that received by the external memory, and therefore the counting circuit can accurately count to a predetermined time according to the clock signal and output an enabling signal to enable a data control signal. The present invention further provides a signal synchronizing method for the memory controller.
摘要翻译：存储器控制器包括用于接收时钟信号并将时钟信号输出到外部存储器的输出缓冲器; 以及用于接收时钟信号并将时钟信号输出到计数电路的副本缓冲器; 其中复制缓冲器和输出缓冲器具有相同的延迟时间，使得由计数电路接收的时钟信号可以与由外部存储器接收的时钟信号同步，因此计数电路可以根据时钟精确地计数到预定时间信号并输出使能信号以启用数据控制信号。本发明还提供了一种用于存储器控制器的信号同步方法。

7. 发明申请

US20080046645A1 MEMORY MANAGEMENT APPARATUS AND METHOD FOR OPTICAL STORAGE SYSTEM 有权
标题翻译：光存储系统的存储管理装置和方法
公开(公告)号：US20080046645A1
公开(公告)日：2008-02-21
申请号：US11838235
申请日：2007-08-14
申请人： Hui-Huang Chang , Yi-Chih Huang , Feng-Cheng Liu
发明人： Hui-Huang Chang , Yi-Chih Huang , Feng-Cheng Liu
IPC分类号： G06F12/06
CPC分类号： G06F12/02 , G11B27/322 , G11B2220/2562
摘要： A memory management apparatus and a related method thereof for accessing digital versatile disc(DVD)data stored in a memory device are disclosed. The memory management apparatus includes an address mapping module, coupled to a bus, for receiving a logic address from the bus and for generating a physical address according to the logic address, and an access control module, coupled to the address mapping module and the memory device, for accessing the digital versatile disc data according to the physical address.
摘要翻译：公开了一种用于访问存储在存储器件中的数字通用盘（DVD）数据的存储器管理装置及其相关方法。存储器管理装置包括地址映射模块，其耦合到总线，用于从总线接收逻辑地址并根据逻辑地址生成物理地址;访问控制模块，耦合到地址映射模块和存储器装置，用于根据物理地址访问数字通用盘数据。

8. 发明申请

US20070277002A1 APPARATUS FOR SHARING ACCESS BY TWO MODULES AND METHOD THEREOF 审中-公开
标题翻译：用于通过两个模块共享访问的装置及其方法
公开(公告)号：US20070277002A1
公开(公告)日：2007-11-29
申请号：US11749737
申请日：2007-05-16
申请人： Keng-Hsiang Liao , Cheng-Hsin Chang , Yi-Chih Huang , Yu-Ting Chuang
发明人： Keng-Hsiang Liao , Cheng-Hsin Chang , Yi-Chih Huang , Yu-Ting Chuang
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： The present invention discloses an apparatus for sharing access by two modules includes at least a storage unit, a first module, and a second module. The second module is coupled to the first module and the storage unit, for accessing the storage unit according to a transmission protocol. The first module accesses the storage unit through the second module according to the transmission protocol. The present invention allows the first module to share access to the storage unit with the second module and thus the first module no longer needs to connect to another storage unit.
摘要翻译：本发明公开了一种用于由两个模块共享访问的装置，至少包括存储单元，第一模块和第二模块。第二模块耦合到第一模块和存储单元，用于根据传输协议访问存储单元。第一模块根据传输协议通过第二模块访问存储单元。本发明允许第一模块与第二模块共享对存储单元的访问，因此第一模块不再需要连接到另一个存储单元。

9. 发明授权

US07277906B2 Method for determining an output value having a lowest error value from an input value 有权
标题翻译：用于从输入值确定具有最低误差值的输出值的方法
公开(公告)号：US07277906B2
公开(公告)日：2007-10-02
申请号：US10707701
申请日：2004-01-05
申请人： Hai-Wei Wang , Yi-Chih Huang
发明人： Hai-Wei Wang , Yi-Chih Huang
IPC分类号： G06F1/02
CPC分类号： G06F1/0356
摘要： The present invention teaches a method for generating an output value corresponding to an input value via a first function comprising a first section and a second section with the use of a lookup table, comprising: prestoring a plurality of first sampling points corresponding only to a third section of a second function, wherein the second function further includes a fourth section and there is a first mathematical transformation between the first function and the second function; receiving the input value corresponding to the first section; generating the output value based on at least one of the first sampling points through performing the first mathematical transformation on the first sampling point; and outputting the output value.
摘要翻译：本发明教导了一种用于通过包括第一部分和第二部分的第一功能通过使用查找表来产生对应于输入值的输出值的方法，包括：预先存储对应于仅第三部分的第三个第一采样点其中所述第二功能还包括第四部分，并且在所述第一功能和所述第二功能之间存在第一数学变换; 接收对应于第一部分的输入值; 通过对所述第一采样点执行所述第一数学变换，基于所述第一采样点中的至少一个生成所述输出值; 并输出该输出值。

10. 发明申请

US20050149594A1 METHOD FOR DETERMINING AN OUTPUT VALUE HAVING A LOWEST ERROR VALUE FROM AN INPUT VALUE 有权
标题翻译：用于从输入值确定具有最低错误值的输出值的方法
公开(公告)号：US20050149594A1
公开(公告)日：2005-07-07
申请号：US10707701
申请日：2004-01-05
申请人： Hai-Wei Wang , Yi-Chih Huang
发明人： Hai-Wei Wang , Yi-Chih Huang
IPC分类号： G06F1/035 , G06F7/00
CPC分类号： G06F1/0356
摘要： The present invention teaches a method for generating an output value corresponding to an input value via a first function comprising a first section and a second section with the use of a lookup table, comprising: prestoring a plurality of first sampling points corresponding only to a third section of a second function, wherein the second function further includes a fourth section and there is a first mathematical transformation between the first function and the second function; receiving the input value corresponding to the first section; generating the output value based on at least one of the first sampling points through performing the first mathematical transformation on the first sampling point; and outputting the output value.
摘要翻译：本发明教导了一种用于通过包括第一部分和第二部分的第一功能通过使用查找表来产生对应于输入值的输出值的方法，包括：预先存储对应于仅第三部分的第三个第一采样点其中所述第二功能还包括第四部分，并且在所述第一功能和所述第二功能之间存在第一数学变换; 接收对应于第一部分的输入值; 通过对所述第一采样点执行所述第一数学变换，基于所述第一采样点中的至少一个生成所述输出值; 并输出该输出值。

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