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1. 发明授权

US06559003B2 Method of producing a ferroelectric semiconductor memory 失效
标题翻译：铁电半导体存储器的制造方法
公开(公告)号：US06559003B2
公开(公告)日：2003-05-06
申请号：US09753587
申请日：2001-01-03
申请人： Walter Hartner , Günther Schindler , Marcus Kastner , Christine Dehm
发明人： Walter Hartner , Günther Schindler , Marcus Kastner , Christine Dehm
IPC分类号： H01L218242
CPC分类号： H01L27/11502 , H01L27/11507 , H01L28/55 , H01L28/75
摘要： A method of producing a ferroelectric semiconductor memory, includes forming a switching transistor on a semiconductor substrate, applying an insulating layer to the switching transistor and then forming a storage capacitor, with electrodes of platinum and a ferroelectric or paraelectric dielectric, on the insulating layer. In order to protect the dielectric from being penetrated by hydrogen during further process steps, a first barrier layer is embedded into the insulating layer and, after completion of the storage capacitor, a second barrier layer, which bonds with the first barrier layer, is deposited.
摘要翻译：一种制造铁电半导体存储器的方法，包括在半导体衬底上形成开关晶体管，在绝缘层上向开关晶体管施加绝缘层，然后形成具有铂电极和铁电体或顺电介质的存储电容器。为了在另外的工艺步骤期间保护电介质不被氢气渗入，第一阻挡层被嵌入到绝缘层中，并且在存储电容器完成之后，与第一阻挡层结合的第二阻挡层被沉积。

2. 发明授权

US06500677B2 Method for fabricating a ferroelectric memory configuration 失效
标题翻译：铁电存储器配置的制造方法
公开(公告)号：US06500677B2
公开(公告)日：2002-12-31
申请号：US10027106
申请日：2001-12-26
申请人： Renate Bergmann , Christine Dehm , Thomas Roehr , Georg Braun , Heinz Hoenigschmid , Günther Schindler
发明人： Renate Bergmann , Christine Dehm , Thomas Roehr , Georg Braun , Heinz Hoenigschmid , Günther Schindler
IPC分类号： H01L2100
CPC分类号： H01L27/11502 , H01L27/11507
摘要： The invention provides a method. In a first step of a method for fabricating a ferroelectric memory configuration, there is provided a substrate having a multiplicity of memory cells. Each of the memory cells has at least one select transistor, at least one short-circuit transistor, and at least one ferroelectric capacitor. The transistors are connected in an electrically conductive manner to a first of the electrodes of the ferroelectric capacitor. In the next step, at least one electrically insulating layer is applied. In the next step, at least one contact hole for connecting a second electrode of the ferroelectric capacitors is produced. Next, contact holes for connecting the short-circuit transistors are produced. Next, the contact holes are filled with electrically conductive material. Next, an electrically conductive layer is applied and patterned, so that the second electrodes of the ferroelectric capacitors are each conductively connected to the short-circuit transistors.
摘要翻译：本发明提供了一种方法。在制造铁电存储器结构的方法的第一步骤中，提供了具有多个存储单元的衬底。每个存储单元具有至少一个选择晶体管，至少一个短路晶体管和至少一个铁电电容器。晶体管以导电方式连接到铁电电容器的第一电极。在下一步骤中，施加至少一个电绝缘层。在下一步骤中，产生用于连接铁电电容器的第二电极的至少一个接触孔。接下来，制造用于连接短路晶体管的接触孔。接下来，接触孔填充有导电材料。接下来，施加导电层并图案化，使得强电介质电容器的第二电极分别与短路晶体管导通。

3. 发明申请

US20070194301A1 Semiconductor arrangement with non-volatile memories 审中-公开
标题翻译：具有非易失性存储器的半导体装置
公开(公告)号：US20070194301A1
公开(公告)日：2007-08-23
申请号：US10580881
申请日：2004-11-24
申请人： Recai Sezi , Andreas Walter , Reimund Engl , Anna Maltenberger , Christine Dehm , Sitaram Arkalgud , Igor Kasko , Joachim Nuetzel , Jakob Kriz , Thomas Mikolajick , Cay-Uwe Pinnow
发明人： Recai Sezi , Andreas Walter , Reimund Engl , Anna Maltenberger , Christine Dehm , Sitaram Arkalgud , Igor Kasko , Joachim Nuetzel , Jakob Kriz , Thomas Mikolajick , Cay-Uwe Pinnow
IPC分类号： H01L51/00 , H01L21/8232
CPC分类号： H01L51/0036 , B82Y10/00 , G11C13/0014 , G11C13/0016 , H01L27/28 , H01L51/0051 , H01L51/0062 , H01L51/0595
摘要： One aspect of the invention relates to a semiconductor arrangement having at least one nonvolatile memory cell which has a first electrode comprising at least two layers; and having an organic material, the organic material forming a compound with that layer of the first electrode which is in direct contact. One aspect of the invention furthermore relates to a method for producing the nonvolatile memory cell, a semiconductor arrangement having a plurality of memory cells according to the invention, and a method for producing the same.
摘要翻译：本发明的一个方面涉及具有至少一个非易失性存储单元的半导体装置，其具有包括至少两层的第一电极; 并且具有有机材料，所述有机材料与所述第一电极的所述层直接接触形成化合物。本发明的一个方面还涉及一种用于制造非易失性存储单元的方法，具有根据本发明的多个存储单元的半导体装置及其制造方法。

4. 发明授权

US6057220A Titanium polycide stabilization with a porous barrier 失效
标题翻译：具有多孔屏障的多晶硅化钛稳定剂
公开(公告)号：US6057220A
公开(公告)日：2000-05-02
申请号：US936029
申请日：1997-09-23
申请人： Atul C. Ajmera , Christine Dehm , Anthony G. Domenicucci , George G. Gifford , Stephen K. Loh , Christopher Parks , Viraj Y. Sardesai
发明人： Atul C. Ajmera , Christine Dehm , Anthony G. Domenicucci , George G. Gifford , Stephen K. Loh , Christopher Parks , Viraj Y. Sardesai
IPC分类号： H01L21/28 , H01L29/49 , H01L21/44 , H01L21/425
CPC分类号： H01L21/28061 , H01L29/4933
摘要： A "porous barrier" is formed without formation of a discrete barrier layer by enriching grain boundaries of a body of polysilicon with nitrogen to inhibit thermal mobility of silicon species therealong. In a polycide gate/interconnect structure, the reduced mobility of silicon suppresses agglomeration of silicon in a metal silicide layer formed thereon. Since silicon agglomeration is a precursor of a polycide inversion phenomenon, polycide inversion which can pierce an underlying oxide and cause device failure is effectively avoided. The increased thermal stability of polycide structures and other structures including a body of polysilicon thus increases the heat budget that can be withstood by the structure and increases the manufacturing process window imposed by the presence of polysilicon which can be exploited in other processes such as annealing to develop a low resistance phase of refractory metal silicide included in the polycide structure, drive-in annealing for formation of source/drain regions of field effect transistors and the like.
摘要翻译：通过用氮富集多晶硅体的晶界而形成不形成离散阻挡层的“多孔阻挡层”，以抑制硅物质的热迁移率。在多晶硅栅极/互连结构中，硅的迁移率降低抑制了在其上形成的金属硅化物层中的硅的聚集。由于硅团聚是多杀线反转现象的前体，因此有效地避免了可能刺穿潜在氧化物并导致器件故障的多硅化物反转。因此，多晶硅结构和包括多晶硅体在内的其他结构的热稳定性增加，因此增加了可被该结构承受的热量预算，并且增加了存在多晶硅所产生的制造工艺窗口，这可以在其它工艺中被利用，例如退火开发包括在多晶硅结构中的难熔金属硅化物的低电阻相，用于形成场效应晶体管的源极/漏极区域的驱动退火等。

5. 发明授权

US07005303B2 Low temperature chemical vapor deposition process for forming bismuth-containing ceramic thin films useful in ferroelectric memory devices 失效
标题翻译：用于形成用于铁电存储器件的含铋陶瓷薄膜的低温化学气相沉积工艺
公开(公告)号：US07005303B2
公开(公告)日：2006-02-28
申请号：US10836550
申请日：2004-04-30
申请人： Frank S. Hintermaier , Christine Dehm , Wolfgang Hoenlein , Peter C. Van Buskirk , Jeffrey F. Roeder , Bryan C. Hendrix , Thomas H. Baum , Debra A. Desrochers
发明人： Frank S. Hintermaier , Christine Dehm , Wolfgang Hoenlein , Peter C. Van Buskirk , Jeffrey F. Roeder , Bryan C. Hendrix , Thomas H. Baum , Debra A. Desrochers
IPC分类号： H01L21/00
CPC分类号： H01L21/02271 , C23C16/40 , C23C16/56 , H01L21/02197 , H01L21/02205 , H01L21/02356 , H01L21/31691
摘要： A low temperature CVD process for deposition of bismuth-containing ceramic thin films suitable for integration to fabricate ferroelectric memory devices. The bismuth-containing film can be formed using a tris(β-diketonate) bismuth precursor. Films of amorphous SBT can be formed by CVD and then ferroannealed to produce films with Aurivillius phase composition having superior ferroelectric properties suitable for manufacturing high density FRAMs.
摘要翻译：用于沉积适合于集成以制造铁电存储器件的含铋陶瓷薄膜的低温CVD工艺。含铋膜可以使用三（β-二酮）铋前体形成。可以通过CVD形成非晶态SBT膜，然后用铁退镀以制备具有优异的铁电性能的Aurivillius相组成的膜，适用于制造高密度FRAM。

6. 发明授权

US06730523B2 Low temperature chemical vapor deposition process for forming bismuth-containing ceramic thin films useful in ferroelectric memory devices 失效
标题翻译：用于形成用于铁电存储器件的含铋陶瓷薄膜的低温化学气相沉积工艺
公开(公告)号：US06730523B2
公开(公告)日：2004-05-04
申请号：US09873138
申请日：2001-06-01
申请人： Frank S. Hintermaier , Christine Dehm , Wolfgang Hoenlein , Peter C. Van Buskirk , Jeffrey F. Roeder , Bryan C. Hendrix , Thomas H. Baum , Debra A. Desrochers
发明人： Frank S. Hintermaier , Christine Dehm , Wolfgang Hoenlein , Peter C. Van Buskirk , Jeffrey F. Roeder , Bryan C. Hendrix , Thomas H. Baum , Debra A. Desrochers
IPC分类号： H01L2100
CPC分类号： H01L21/31691 , C23C16/40 , C23C16/56
摘要： A low temperature CVD process using a tris (&bgr;-diketonate) bismuth precursor for deposition of bismuth ceramic thin films suitable for integration to fabricate ferroelectric memory devices. Films of amorphous SBT can be formed by CVD and then ferroannealed to produce films with Aurivillius phase composition having superior ferroelectric properties suitable for manufacturing high density FRAMs.
摘要翻译：使用三（β-二酮）铋前体的低温CVD方法，用于沉积适合于制造铁电存储器件的一体化的铋陶瓷薄膜。可以通过CVD形成非晶态SBT膜，然后用铁退镀以制备具有优异的铁电性能的Aurivillius相组成的膜，适用于制造高密度FRAM。

7. 发明授权

US06670662B1 Semiconductor storage component with storage cells, logic areas and filling structures 有权
标题翻译：具有存储单元，逻辑区域和填充结构的半导体存储组件
公开(公告)号：US06670662B1
公开(公告)日：2003-12-30
申请号：US09980386
申请日：2002-03-19
申请人： Christine Dehm , Guenther Schindler
发明人： Christine Dehm , Guenther Schindler
IPC分类号： H01L27108
CPC分类号： H01L27/10844 , H01L27/10852 , H01L28/55 , H01L28/60
摘要： The invention provides a semiconductor memory component with random access, also having a structure which is differentiated into memory cells and logic regions and has a lower oxide layer arranged on a silicon substrate and an upper oxide layer arranged on the lower oxide layer, each memory cell comprising at least one transistor in the transition region between silicon substrate and lower oxide layer and a capacitor in the transition region between lower oxide layer and upper oxide layer, which capacitor is connected to the transistor via a contact hole, which is filled with metal, in the lower oxide layer and comprises a ferroelectric arranged between two electrodes, the electrode which is connected to the transistor and adjoins the lower oxide layer having a relatively great thickness, and each logic region comprising at least one transistor in the transition region between silicon substrate and lower oxide layer, which transistor is connected to an electrode on the topside of the upper oxide layer via a contact hole, which is filled with metal, in the lower oxide layer and the upper oxide layer. According to the invention, it is provided that between the capacitors of the memory cells and the contact holes in the logic regions, level compensation between the topology of the memory cells and of the logic regions is created by dummy structures.
摘要翻译：本发明提供了具有随机存取的半导体存储器组件，其还具有分为存储单元和逻辑区域的结构，并且具有布置在硅衬底上的低氧化物层和布置在低氧化物层上的上氧化层，每个存储单元包括在硅衬底和低氧化物层之间的过渡区域中的至少一个晶体管和在低氧化物层和上部氧化物层之间的过渡区域中的电容器，该电容器通过填充有金属的接触孔连接到晶体管，在所述低氧化物层中并且包括布置在两个电极之间的铁电体，所述电极连接到所述晶体管并且邻接所述低氧化物层具有相对较大的厚度，并且每个逻辑区域包括在硅衬底之间的过渡区域中的至少一个晶体管和低氧化物层，该晶体管连接到u的顶部上的电极通过在低氧化物层和上部氧化物层中填充有金属的接触孔来形成氧化皮层。根据本发明，提供在存储单元的电容器和逻辑区域中的接触孔之间，通过虚拟结构产生存储器单元的拓扑和逻辑区域之间的电平补偿。

8. 发明授权

US06303391B1 Low temperature chemical vapor deposition process for forming bismuth-containing ceramic films useful in ferroelectric memory devices 失效
标题翻译：用于形成用于铁电存储器件的含铋陶瓷膜的低温化学气相沉积工艺
公开(公告)号：US06303391B1
公开(公告)日：2001-10-16
申请号：US08975087
申请日：1997-11-20
申请人： Frank S. Hintermaier , Christine Dehm , Wolfgang Hoenlein , Peter C. Van Buskirk , Jeffrey F. Roeder , Bryan C. Hendrix , Thomas H. Baum , Debra A. Desrochers
发明人： Frank S. Hintermaier , Christine Dehm , Wolfgang Hoenlein , Peter C. Van Buskirk , Jeffrey F. Roeder , Bryan C. Hendrix , Thomas H. Baum , Debra A. Desrochers
IPC分类号： H01L2100
CPC分类号： H01L21/31691 , C23C16/40 , C23C16/56
摘要： A low temperature CVD process using a tris (&bgr;-diketonate) bismuth precursor for deposition of bismuth ceramic thin films suitable for integration to fabricate ferroelectric memory devices. Films of amorphous SBT can be formed by CVD and then ferroannealed to produce films with Aurivillius phase composition having superior ferroelectric properties suitable for manufacturing high density FRAMs.
摘要翻译：使用三（β-二酮）铋前体的低温CVD方法，用于沉积适合于制造铁电存储器件的一体化的铋陶瓷薄膜。可以通过CVD形成非晶态SBT膜，然后用铁退镀以制备具有优异的铁电性能的Aurivillius相组成的膜，适用于制造高密度FRAM。

9. 发明授权

US07049628B2 Semiconductor memory cell and semiconductor memory device 有权
公开(公告)号：US07049628B2
公开(公告)日：2006-05-23
申请号：US10395428
申请日：2003-03-24
申请人： Günter Schmid , Marcus Halik , Hagen Klauk , Christine Dehm , Thomas Haneder , Thomas Mikolajick
发明人： Günter Schmid , Marcus Halik , Hagen Klauk , Christine Dehm , Thomas Haneder , Thomas Mikolajick
IPC分类号： H01L35/24
CPC分类号： G11C13/0014 , B82Y10/00 , G11C11/5664 , G11C13/0016 , H01L27/101 , H01L29/78391
摘要： The semiconductor memory cell is characterized in that at least one modulation region is provided between a first gate electrode of the gate electrode configuration and the insulation region, and in that the modulation region has or is formed from a material or modulation material having electrical and/or further material properties that can be modulated in a controllable manner between at least two states in such a way that, in accordance with these states of the modulation material or of the modulation region, the channel region can be influenced electromagnetically, in particular for a given electrical potential difference between the first gate electrode and the source/drain regions.

10. 发明授权

US5674769A Process for forming deep trench DRAMs with sub-groundrule gates 失效
标题翻译：用次基底栅形成深沟槽DRAM的工艺
公开(公告)号：US5674769A
公开(公告)日：1997-10-07
申请号：US665183
申请日：1996-06-14
申请人： Johann Alsmeier , Christine Dehm , Erwin Hammerl , Reinhard J. Stengl
发明人： Johann Alsmeier , Christine Dehm , Erwin Hammerl , Reinhard J. Stengl
IPC分类号： H01L29/41 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10876 , H01L27/10823
摘要： A method of fabricating sub-GR gates in a deep trench DRAM cell. The method comprises depositing, removing, and selectively etching a plurality of layers which include sacrificial spacers, liners, masking, and resist layers of both semiconducting and non-semiconducting materials on a semiconductor substrate according to specific process flows designed to circumvent the problems associated with prior art sub-GR processes. The method represents an improvement on standard gate conductor processes and provides a device which achieves an up to now unachieved decoupling of channel doping and junction doping.
摘要翻译：在深沟槽DRAM单元中制造子GR栅极的方法。该方法包括在半导体衬底上沉积，去除和选择性地蚀刻包括半导体衬底上的半导体和非半导体材料的牺牲隔离物，衬垫，掩模和抗蚀剂层的多个层，所述特定工艺流程旨在规避与现有技术的子GR过程。该方法代表了对标准栅极导体工艺的改进，并且提供了实现通道掺杂和结掺杂的迄今未达成的去耦的器件。

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