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    • 1. 发明授权
    • Wire forming method for semiconductor device
    • 半导体器件的成线方法
    • US5604156A
    • 1997-02-18
    • US560913
    • 1995-11-20
    • U-in ChungJae-duk KimChang-ki Hong
    • U-in ChungJae-duk KimChang-ki Hong
    • H01L21/28H01L21/304H01L21/306H01L21/3205H01L21/768H01L23/532H01L21/44
    • H01L21/76831H01L21/76807H01L21/76843H01L21/76877H01L23/53238H01L23/53257H01L23/5329H01L2924/0002
    • A wire forming method for a semiconductor device includes the steps of depositing an insulation material on a semiconductor substrate and patterning the insulation material to form a first insulation layer, forming a lower capping layer on the first insulation layer, etching the lower capping layer and the first insulation layer to form a first contact hole that exposes a first part of the semiconductor substrate, forming a wire layer over the capping layer and the first part of the semiconductor substrate, performing a chemical and mechanical polishing (CMP) process with respect to the wire layer and the lower capping layer to expose the first insulation layer, forming a second insulation layer over the wire layer and the first insulation layer, and etching the first and second insulation layers to form a second contact hole that exposes a second part of the semiconductor substrate. The wire forming method can prevent the lifting of the wire layer, the splitting of the lower insulation layer, and the formation of a protrusion n the second contact hole.
    • 一种用于半导体器件的线形成方法包括以下步骤:在半导体衬底上沉积绝缘材料并图案化绝缘材料以形成第一绝缘层,在第一绝缘层上形成下覆盖层,蚀刻下封盖层和 第一绝缘层以形成暴露半导体衬底的第一部分的第一接触孔,在覆盖层和半导体衬底的第一部分上方形成引线层,对相对于第二绝缘层进行化学和机械抛光(CMP)处理 线层和下覆盖层以暴露第一绝缘层,在导线层和第一绝缘层上形成第二绝缘层,并蚀刻第一和第二绝缘层以形成第二接触孔,其暴露第二绝缘层的第二部分 半导体衬底。 线形成方法可以防止线层的提升,下绝缘层的分离,以及在第二接触孔处形成突起。