专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20070066018A1 METHODS OF FABRICATING VERTICAL CHANNEL FIELD EFFECT TRANSISTORS HAVING INSULATING LAYERS THEREON 有权
标题翻译：制造具有绝缘层的垂直通道场效应晶体管的方法
公开(公告)号：US20070066018A1
公开(公告)日：2007-03-22
申请号：US11556804
申请日：2006-11-06
申请人： Tai-Su Park , Eui-Joon Yoon , U-In Chung , Si-Young Choi , Jong-Ho Lee
发明人： Tai-Su Park , Eui-Joon Yoon , U-In Chung , Si-Young Choi , Jong-Ho Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/7851 , H01L29/66795 , H01L29/7854
摘要： A method of forming a field effect transistor includes forming a vertical channel protruding from a substrate including a source/drain region junction between the vertical channel and the substrate, and forming an insulating layer extending on a side wall of the vertical channel toward the substrate to beyond the source/drain region junction. The method may also include forming a nitride layer extending on the side wall away from the substrate to beyond the insulating layer, forming a second insulating layer extending on the side wall that is separated from the channel by the nitride layer, and forming a gate electrode extending on the side wall toward the substrate to beyond the source/drain region junction.
摘要翻译：形成场效应晶体管的方法包括形成从包括垂直沟道和衬底之间的源极/漏极区域的衬底突出的垂直沟道，并且形成在垂直沟道的侧壁上朝向衬底延伸的绝缘层，超出源/漏区结。该方法还可以包括在侧壁上形成远离衬底延伸到绝缘层的氮化物层，形成在侧壁上延伸的第二绝缘层，所述第二绝缘层通过氮化物层从沟道分离，并形成栅电极在侧壁上朝向衬底延伸超过源/漏区结。

2. 发明授权

US5604156A Wire forming method for semiconductor device 失效
标题翻译：半导体器件的成线方法
公开(公告)号：US5604156A
公开(公告)日：1997-02-18
申请号：US560913
申请日：1995-11-20
申请人： U-in Chung , Jae-duk Kim , Chang-ki Hong
发明人： U-in Chung , Jae-duk Kim , Chang-ki Hong
IPC分类号： H01L21/28 , H01L21/304 , H01L21/306 , H01L21/3205 , H01L21/768 , H01L23/532 , H01L21/44
CPC分类号： H01L21/76831 , H01L21/76807 , H01L21/76843 , H01L21/76877 , H01L23/53238 , H01L23/53257 , H01L23/5329 , H01L2924/0002
摘要： A wire forming method for a semiconductor device includes the steps of depositing an insulation material on a semiconductor substrate and patterning the insulation material to form a first insulation layer, forming a lower capping layer on the first insulation layer, etching the lower capping layer and the first insulation layer to form a first contact hole that exposes a first part of the semiconductor substrate, forming a wire layer over the capping layer and the first part of the semiconductor substrate, performing a chemical and mechanical polishing (CMP) process with respect to the wire layer and the lower capping layer to expose the first insulation layer, forming a second insulation layer over the wire layer and the first insulation layer, and etching the first and second insulation layers to form a second contact hole that exposes a second part of the semiconductor substrate. The wire forming method can prevent the lifting of the wire layer, the splitting of the lower insulation layer, and the formation of a protrusion n the second contact hole.
摘要翻译：一种用于半导体器件的线形成方法包括以下步骤：在半导体衬底上沉积绝缘材料并图案化绝缘材料以形成第一绝缘层，在第一绝缘层上形成下覆盖层，蚀刻下封盖层和第一绝缘层以形成暴露半导体衬底的第一部分的第一接触孔，在覆盖层和半导体衬底的第一部分上方形成引线层，对相对于第二绝缘层进行化学和机械抛光（CMP）处理线层和下覆盖层以暴露第一绝缘层，在导线层和第一绝缘层上形成第二绝缘层，并蚀刻第一和第二绝缘层以形成第二接触孔，其暴露第二绝缘层的第二部分半导体衬底。线形成方法可以防止线层的提升，下绝缘层的分离，以及在第二接触孔处形成突起。

3. 发明授权

US08803266B2 Storage nodes, magnetic memory devices, and methods of manufacturing the same 有权
标题翻译：存储节点，磁存储器件及其制造方法
公开(公告)号：US08803266B2
公开(公告)日：2014-08-12
申请号：US13313361
申请日：2011-12-07
申请人： Kwang-seok Kim , U-In Chung , Jai-kwang Shin , Kee-won Kim , Sung-chul Lee , Ung-hwan Pi
发明人： Kwang-seok Kim , U-In Chung , Jai-kwang Shin , Kee-won Kim , Sung-chul Lee , Ung-hwan Pi
IPC分类号： H01L29/72
CPC分类号： H01L27/228 , G11C11/161 , H01L29/82 , H01L43/08 , H01L43/12
摘要： A storage node of a magnetic memory device includes: a lower magnetic layer, a tunnel barrier layer formed on the lower magnetic layer, and a free magnetic layer formed on the tunnel barrier. The free magnetic layer has a magnetization direction that is switchable in response to a spin current. The free magnetic layer has a cap structure surrounding at least one material layer on which the free magnetic layer is formed.
摘要翻译：磁存储器件的存储节点包括：下磁层，形成在下磁层上的隧道势垒层和形成在隧道势垒上的自由磁层。自由磁性层具有响应于自旋电流而可切换的磁化方向。自由磁性层具有围绕形成有自由磁性层的至少一个材料层的盖结构。

4. 发明申请

US20130320286A1 SWITCHING ELEMENTS AND DEVICES, MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME 审中-公开
标题翻译：切换元件和设备，存储器件及其制造方法
公开(公告)号：US20130320286A1
公开(公告)日：2013-12-05
申请号：US13905822
申请日：2013-05-30
申请人： Dong-soo LEE , Myoung-jae LEE , U-in CHUNG
发明人： Dong-soo LEE , Myoung-jae LEE , U-in CHUNG
IPC分类号： H01L45/00
CPC分类号： H01L45/145 , H01L27/2427 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/14 , H01L45/146 , H01L45/1625 , H01L45/1641
摘要： A switching element includes: a first electrode; a second electrode; and a silicon-containing chalconitride layer between the first electrode and the second electrode. A switching device includes: a threshold switch material layer between a first electrode and a second electrode. The threshold switch material layer includes a cationic metal element, a chalcogen element, a silicon element and a nitrogen element. A memory device include: a plurality of first wirings arranged in parallel with each other; a plurality of second wirings crossing the first wirings, and arranged in parallel with each other; and a memory cell formed at each intersection of the plurality of first wirings and the plurality of second wirings. The memory cell includes a laminate having a silicon-containing chalconitride layer, an intermediate electrode, and a memory layer.
摘要翻译：开关元件包括：第一电极; 第二电极; 以及在所述第一电极和所述第二电极之间的含硅的仲氮化物层。开关装置包括：第一电极和第二电极之间的阈值开关材料层。阈值开关材料层包括阳离子金属元素，硫属元素，硅元素和氮元素。存储器件包括：彼此平行布置的多个第一布线; 多个第二布线，穿过第一配线，彼此平行布置; 以及形成在所述多个第一布线和所述多个第二布线的每个交叉点处的存储单元。存储单元包括具有含硅的恰氮氮化物层，中间电极和存储层的层压体。

5. 发明申请

US20130241520A1 POWER MANAGEMENT CHIPS AND POWER MANAGEMENT DEVICES INCLUDING THE SAME 有权
标题翻译：电源管理卡和电源管理设备，包括它们
公开(公告)号：US20130241520A1
公开(公告)日：2013-09-19
申请号：US13588488
申请日：2012-08-17
申请人： Ho-jung KIM , Jai-kwang SHIN , U-in CHUNG , Hyun-sik CHOI
发明人： Ho-jung KIM , Jai-kwang SHIN , U-in CHUNG , Hyun-sik CHOI
IPC分类号： G05F3/02
CPC分类号： H03K17/687 , H01L21/8213 , H01L21/8252 , H01L29/1608 , H01L29/2003 , H01L29/7787 , H02M1/08 , H02M3/337 , H03K2217/0036 , H03K2217/0063 , H03K2217/0072 , H03K2217/0081
摘要： A power management chip and a power management device including the power management chip. The power management chip includes at least one power switch and a driver unit for generating a driving signal for driving the at least one power switch, the driver unit including one or more circuit units formed on a same substrate as the at least one power switch.
摘要翻译：电源管理芯片和包括电源管理芯片的电源管理装置。电源管理芯片包括至少一个电源开关和驱动器单元，用于产生用于驱动至少一个电源开关的驱动信号，所述驱动器单元包括形成在与所述至少一个电源开关相同的基板上的一个或多个电路单元。

6. 发明申请

US20110108704A1 Image sensors and methods of operating the same 有权
标题翻译：图像传感器及其操作方法
公开(公告)号：US20110108704A1
公开(公告)日：2011-05-12
申请号：US12805723
申请日：2010-08-17
申请人： Ho-jung Kim , U-in Chung , Jai-kwang Shin , Sun-il Kim , I-hun Song , Chang-jung Kim , Sang-hun Jeon
发明人： Ho-jung Kim , U-in Chung , Jai-kwang Shin , Sun-il Kim , I-hun Song , Chang-jung Kim , Sang-hun Jeon
IPC分类号： H01L27/146 , H01L31/09 , H01L31/101 , H01L31/102
CPC分类号： H04N9/045 , H01L27/14643 , H04N5/3745
摘要： Image sensors and methods of operating the same. An image sensor includes a pixel array including a plurality of pixels. Each of the plurality of pixels includes a photo sensor, the voltage-current characteristics of which vary according to energy of incident light, and that generates a sense current determined by the energy of the incident light; a reset unit that is activated to generate a reference current, according to a reset signal for resetting at least one of the plurality of pixels; and a conversion unit that converts the sense current and the reference current into a sense voltage and a reference voltage, respectively.
摘要翻译：图像传感器及其操作方法。图像传感器包括包括多个像素的像素阵列。多个像素中的每一个包括光电传感器，其电压 - 电流特性根据入射光的能量而变化，并且产生由入射光的能量确定的感测电流; 根据用于复位所述多个像素中的至少一个的复位信号，被激活以产生参考电流的复位单元; 以及转换单元，其将感测电流和参考电流分别转换为感测电压和参考电压。

7. 发明授权

US06391714B2 Method for fabricating a capacitor in a semiconductor memory device 失效
标题翻译：在半导体存储器件中制造电容器的方法
公开(公告)号：US06391714B2
公开(公告)日：2002-05-21
申请号：US09738296
申请日：2000-12-18
申请人： Chul-Ho Shin , U In Chung
发明人： Chul-Ho Shin , U In Chung
IPC分类号： H01L218242
CPC分类号： H01L28/84 , H01L21/3143 , H01L27/10814 , H01L27/10855 , Y10T29/41
摘要： A method for making a capacitor of a semiconductor memory device capable of providing increased capacitance without degraded resolution, as well as without the removal of any interlayer insulation layers upon formation of a lower electrode for the capacitor, wherein after formation of an access transistor on a semiconductor substrate, a first interlayer insulation layer for planarization of a surface of the semiconductor substrate and a second interlayer insulation layer for formation of the capacitor lower electrode are formed. After formation of an opening for exposing a part of an impurity diffusion region of the access transistor by etching a part of the first and second interlayer insulating layers, a spacer is formed within the opening. Further, after deposition of a conductive layer for the capacitor lower electrode onto a surface of the substrate, a planarization process is carried out until a part of the upper surface of the spacer is exposed. Finally, after removal of the exposed spacer, the dielectric layer and a conductive layer for the upper electrode of the capacitor are formed in sequence. The method does not require any additional insulation layer evaporation process, since the interlayer insulation layer for formation of the reverse storage electrode could be used for formation of a gate contact of a logic region, without removal. Consequently, simplification of fabrication process for a capacitor is achieved.
摘要翻译：一种用于制造半导体存储器件的电容器的方法，其能够提供增加的电容而不降低分辨率，以及在形成用于电容器的下电极时不去除任何层间绝缘层，其中在形成存取晶体管半导体衬底，用于使半导体衬底的表面平坦化的第一层间绝缘层和用于形成电容器下电极的第二层间绝缘层。在形成用于通过蚀刻第一和第二层间绝缘层的一部分来暴露存取晶体管的一部分杂质扩散区的开口，在开口内形成间隔物。此外，在将电容器下电极的导电层沉积到基板的表面上之后，进行平坦化处理直到间隔件的上表面的一部分露出。最后，在去除暴露的间隔物之后，依次形成电介质层和用于电容器的上电极的导电层。该方法不需要任何额外的绝缘层蒸发工艺，因为用于形成反向存储电极的层间绝缘层可用于形成逻辑区域的栅极接触而不去除。因此，实现了电容器制造工艺的简化。

8. 发明授权

US5656337A Method of forming a dielectric layer 失效
标题翻译：形成电介质层的方法
公开(公告)号：US5656337A
公开(公告)日：1997-08-12
申请号：US296931
申请日：1994-08-31
申请人： In-Seon Park , Myoung-Bum Lee , Chang-Gee Hong , Chang-Gyu Kim , U-In Chung
发明人： In-Seon Park , Myoung-Bum Lee , Chang-Gee Hong , Chang-Gyu Kim , U-In Chung
IPC分类号： H01L21/205 , C23C16/02 , C23C16/40 , C23C16/44 , H01L21/31 , H01L21/3105 , H01L21/316 , H01L21/3205 , H05H1/00
CPC分类号： H01L21/02164 , C23C16/0245 , C23C16/402 , C23C16/44 , H01L21/02271 , H01L21/02315 , H01L21/31051 , H01L21/31608
摘要： A deposition rate of a dielectric material is varied with the electrical polarity of an underlying layer to obtain excellent deposition and planarization characteristics. A conductive layer and the underlying dielectric are surface-treated to have different electrical polarities so that the dielectric is formed by using the difference of deposition rates of the dielectric material between that on the conductive layer and that on the underlying dielectric. A CVD apparatus having a DC power source connected between a susceptor and a gas injection portion thereof is provided. The deposition and planarization can be performed at low temperatures and are simplified in process.
摘要翻译：介电材料的沉积速率随着下层的电极性而变化，以获得优异的沉积和平坦化特性。导电层和下面的电介质被表面处理以具有不同的电极性，使得通过使用电介质材料在导电层上和在下面的电介质之间的沉积速率的差异来形成电介质。提供了一种具有连接在基座和其气体注入部分之间的直流电源的CVD装置。沉积和平坦化可以在低温下进行并且在工艺上被简化。

9. 发明授权

US09525410B2 Power management chips and power management devices including the same 有权
标题翻译：电源管理芯片和电源管理设备包括相同
公开(公告)号：US09525410B2
公开(公告)日：2016-12-20
申请号：US13588488
申请日：2012-08-17
申请人： Ho-jung Kim , Jai-kwang Shin , U-in Chung , Hyun-sik Choi
发明人： Ho-jung Kim , Jai-kwang Shin , U-in Chung , Hyun-sik Choi
IPC分类号： H03K17/687 , H02M1/08 , H02M3/337 , H01L29/778 , H01L29/16 , H01L29/20 , H01L21/82 , H01L21/8252
CPC分类号： H03K17/687 , H01L21/8213 , H01L21/8252 , H01L29/1608 , H01L29/2003 , H01L29/7787 , H02M1/08 , H02M3/337 , H03K2217/0036 , H03K2217/0063 , H03K2217/0072 , H03K2217/0081
摘要： A power management chip and a power management device including the power management chip. The power management chip includes at least one power switch and a driver unit for generating a driving signal for driving the at least one power switch, the driver unit including one or more circuit units formed on a same substrate as the at least one power switch.
摘要翻译：电源管理芯片和包括电源管理芯片的电源管理装置。电源管理芯片包括至少一个电源开关和驱动器单元，用于产生用于驱动至少一个电源开关的驱动信号，所述驱动器单元包括形成在与所述至少一个电源开关相同的基板上的一个或多个电路单元。

10. 发明授权

US08742478B2 Graphene transistor having air gap, hybrid transistor having the same, and methods of fabricating the same 有权
标题翻译：具有气隙的石墨烯晶体管，具有相同的混合晶体管及其制造方法
公开(公告)号：US08742478B2
公开(公告)日：2014-06-03
申请号：US13667097
申请日：2012-11-02
申请人： Hyun-jong Chung , U-in Chung , Ki-nam Kim
发明人： Hyun-jong Chung , U-in Chung , Ki-nam Kim
IPC分类号： H01L29/76
CPC分类号： H01L29/772 , B82Y40/00 , H01L21/8232 , H01L27/0688 , H01L29/1606 , H01L29/41758 , H01L29/518 , H01L29/778 , H01L29/78606 , H01L29/78684 , Y10S977/734 , Y10S977/842 , Y10S977/938
摘要： A graphene transistor includes: a gate electrode on a substrate; a gate insulating layer on the gate electrode; a graphene channel on the gate insulating layer; a source electrode and a drain electrode on the graphene channel, the source and drain electrode being separate from each other; and a cover that covers upper surfaces of the source electrode and the drain electrode and forms an air gap above the graphene channel between the source electrode and the drain electrode.
摘要翻译：石墨烯晶体管包括：基板上的栅电极; 栅电极上的栅极绝缘层; 栅极绝缘层上的石墨烯通道; 在石墨烯通道上的源极和漏极，源极和漏极彼此分离; 以及覆盖源电极和漏电极的上表面并在源电极和漏电极之间的石墨烯通道上方形成气隙的盖。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式