专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5594279A Semiconductor device having shield wiring for noise suppression 失效
标题翻译：具有用于噪声抑制的屏蔽布线的半导体器件
公开(公告)号：US5594279A
公开(公告)日：1997-01-14
申请号：US149876
申请日：1993-11-10
申请人： Yutaka Itou , Hidetoshi Iwai , Toshiyuki Sakuta , Takumi Nasu , Tomohiro Suzuki
发明人： Yutaka Itou , Hidetoshi Iwai , Toshiyuki Sakuta , Takumi Nasu , Tomohiro Suzuki
IPC分类号： H01L23/52 , H01L21/3205 , H01L23/522 , H01L23/552 , H01L23/48
CPC分类号： H01L24/06 , H01L23/5225 , H01L23/552 , H01L24/05 , H01L24/48 , H01L24/49 , H01L2224/04042 , H01L2224/05554 , H01L2224/05556 , H01L2224/05624 , H01L2224/06136 , H01L2224/48091 , H01L2224/48247 , H01L2224/48253 , H01L2224/4826 , H01L2224/48464 , H01L2224/49113 , H01L2224/49175 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01023 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/19041 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025
摘要： A semiconductor device in which shield wiring is arranged between the semiconductor substrate and the power source wiring for supplying the power source potential or ground potential. Noise, as represented by variations in the potential of the semiconductor substrate, is substantially prevented from transferring to the aforementioned power source wiring by the shield wiring. In one aspect, shield wiring 1 is arranged between Vss wiring for supplying potential to the various circuits on the semiconductor substrate and substrate 7. This shield wiring 1 is connected to grounding lead frame 18 via M1 intra-chip wiring 4, M2 intra-chip wiring 5, connecting part 40, bonding pad 3 and bonding wire 8. Since the coupling impedance between shield wiring 1 and substrate 7 (due almost solely to the electrostatic capacitance Css) is large, and coupling impedance between Vss wiring 2 and substrate 7 (due almost solely to the junction capacitance D) is low, the noise caused by variations in the potential of substrate 7 is transferred to shield wiring 1, while it is not appreciably transferred to Vss wiring 2.
摘要翻译：一种半导体器件，其中屏蔽布线布置在半导体衬底和用于提供电源电位或接地电位的电源布线之间。基本上防止了由半导体衬底的电位变化所表示的噪声通过屏蔽布线转移到上述电源布线。在一个方面，屏蔽布线1布置在用于向半导体衬底和衬底7上的各种电路供电的Vss布线之间。该屏蔽布线1经由M1片内布线4，M2片内连接到接地引线框架18 布线5，连接部40，接合焊盘3和接合线8.由于屏蔽布线1和基板7之间的耦合阻抗（几乎完全相当于静电电容Css），所以Vss布线2和基板7 由于几乎完全由结电容D）导致的，基板7的电位的变化引起的噪声被传送到屏蔽布线1，而不明显地转移到Vss布线2。

2. 发明授权

US5453959A Semiconductor memory device having a self-refreshing control circuit 失效
标题翻译：具有自刷新控制电路的半导体存储器件
公开(公告)号：US5453959A
公开(公告)日：1995-09-26
申请号：US220249
申请日：1994-03-30
申请人： Toshiyuki Sakuta , Tomohiro Suzuki
发明人： Toshiyuki Sakuta , Tomohiro Suzuki
IPC分类号： G11C11/403 , G11C11/406 , G11C7/00
CPC分类号： G11C11/406
摘要： A semiconductor memory device capable of a self-refreshing operation with a refresh-initiation signal generated in the memory device has a self-refreshing control circuit. A self-refreshing operation is automatically effected, without externally supplied clock signals, with a specific refreshing cycle having an internally set mode entry time period, a burst refresh time period and an internally set pause time period. These time periods are detected by a single counter circuit arranged to count pulses produced from a basic clock pulse signal generated by an oscillator. The burst refreshing is effected with the pulses contained in a pulse signal generated in synchronization with the basic clock pulse signal from the oscillator.
摘要翻译：能够在存储装置中产生的刷新启动信号进行自刷新操作的半导体存储器件具有自刷新控制电路。在没有外部提供的时钟信号的情况下，自动刷新操作具有具有内部设定模式进入时间段，突发刷新时间周期和内部设置的暂停时间段的特定刷新周期。这些时间周期通过一个单个计数器电路来检测，该计数器电路被布置成对由振荡器产生的基本时钟脉冲信号产生的脉冲进行计数。脉冲串刷新通过与来自振荡器的基本时钟脉冲信号同步产生的脉冲信号中包含的脉冲来实现。

3. 发明授权

US5633825A Voltage generating circuit in semiconductor integrated circuit 失效
标题翻译：半导体集成电路中的电压产生电路
公开(公告)号：US5633825A
公开(公告)日：1997-05-27
申请号：US651515
申请日：1996-05-22
申请人： Toshiyuki Sakuta , Tomohiro Suzuki , Yuriko Iizuka
发明人： Toshiyuki Sakuta , Tomohiro Suzuki , Yuriko Iizuka
IPC分类号： G11C11/407 , G11C5/14 , G11C11/401 , G11C7/00
CPC分类号： G11C5/145 , G11C5/143
摘要： A voltage generating circuit in a semiconductor integrated circuit driven by two sorts of power supply voltages, includes a unit for generating plural sorts of signals; a unit for selecting one of the plural sorts of signals in response to an operation mode of the semiconductor integrated circuit; and a pumping unit for producing either a first predetermined voltage higher than the high power supply voltage among the two sorts of power supply voltages, or a second predetermined voltage lower than the low power supply voltage by a pumping operation based upon the signal selected by the selecting unit.
摘要翻译：由两种电源电压驱动的半导体集成电路中的电压产生电路包括用于产生多种信号的单元; 用于响应半导体集成电路的操作模式选择多种信号之一的单元; 以及泵送单元，用于在两种电源电压之中产生高于高电源电压的第一预定电压，或者通过基于由所述电源电压选择的信号的泵送操作产生低于低电源电压的第二预定电压选择单位。

4. 发明授权

US5534817A Voltage generating circuit 失效
标题翻译：电压发生电路
公开(公告)号：US5534817A
公开(公告)日：1996-07-09
申请号：US292538
申请日：1994-08-18
申请人： Tomohiro Suzuki , Toshiyuki Sakuta
发明人： Tomohiro Suzuki , Toshiyuki Sakuta
IPC分类号： G01R19/00 , G05F3/24 , G05F3/26 , G11C11/407 , H03G3/02 , H03K19/00 , G05F3/02
CPC分类号： G05F3/247 , G05F3/262
摘要： A voltage generating circuit for providing a prescribed voltage, such as 1/2V.sub.DD of the power source voltage V.sub.DD, wherein the capacity of the current and the response time of the voltage generating circuit is significantly improved. When the output voltage V.sub.OUT of the voltage generating circuit drops suddenly from a reference value 1/2V.sub.DD and goes below the lower limit of an allowable voltage level VM-, an n-type MOS transistor MN5A of an output voltage detecting circuit 14 turns on. The potential of the gate terminal for a p-type MOS transistor MP6A in a digital output circuit 16 is pulled to the level of the output voltage V.sub.OUT via the transistor MN5A that was turned on, and said p-type MOS transistor MP6A is turned on in the saturated area more or less perfectly. By virtue of a large amount of current flowing to the output side of a terminal side, namely the load circuit side, at an appropriate voltage from a power source terminal 18 via p-type MOS transistor MP6A which was turned on in the saturated area, a reduction in output voltage V.sub.OUT is stopped quickly and the output voltage is restored to the normal level within a short time.
摘要翻译：一种用于提供诸如电源电压VDD的1 / 2VDD的规定电压的电压产生电路，其中电压产生电路的电流和响应时间的容量显着提高。当电压产生电路的输出电压VOUT从参考值1 / 2VDD突然下降并且低于容许电压电平VM-的下限时，输出电压检测电路14的n型MOS晶体管MN5A导通。数字输出电路16中的p型MOS晶体管MP6A的栅极端子的电位经导通的晶体管MN5A被拉到输出电压VOUT的电平，并且所述p型MOS晶体管MP6A导通在饱和区域或多或少完美。由于在饱和区域中经由p型MOS晶体管MP6A从电源端子18流过至端子侧（即负载电路侧）的输出侧的大量电流，输出电压VOUT的降低快速停止，并且输出电压在短时间内恢复到正常水平。

5. 发明授权

US5528538A Voltage generating circuit in semiconductor integrated circuit 失效
标题翻译：半导体集成电路中的电压产生电路
公开(公告)号：US5528538A
公开(公告)日：1996-06-18
申请号：US84628
申请日：1993-06-30
申请人： Toshiyuki Sakuta , Tomohiro Suzuki , Yuriko Iizuka
发明人： Toshiyuki Sakuta , Tomohiro Suzuki , Yuriko Iizuka
IPC分类号： G11C11/407 , G11C5/14 , G11C11/401 , G11C7/00
CPC分类号： G11C5/145 , G11C5/143
摘要： A voltage generating circuit in a semiconductor integrated circuit driven by two sorts of power supply voltages, includes a unit for generating plural sorts of signals; a unit for selecting one of the plural sorts of signals in response to an operation mode of the semiconductor integrated circuit; and a pumping unit for producing either a first predetermined voltage higher than the high power supply voltage among the two sorts of power supply voltages, or a second predetermined voltage lower than the low power supply voltage by a pumping operation based upon the signal selected by the selecting unit.
摘要翻译：由两种电源电压驱动的半导体集成电路中的电压产生电路包括用于产生多种信号的单元; 用于响应半导体集成电路的操作模式选择多种信号之一的单元; 以及泵送单元，用于在两种电源电压之中产生高于高电源电压的第一预定电压，或者通过基于由所述电源电压选择的信号的泵送操作产生低于低电源电压的第二预定电压选择单位。

6. 发明授权

US5514905A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US5514905A
公开(公告)日：1996-05-07
申请号：US329824
申请日：1994-10-27
申请人： Toshiyuki Sakuta , Kazuyuki Miyazawa , Satoshi Oguchi , Aizo Kaneda , Masao Mitani , Shozo Nakamura , Kunihiko Nishi , Gen Murakami
发明人： Toshiyuki Sakuta , Kazuyuki Miyazawa , Satoshi Oguchi , Aizo Kaneda , Masao Mitani , Shozo Nakamura , Kunihiko Nishi , Gen Murakami
IPC分类号： H01L23/29 , H01L23/495 , H01L23/48 , H01L29/41
CPC分类号： H01L23/4951 , H01L23/293 , H01L2224/05599 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/48599 , H01L24/45 , H01L24/48 , H01L2924/00014 , H01L2924/01014 , H01L2924/01057 , H01L2924/01079 , H01L2924/01082 , H01L2924/10253 , H01L2924/14
摘要： A semiconductor device is provided in connection with a semiconductor chip which has a plurality of bonding pads at a part corresponding to a centrally located area of the front or first main surface thereof, an organic insulator film which overlies the semiconductor chip and which has an opening in correspondence with the bonding pads, a plurality of leads which overly the organic insulator film, and a molding resin with which these constituents are sealed or packaged.
摘要翻译：半导体器件与半导体芯片相连，该半导体芯片在与其前表面或第一主表面的中心位置相对应的部分处具有多个接合焊盘;半导体芯片，覆盖在半导体芯片上并具有开口与接合焊盘相对应，多个有机绝缘膜上的引线以及密封或封装这些成分的成型树脂。

7. 再颁专利

USRE37539E1 Sealed stacked arrangement of semiconductor devices 有权
标题翻译：密封堆叠布置的半导体器件
公开(公告)号：USRE37539E1
公开(公告)日：2002-02-05
申请号：US09471000
申请日：1999-12-23
申请人： Satoshi Oguchi , Masamichi Ishihara , Kazuya Ito , Gen Murakami , Ichiro Anjoh , Toshiyuki Sakuta , Yasunori Yamaguchi , Yasuhiro Kasama , Tetsu Udagawa , Eiji Momose , Youichi Matsuno , Hiroshi Satoh , Atsusi Nozoe
发明人： Satoshi Oguchi , Masamichi Ishihara , Kazuya Ito , Gen Murakami , Ichiro Anjoh , Toshiyuki Sakuta , Yasunori Yamaguchi , Yasuhiro Kasama , Tetsu Udagawa , Eiji Momose , Youichi Matsuno , Hiroshi Satoh , Atsusi Nozoe
IPC分类号： H01L2328
CPC分类号： H01L24/06 , G11C5/00 , G11C5/02 , G11C5/06 , H01L23/4951 , H01L23/49537 , H01L23/49575 , H01L24/45 , H01L24/48 , H01L24/49 , H01L25/0652 , H01L2224/0401 , H01L2224/04042 , H01L2224/05554 , H01L2224/06136 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/4554 , H01L2224/4569 , H01L2224/48091 , H01L2224/48137 , H01L2224/48247 , H01L2224/4826 , H01L2224/49171 , H01L2224/49175 , H01L2224/73215 , H01L2224/73265 , H01L2225/1029 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01043 , H01L2924/01047 , H01L2924/01055 , H01L2924/01073 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A pair of DRAM chips 1A and 1B are mounted opposedly to each other with wiring means such as lead frames put therebetween, the lead frames being substantially integral with external terminals 3B. Then, these DRAM chips and lead frames are connected together by the conventional wire bonding method. Plural pairs of the thus-connected DRAM chips and lead frames are stacked and corresponding leads of the lead frames are connected in common to form a laminate. The plural DRAM chips thus mounted are activated selectively in accordance with a predetermined chip selection signal. Additionally, partial DRAM chips capable of partially functioning normally are combined together by utilizing the above chip mounting method to constitute a single DRAM package.
摘要翻译：一对DRAM芯片1A和1B通过诸如引线框架之间的布线装置彼此相对地安装，引线框架与外部端子3B基本上成一体。然后，这些DRAM芯片和引线框架通过常规的引线键合方法连接在一起。堆叠这样连接的DRAM芯片和引线框架的多对，引线框架的相应引线共同连接以形成层叠体。这样安装的多个DRAM芯片根据预定的芯片选择信号选择性地被激活。此外，通过利用上述芯片安装方法，能够正常部分正常工作的部分DRAM芯片组合在一起，以构成单个DRAM封装。

8. 发明授权

US5410507A Special mode control method for dynamic random access memory 失效
标题翻译：动态随机存取存储器的特殊模式控制方法
公开(公告)号：US5410507A
公开(公告)日：1995-04-25
申请号：US977212
申请日：1992-11-16
申请人： Masanori Tazunoki , Shigetoshi Sakomura , Toshitsugu Takekuma , Yutaka Ito , Kazuya Ito , Wataru Arakawa , Hidetoshi Iwai , Toshiyuki Sakuta , Masamichi Ishihara
发明人： Masanori Tazunoki , Shigetoshi Sakomura , Toshitsugu Takekuma , Yutaka Ito , Kazuya Ito , Wataru Arakawa , Hidetoshi Iwai , Toshiyuki Sakuta , Masamichi Ishihara
IPC分类号： G11C11/4074 , G11C11/4076 , G11C13/00
CPC分类号： G11C11/4076 , G11C11/4074
摘要： A dynamic RAM provided with a data retention mode intended for low power consumption is provided. In the data retention mode, the current supply capabilities of voltage generation circuits which generate decreased voltage, increased voltage, reference voltage, etc., are limited in the range in which information retention operation in memory cells can be maintained, and the number of selected memory mats in the data retention mode is increased with respect to that of memory mats selected in the normal read/write mode and refresh mode. Special modes such as the data retention mode are set by combining an address strobe signal and other control signals and dummy CBR refresh is executed to release the special mode.
摘要翻译：提供了具有旨在低功耗的数据保留模式的动态RAM。在数据保持模式下，产生电压降低，电压升高，参考电压等的电压产生电路的电流供应能力在保持存储器单元的信息保持操作的范围内被限制，并且所选择的数量相对于在正常读/写模式和刷新模式中选择的存储器垫，数据保持模式中的存储器垫增加。通过组合地址选通信号和其他控制信号来设置数据保持模式等特殊模式，执行虚拟CBR刷新以释放特殊模式。

9. 发明授权

US5309011A Wafer scale or full wafer memory system, packaging method thereof, and wafer processing method employed therein 失效
标题翻译：晶圆规模或全晶圆存储器系统，其封装方法和其中采用的晶片处理方法
公开(公告)号：US5309011A
公开(公告)日：1994-05-03
申请号：US960848
申请日：1992-10-14
申请人： Masanori Tazunoki , Hiromitsu Mishimagi , Makoto Homma , Toshiyuki Sakuta , Hisashi Nakamura , Keiji Sasaki , Minoru Enomoto , Toshihiko Satoh , Kunizo Sahara , Shigeo Kuroda , Kanji Otsuka , Masao Kawamura , Hinoko Kurosawa , Kazuya Ito
发明人： Masanori Tazunoki , Hiromitsu Mishimagi , Makoto Homma , Toshiyuki Sakuta , Hisashi Nakamura , Keiji Sasaki , Minoru Enomoto , Toshihiko Satoh , Kunizo Sahara , Shigeo Kuroda , Kanji Otsuka , Masao Kawamura , Hinoko Kurosawa , Kazuya Ito
IPC分类号： H01L23/14 , H01L23/32 , H01L23/538 , H01L25/065 , H01L25/07 , H01L27/02 , H01L27/10 , H01L27/15
CPC分类号： H01L23/147 , H01L23/32 , H01L23/5385 , H01L25/0652 , H01L25/073 , H01L2224/0401 , H01L2224/16225 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/48091 , H01L2224/48464 , H01L2224/48599 , H01L2224/48699 , H01L2224/73265 , H01L24/45 , H01L24/48 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01039 , H01L2924/01078 , H01L2924/01079 , H01L2924/10253 , H01L2924/12042 , H01L2924/1305 , H01L2924/14 , H01L2924/15174 , H01L2924/15312 , H01L2924/16152 , H01L2924/3025
摘要： To achieve higher packaging density and one wafer level for a full-sized wafer memory, or wafer-scale integration memory system, the wafers are vertically stacked with each other at a predetermined interval. A packaging technique is improved in such a way that a memory system layout can be precisely realized and a precise through hole can be formed. Moreover, other chips are fixed on the wafer so as to achieve furthermore the high packaging density.
摘要翻译：为了实现全尺寸晶片存储器或晶片级积分存储器系统的更高的封装密度和一个晶片级，晶片以预定的间隔彼此垂直堆叠。改进了封装技术，使得可以精确地实现存储器系统布局并且可以形成精确的通孔。此外，其他芯片固定在晶片上，从而进一步实现高封装密度。

10. 发明申请

US20050051898A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20050051898A1
公开(公告)日：2005-03-10
申请号：US10970027
申请日：2004-10-22
申请人： Toshiaki Minami , Toshiyuki Sakuta , Makoto Kuwata
发明人： Toshiaki Minami , Toshiyuki Sakuta , Makoto Kuwata
IPC分类号： H01L21/3205 , H01L21/768 , H01L21/82 , H01L21/822 , H01L23/485 , H01L23/52 , H01L23/528 , H01L27/04 , H01L23/48
CPC分类号： H01L24/05 , H01L23/5286 , H01L24/06 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/02166 , H01L2224/04042 , H01L2224/05554 , H01L2224/05624 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48463 , H01L2224/48624 , H01L2224/48724 , H01L2224/4943 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01027 , H01L2924/01029 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01076 , H01L2924/01079 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/10162 , H01L2924/1306 , H01L2924/14 , H01L2924/30105 , H01L2924/00014 , H01L2924/00
摘要： In a semiconductor device having the upmost wiring layer comprised of aluminum and the wiring layer immediately below it comprised of copper, the upmost wiring layer is made thicker than the wiring layer immediately below it so that the upmost wiring layer is lower in sheet resistance than the wiring layer immediately below it. Multiple ring power lines VR and pads PD are formed of the upmost wiring layer, and the ring power lines VR and the pads PD are connected respectively through power lines VLB1 of the upmost wiring layer. Consequently, the voltage drop on the power feed path from the pads PD to the ring power lines VR can be reduced and the power conduction from the pads PD to the ring power lines VR can be stabilized.
摘要翻译：在由铝构成的最上层布线层和由铜构成的正下方的布线层的半导体装置中，最上层的布线层比其正下方的布线层厚，因此最上层布线层的薄层电阻比接线层正下方。多个环形电源线VR和焊盘PD由最上面的布线层形成，并且环形电源线VR和焊盘PD分别通过最上面布线层的电力线VLB1连接。因此，可以减小从焊盘PD到环形电源线VR的馈电路径上的电压降，并且可以稳定从焊盘PD到环形电源线VR的电力传导。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式