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1. 发明授权

US4845670A Memory device using shift-register 失效
标题翻译：使用移位寄存器的存储器件
公开(公告)号：US4845670A
公开(公告)日：1989-07-04
申请号：US15348
申请日：1987-02-17
申请人： Toshio Nishimoto , Hideki Kawai , Masaru Fujii , Kiyoto Ohta
发明人： Toshio Nishimoto , Hideki Kawai , Masaru Fujii , Kiyoto Ohta
IPC分类号： G11C19/28 , G11C7/10 , G11C19/00
CPC分类号： G11C7/1036
摘要： In a memory device, a shift-register comprises a plurality of stages for transferring sequentially a pair of signals which have mutually opposite phases. Each stage has a comparator circuit which compares the pair of signals and generates a pair of fixed voltage signals. By this construction, high-speed operation of the memory device, low power consumptions, and high-capacity load driving are achieved.
摘要翻译：在存储装置中，移位寄存器包括用于顺序地传送具有相反相位的一对信号的多个级。每个级具有比较器电路，其比较该对信号并产生一对固定电压信号。通过这种结构，实现了存储器件的高速运行，低功耗和高容量负载驱动。

2. 发明授权

US4796224A Layout for stable high speed semiconductor memory device 失效
标题翻译：布局稳定的高速半导体存储器件
公开(公告)号：US4796224A
公开(公告)日：1989-01-03
申请号：US15349
申请日：1987-02-17
申请人： Hideki Kawai , Masaru Fujii , Kiyoto Ohta , Yoshikazu Maeyama
发明人： Hideki Kawai , Masaru Fujii , Kiyoto Ohta , Yoshikazu Maeyama
IPC分类号： G11C7/00 , G11C5/02 , G11C11/401 , G11C11/41
CPC分类号： G11C5/025
摘要： In a semiconductor memory device, a memory cell array is separated into at least two portions on a substrate, and a serial memory element, such as a shift register, and control signal lines are collectively disposed between the two memory cell array portions, and by this arrangement, the length of the control signal lines and data lines can be minimized so that the stray or parasitic capacitance is reduced, and a higher speed and stable operation of the device is thereby realized.
摘要翻译：在半导体存储装置中，将存储单元阵列分离为基板上的至少两个部分，并且诸如移位寄存器的串行存储元件和控制信号线共同设置在两个存储单元阵列部分之间，并且由通过这种布置，可以使控制信号线和数据线的长度最小化，从而减小杂散或寄生电容，从而实现装置的更高的速度和稳定的操作。

3. 发明授权

US4821299A Semiconductor integrated circuit device including shift register having substantially equalized wiring between stages thereof 失效
标题翻译：包括移位寄存器的半导体集成电路器件，其阶段之间布线基本相等
公开(公告)号：US4821299A
公开(公告)日：1989-04-11
申请号：US15347
申请日：1987-02-17
申请人： Hideki Kawai , Masaru Fujii , Kiyoto Ohta , Masahiko Sakagami
发明人： Hideki Kawai , Masaru Fujii , Kiyoto Ohta , Masahiko Sakagami
IPC分类号： G11C19/00 , G11C19/18 , G11C19/28 , H03K23/54
CPC分类号： G11C19/188
摘要： In a semiconductor integrated circuit device having at least one shift register, a plurality of 5 stages of the shift register are electrically connected in series, the 1st stage of said shift register is located in the closest position to the data input terminal, and other succeeding stages are sequentially and straightly located at intervals; the chain of the stages is folded at a particular stage, and further succeeding stages are sequentially and straightly located at intervals so as to fill in the spaces between the other stages, thus, the unbalance of the load capacitance between said stages and the functional unbalance between the shift registers can be minimized.
摘要翻译：在具有至少一个移位寄存器的半导体集成电路器件中，移位寄存器的多个5级串联电连接，所述移位寄存器的第1级位于与数据输入端最接近的位置，阶段是以间隔顺序和直线定位的; 阶段的链条在特定阶段被折叠，并且进一步的后续阶段以间隔顺序和直线地定位，以便填充其他阶段之间的空间，因此，所述阶段之间的负载电容的不平衡和功能不平衡移位寄存器之间可以最小化。

4. 发明授权

US06842388B2 Semiconductor memory device with bit line precharge voltage generating circuit 有权
标题翻译：具有位线预充电电压发生电路的半导体存储器件
公开(公告)号：US06842388B2
公开(公告)日：2005-01-11
申请号：US10300499
申请日：2002-11-19
申请人： Kenichi Origasa , Kiyoto Ohta , Masanobu Hirose
发明人： Kenichi Origasa , Kiyoto Ohta , Masanobu Hirose
IPC分类号： G01R31/28 , G01R31/3185 , G11C7/10 , G11C7/12 , G11C11/401 , G11C11/406 , G11C11/407 , G11C11/409 , G11C29/50 , G11C7/00
CPC分类号： G11C7/12 , G11C7/1048 , G11C2207/002
摘要： The present invention is a semiconductor memory device provided with bit line pairs to which a plurality of memory cells are attached, a plurality of precharge circuits for precharging the bit line pairs to a first voltage that is different from a mean value between a high level and a low level, a bit line precharge power line for supplying the first voltage for precharging to the precharge circuits, a capacitor, a charging circuit for charging the capacitor, and transfer gate circuits for controlling connection and disconnection of the capacitor and the bit line precharge power line. The transfer gate circuits are controlled so that the capacitor and the precharge power line are connected during precharging of the bit line pairs. Thus, precharging of the bit lines can be performed at high speeds with high precision.
摘要翻译：本发明是一种具有多个存储单元的位线对的半导体存储器件，多个用于将位线对预充电到第一电压的预充电电路，该第一电压不同于高电平和用于向预充电电路提供用于预充电的第一电压的位线预充电电源线，电容器，用于对电容器充电的充电电路，以及用于控制电容器的连接和断开的控制电路以及位线预充电电源线。控制传输门电路，使电容器和预充电电源线在位线对的预充电期间连接。因此，能够高精度地进行位线的预充电。

5. 发明授权

US06628162B2 Semiconductor integrated circuit 有权
公开(公告)号：US06628162B2
公开(公告)日：2003-09-30
申请号：US09991178
申请日：2001-11-16
申请人： Masataka Kondo , Kiyoto Ohta , Yuji Yamasaki , Toshikazu Suzuki , Masanobu Hirose
发明人： Masataka Kondo , Kiyoto Ohta , Yuji Yamasaki , Toshikazu Suzuki , Masanobu Hirose
IPC分类号： G05F110
CPC分类号： G05F3/247
摘要： A semiconductor integrated circuit includes a functional circuit and a power source voltage generating circuit used for operating the functional circuit. In the power source voltage generating circuit, output stage transistors are driven by comparing a plurality of reference voltages produced by a plurality of resistors connected in series to one another with output voltages of a plurality of differential amplifiers connected in parallel to one another and varying gate voltages.

6. 发明授权

US06532187B2 Semiconductor device having integrated memory and logic 有权
标题翻译：具有集成存储器和逻辑的半导体器件
公开(公告)号：US06532187B2
公开(公告)日：2003-03-11
申请号：US09867547
申请日：2001-05-31
申请人： Tomonori Fujimoto , Shoji Sakamoto , Kiyoto Ohta
发明人： Tomonori Fujimoto , Shoji Sakamoto , Kiyoto Ohta
IPC分类号： G11C800
CPC分类号： G11C11/4082 , G11C8/06 , G11C29/48
摘要： In a conventional DRAM, row addresses and column addresses are latched by DFF and decoding of addresses is started a certain time after a clock rise, and it takes a long time after the clock rise until the decoding is completed, having a problem that it is not possible to perform read/write at high speed. The present invention adopts a configuration connecting latch circuits such as the row address latch circuits and column address latch circuits using a scan chain. This makes decoding of row addresses and column addresses start when the clock is “L”, making it possible to complete decoding on the rise of each operation clock cycle, shorten the operation clock cycle and speed up read/write. The conventional art conducts a test on the connection between the row addresses and column addresses of the logic section and memory through an actual operation test of the entire LSI, resulting in a low circuit failure detection rate. The present invention conducts this test through a scan test, making it possible to automatically create test patterns with high circuit failure detection rate.
摘要翻译：在常规DRAM中，行地址和列地址被DFF锁存，地址的解码在时钟上升之后的特定时间开始，并且在时钟上升直到解码完成之后需要很长时间，具有这样的问题不可能高速执行读/写。本发明采用使用扫描链连接诸如行地址锁存电路和列地址锁存电路的锁存电路的配置。这使得当时钟为“L”时，行地址和列地址的解码开始，使得可以在每个操作时钟周期的上升完成解码，缩短操作时钟周期并加快读/写速度。传统技术通过整个LSI的实际操作测试来对逻辑部分和存储器的行地址和列地址之间的连接进行测试，导致低电路故障检测率。本发明通过扫描测试进行该测试，使得可以自动创建具有高电路故障检测速率的测试图案。

7. 发明授权

US06198671B1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US06198671B1
公开(公告)日：2001-03-06
申请号：US09506102
申请日：2000-02-17
申请人： Yasuhiro Aoyama , Kazuhiko Shimakawa , Kiyoto Ohta , Masanobu Hirose
发明人： Yasuhiro Aoyama , Kazuhiko Shimakawa , Kiyoto Ohta , Masanobu Hirose
IPC分类号： G11C700
CPC分类号： G11C5/14
摘要： The semiconductor memory device formed on a semiconductor substrate includes: a memory cell array having a plurality of memory cells formed at intersections between a plurality of word lines and a plurality of bit line pairs; a plurality of sense amplifiers each formed to correspond to each of the plurality of bit line pairs for amplifying a potential difference read on the bit line pair; and a low-level potential generation section for generating a low-level potential out of high-level and low-level potentials to be applied to the memory cells, the bit line pairs, and the sense amplifiers. The low-level potential generation section has: a ground potential generation part having a ground potential generation semiconductor element for generating as the low-level potential a first potential substantially equal to a ground potential; a threshold potential generation part having a threshold potential generation semiconductor element for generating as the low-level potential a second potential substantially equal to a threshold potential, and operating when a potential exceeding the threshold potential is applied; and a ground potential control part for controlling operation of the ground potential generation semiconductor element.
摘要翻译：形成在半导体衬底上的半导体存储器件包括：存储单元阵列，具有形成在多个字线和多个位线对之间的交叉处的多个存储单元; 多个读出放大器，每个形成为对应于多个位线对中的每一个，用于放大位线对上读取的电位差; 以及用于在施加到存储单元，位线对和读出放大器的高电平和低电平电位之间产生低电平电位的低电平电位产生部分。低电平电位产生部分具有：具有接地电位产生半导体元件的地电位产生部分，用于产生基本上等于地电势的第一电位作为低电位电位; 阈值电位产生部分，其具有用于产生基本上等于阈值电位的第二电位作为低电位电位的阈值电位产生半导体元件，并且当施加超过阈值电势的电位时操作; 以及用于控制地电位产生半导体元件的工作的接地电位控制部。

8. 发明申请

US20110255353A1 SEMICONDUCTOR INTEGRATED CIRCUIT 有权
标题翻译：半导体集成电路
公开(公告)号：US20110255353A1
公开(公告)日：2011-10-20
申请号：US13168515
申请日：2011-06-24
申请人： Yoshifumi FUKUSHIMA , Shoji Sakamoto , Hiroyuki Sadakata , Kiyoto Ohta
发明人： Yoshifumi FUKUSHIMA , Shoji Sakamoto , Hiroyuki Sadakata , Kiyoto Ohta
IPC分类号： G11C7/08
CPC分类号： G11C5/00 , G01R31/2874 , G11C5/143 , G11C7/04 , G11C8/10 , G11C8/18 , G11C11/4076 , G11C29/50 , G11C2029/5002 , H03K19/00369
摘要： A temperature sensing circuit activates a sensing signal when sensing that a temperature inside a semiconductor integrated circuit is lower than a predetermined temperature. A heat generation control circuit activates a heat generation control signal when the sensing signal is activated. When the heat generation control signal is activated, a current is generated inside a memory circuit to raise the temperature inside the semiconductor integrated circuit.
摘要翻译：当感测半导体集成电路内的温度低于预定温度时，温度检测电路激活感测信号。当感测信号被激活时，发热控制电路激活发热控制信号。当发热控制信号被激活时，在存储器电路内部产生电流以升高半导体集成电路内的温度。

9. 发明授权

US07266036B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07266036B2
公开(公告)日：2007-09-04
申请号：US10860111
申请日：2004-06-04
申请人： Emi Hayashi , Kiyoto Ohta , Yuji Yamasaki
发明人： Emi Hayashi , Kiyoto Ohta , Yuji Yamasaki
IPC分类号： G11C8/00
CPC分类号： G11C29/808 , G11C11/401 , G11C29/24
摘要： A semiconductor memory device is provided with a plurality of memory blocks including a plurality of word lines and a plurality of bit line pairs intersecting the individual word lines, a plurality of memory cells provided at each of intersections where the individual word lines intersect the bit line pairs, and a plurality of sense amplifiers respectively provided in correspondence with the bit line pairs. The semiconductor memory device further comprises common data bus line pairs each connected via switch transistors to the corresponding memory blocks, a read/write amplifier for performing a data read/write operation through the common data bus line pairs on the memory blocks, and an SRAM cell electrically connected via switch transistors to each common data bus line pair.
摘要翻译：半导体存储器件具有多个存储块，包括多个字线和与各个字线相交的多个位线对，多个存储单元，设置在各个字线与位线相交的每个相交处分别对应于位线对提供的多个读出放大器。半导体存储器件还包括通过开关晶体管连接到对应的存储块的公共数据总线线对，用于通过存储器块上的公共数据总线对执行数据读/写操作的读/写放大器，以及SRAM 单元经由开关晶体管电连接到每个公共数据总线线对。

10. 发明授权

US06741118B2 Semiconductor integrated circuit device and method of manufacturing the same 有权
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US06741118B2
公开(公告)日：2004-05-25
申请号：US10306588
申请日：2002-11-27
申请人： Toshitaka Uchikoba , Yuji Yamasaki , Kenichi Origasa , Kiyoto Ohta
发明人： Toshitaka Uchikoba , Yuji Yamasaki , Kenichi Origasa , Kiyoto Ohta
IPC分类号： G05F110
CPC分类号： H02M3/07 , H02M2003/071
摘要： A semiconductor integrated circuit device includes a charge pump circuit for outputting a predetermined negative voltage to a negative voltage node, a voltage detection circuit for generating a first detection signal when the voltage of the negative voltage node has reached a first detection voltage and for generating a second detection signal when the voltage of the negative voltage node has reached a second detection voltage, an oscillator that is driven in response to the first detection signal so as to generate a signal for driving the charge pump circuit, and a negative voltage raising circuit that has an output terminal connected to the negative voltage node, and that is driven in response to the second detection signal so as to raise the voltage of the negative voltage node through the output of its output terminal. The VBB voltage can be increased rapidly and can be controlled at higher speeds, thereby increasing the stability of the voltage.
摘要翻译：半导体集成电路装置包括用于向负电压节点输出预定负电压的电荷泵电路，当负电压节点的电压达到第一检测电压时产生第一检测信号的电压检测电路，当所述负电压节点的电压达到第二检测电压时的第二检测信号;响应于所述第一检测信号被驱动以产生用于驱动所述电荷泵电路的信号的振荡器;以及负电压升高电路，具有连接到负电压节点的输出端子，并且响应于第二检测信号被驱动，以便通过其输出端子的输出来提高负电压节点的电压。 VBB电压可以快速增加，可以在更高的速度下进行控制，从而提高电压的稳定性。

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