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1. 发明授权

US07266036B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07266036B2
公开(公告)日：2007-09-04
申请号：US10860111
申请日：2004-06-04
申请人： Emi Hayashi , Kiyoto Ohta , Yuji Yamasaki
发明人： Emi Hayashi , Kiyoto Ohta , Yuji Yamasaki
IPC分类号： G11C8/00
CPC分类号： G11C29/808 , G11C11/401 , G11C29/24
摘要： A semiconductor memory device is provided with a plurality of memory blocks including a plurality of word lines and a plurality of bit line pairs intersecting the individual word lines, a plurality of memory cells provided at each of intersections where the individual word lines intersect the bit line pairs, and a plurality of sense amplifiers respectively provided in correspondence with the bit line pairs. The semiconductor memory device further comprises common data bus line pairs each connected via switch transistors to the corresponding memory blocks, a read/write amplifier for performing a data read/write operation through the common data bus line pairs on the memory blocks, and an SRAM cell electrically connected via switch transistors to each common data bus line pair.
摘要翻译：半导体存储器件具有多个存储块，包括多个字线和与各个字线相交的多个位线对，多个存储单元，设置在各个字线与位线相交的每个相交处分别对应于位线对提供的多个读出放大器。半导体存储器件还包括通过开关晶体管连接到对应的存储块的公共数据总线线对，用于通过存储器块上的公共数据总线对执行数据读/写操作的读/写放大器，以及SRAM 单元经由开关晶体管电连接到每个公共数据总线线对。

2. 发明授权

US5694328A Method for designing a large scale integrated (LSI) layout 失效
标题翻译：大规模集成（LSI）布局设计方法
公开(公告)号：US5694328A
公开(公告)日：1997-12-02
申请号：US631904
申请日：1996-04-12
申请人： Emi Hayashi , Hiroyuki Miyamoto , Yoshihiro Tabira
发明人： Emi Hayashi , Hiroyuki Miyamoto , Yoshihiro Tabira
IPC分类号： G06F17/50 , H01L27/02
CPC分类号： H01L27/0207 , G06F17/5068
摘要： A plurality of cells which have input terminals and output terminals on four sides are divided into a plurality of groups of cells. The plurality of cells are placed in an array form at positions which are either adjacent or nonadjacent. A plurality of groups of cells are placed one after another such that the resulting layout becomes substantially rectangular or square. Power buses are routed parallel to each other, and power supply lines are routed from the power buses to cells. Data lines are routed between the terminals of the cells.
摘要翻译：在四侧具有输入端子和输出端子的多个单元被分成多组单元。多个单元格以与阵列形式相邻或不相邻的位置放置。多个单元组被一个接一个放置，使得所得到的布局变成基本上矩形或正方形。电源总线彼此并联连接，电源线从电源总线路由到单元。数据线在单元的端子之间路由。

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