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1. 发明授权

US07877667B2 Semiconductor memory 有权
公开(公告)号：US07877667B2
公开(公告)日：2011-01-25
申请号：US11714762
申请日：2007-03-07
申请人： Kenichi Origasa , Kiyoto Ohta
发明人： Kenichi Origasa , Kiyoto Ohta
IPC分类号： G06F11/00 , G06F11/08 , G11B20/18
CPC分类号： G11C7/1006 , G11C7/1078 , G11C7/1087 , G11C2029/0411
摘要： In order to correct an error in input data to thereby obtain write data, in a memory core, an EXOR element performs arithmetic processing based on an output result of an output data latch for latching read data and a result of inputted array input data, and a selector selects a result of the arithmetic processing to prepare write data. Thus, data obtained after performance of the arithmetic processing can be generated in a semiconductor memory by an operation performed immediately after data read. In addition, it is unnecessary to transfer data to an external logic circuit. Therefore, the result of the arithmetic processing can be written to a memory cell block in a subsequent clock.

2. 发明申请

US20080291717A1 SEMICONDUCTOR STORAGE DEVICE INCORPORATED INTO A SYSTEM LSI WITH FINER DESIGN RULES 有权
标题翻译：半导体存储设备中包含的的系统LSI更精细的设计规则。
公开(公告)号：US20080291717A1
公开(公告)日：2008-11-27
申请号：US12115921
申请日：2008-05-06
申请人： Kenichi Origasa
发明人： Kenichi Origasa
IPC分类号： G11C11/4063 , G11C7/00
CPC分类号： G11C11/4087 , G11C8/08 , G11C8/10 , G11C11/4085
摘要： In the present invention, a row decoder circuit is made up of a transistor having a first gate oxide film thickness, a transistor having a second gate oxide film thickness, and a transistor having a third gate oxide film thickness. Thus even a control circuit at a lower voltage can drive word lines at high speeds while achieving reliability.
摘要翻译：在本发明中，行译码器电路由具有第一栅极氧化膜层的厚度，具有第二栅氧化膜厚度的晶体管，和具有氧化膜的厚度第三栅极的晶体管的晶体管组成。因此，即使是较低电压的控制电路也可以高速驱动字线，同时实现可靠性。

3. 发明授权

US07312649B2 Voltage booster power supply circuit 有权
标题翻译：升压电源电路
公开(公告)号：US07312649B2
公开(公告)日：2007-12-25
申请号：US10820033
申请日：2004-04-08
申请人： Kenichi Origasa , Kiyoto Ohta
发明人： Kenichi Origasa , Kiyoto Ohta
IPC分类号： G05F1/46 , H02M3/00
CPC分类号： H02M3/073 , G11C5/145 , G11C11/4074
摘要： A voltage booster power supply circuit using a first voltage VDD3 and a second voltage VDDM to boost the first voltage VDD3, which is higher than the second voltage, to provide a boosted voltage VPP. Thus, a high efficiency of generation of a boosted voltage can be achieved compared with a configuration in which only the second voltage is used to boost the first voltage. A detector circuit detects the boosted voltage VPP to control a voltage booster circuit.
摘要翻译：一种使用第一电压VDD 3和第二电压VDDM以升高高于第二电压的第一电压VDD 3以提供升压电压VPP的升压电源电路。因此，与仅使用第二电压来提高第一电压的配置相比，可以实现高效率的升压电压的产生。检测器电路检测升压电压VPP以控制升压电路。

4. 发明申请

US20070260964A1 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：US20070260964A1
公开(公告)日：2007-11-08
申请号：US11714762
申请日：2007-03-07
申请人： Kenichi Origasa , Kiyoto Ohta
发明人： Kenichi Origasa , Kiyoto Ohta
IPC分类号： G11C29/00
CPC分类号： G11C7/1006 , G11C7/1078 , G11C7/1087 , G11C2029/0411
摘要： In order to correct an error in input data to thereby obtain write data, in a memory core, an EXOR element performs arithmetic processing based on an output result of an output data latch for latching read data and a result of inputted array input data, and a selector selects a result of the arithmetic processing to prepare write data. Thus, data obtained after performance of the arithmetic processing can be generated in a semiconductor memory by an operation performed immediately after data read. In addition, it is unnecessary to transfer data to an external logic circuit. Therefore, the result of the arithmetic processing can be written to a memory cell block in a subsequent clock.
摘要翻译：为了校正输入数据中的错误从而获得写入数据，在存储器核心中，EXOR元件基于用于锁存读取数据的输出数据锁存器的输出结果和输入的数组输入数据的结果执行算术处理，以及选择器选择算术处理的结果来准备写入数据。因此，通过在数据读取之后立即执行的操作，可以在半导体存储器中产生在执行算术处理之后获得的数据。此外，不需要将数据传送到外部逻辑电路。因此，算术处理的结果可以在随后的时钟中写入存储单元块。

5. 发明申请

US20110119563A1 Semiconductor memory 审中-公开
标题翻译：半导体存储器
公开(公告)号：US20110119563A1
公开(公告)日：2011-05-19
申请号：US12929362
申请日：2011-01-19
申请人： Kenichi Origasa , Kiyoto Ohta
发明人： Kenichi Origasa , Kiyoto Ohta
IPC分类号： G06F11/10
CPC分类号： G11C7/1006 , G11C7/1078 , G11C7/1087 , G11C2029/0411
摘要： In order to correct an error in input data to thereby obtain write data, in a memory core, an EXOR element performs arithmetic processing based on an output result of an output data latch for latching read data and a result of inputted array input data, and a selector selects a result of the arithmetic processing to prepare write data. Thus, data obtained after performance of the arithmetic processing can be generated in a semiconductor memory by an operation performed immediately after data read. In addition, it is unnecessary to transfer data to an external logic circuit. Therefore, the result of the arithmetic processing can be written to a memory cell block in a subsequent clock.
摘要翻译：为了校正输入数据中的错误从而获得写入数据，在存储器核心中，EXOR元件基于用于锁存读取数据的输出数据锁存器的输出结果和输入的数组输入数据的结果执行算术处理，以及选择器选择算术处理的结果来准备写入数据。因此，通过在数据读取之后立即执行的操作，可以在半导体存储器中产生在执行算术处理之后获得的数据。此外，不需要将数据传送到外部逻辑电路。因此，算术处理的结果可以在随后的时钟中写入存储单元块。

6. 发明授权

US06487138B2 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：US06487138B2
公开(公告)日：2002-11-26
申请号：US09870467
申请日：2001-06-01
申请人： Kenichi Origasa
发明人： Kenichi Origasa
IPC分类号： G11C700
CPC分类号： G11C8/10 , G11C8/08
摘要： To provide a semiconductor memory which can drive a word line faster than a conventional art, and reduce a layout area when a chip is formed as a semiconductor integrated circuit, thereby miniaturizing the chip. In the present invention, a word driver for driving the word line is constituted by a one-stage row decoder and a one-stage word driver group, and a load on a word line select signal is reduced, thereby driving the word line at high speeds.
摘要翻译：为了提供可以比常规技术更快地驱动字线的半导体存储器，并且当芯片形成为半导体集成电路时减小布局面积，从而使芯片小型化。在本发明中，用于驱动字线的字驱动器由一级行解码器和一级字驱动器组构成，字线选择信号上的负载减小，从而将字线驱动为高电平速度。

7. 发明申请

US20050205983A1 Semiconductor memory device and multi-chip module comprising the semiconductor memory device 有权
标题翻译：半导体存储器件和包括半导体存储器件的多芯片模块
公开(公告)号：US20050205983A1
公开(公告)日：2005-09-22
申请号：US11131385
申请日：2005-05-18
申请人： Kenichi Origasa , Yuji Yamasaki
发明人： Kenichi Origasa , Yuji Yamasaki
IPC分类号： G11C17/00 , G11C5/06 , G11C11/22 , G11C11/401 , G11C11/407 , G11C11/41 , G11C11/413 , G11C16/04 , G11C16/06 , G11C29/48 , H01L21/822 , H01L21/8242 , H01L25/065 , H01L25/07 , H01L25/18 , H01L27/04 , H01L27/10 , H01L27/108 , H01L23/02
CPC分类号： H01L25/18 , G11C5/06 , G11C29/48 , G11C2207/105 , H01L25/0652 , H01L2224/05573 , H01L2224/16145 , H01L2924/00014 , H01L2924/3011 , H01L2224/05599
摘要： In a semiconductor memory device composed of a semiconductor chip and overlaid to a surface of another semiconductor chip so as to connect together, a control circuit provided in the semiconductor memory device is provided with a chip connector portion having a plurality of pads. The chip connector portion is formed to have a configuration corresponding to the maximum capacity of the memory cell array provided in the semiconductor memory device, and the location and the number of the pads are invariably determined even when the memory cell array has a capacity less than the maximum capacity. The control circuit incorporating the chip connector portion is also invariably determined so as to control reading and writing data from and into the memory cell array having the maximum capacity, regardless of the capacity of the memory cell array provided.
摘要翻译：在由半导体芯片构成并与另一半导体芯片的表面重合以连接在一起的半导体存储器件中，设置在半导体存储器件中的控制电路设置有具有多个焊盘的芯片连接器部分。芯片连接器部分形成为具有对应于设置在半导体存储器件中的存储单元阵列的最大容量的配置，并且即使当存储单元阵列具有小于等于的容量时，也始终确定焊盘的位置和数量最大容量。包含芯片连接器部分的控制电路也总是被确定，以便控制从具有最大容量的存储单元阵列读取和写入数据，而与所提供的存储单元阵列的容量无关。

8. 发明授权

US06349072B1 Random access memory device 失效
标题翻译：随机存取存储器件
公开(公告)号：US06349072B1
公开(公告)日：2002-02-19
申请号：US09705541
申请日：2000-11-03
申请人： Kenichi Origasa , Kiyoto Oota , Tomonori Fujimoto
发明人： Kenichi Origasa , Kiyoto Oota , Tomonori Fujimoto
IPC分类号： G11C800
CPC分类号： G11C7/22 , G11C8/18 , G11C11/4076 , G11C11/409 , G11C2207/2281 , G11C2207/229
摘要： To realize a semiconductor memory which can be operated at a low frequency without reducing a data transfer rate, the semiconductor memory according to the invention is configured so that a series of operation can be finished in two clock cycles of row address strobe operation and column address strobe operation for operating DRAM. Timing for turning a sense amplifier activation signal SE at a high level after delay time determined by a first delay element since a leading edge of a clock pulse CLK that turns a row address strobe pulse (/RAS) at a low level and activating a sense amplifier sequence is generated. Also, timing for starting read operation and write operation since a leading edge of the clock pulse CLK at which a column address strobe pulse (/CAS) is turned at a low level, turning the sense amplifier activation signal SE at a low level, turning a bit line precharge signal EQPR at a high level and starting precharge operation when the termination of reading and writing is detected is acquired.
摘要翻译：为了实现能够以低频率操作而不降低数据传输速率的半导体存储器，根据本发明的半导体存储器被配置为使得可以在行地址选通操作和列地址的两个时钟周期中完成一系列操作频闪操作用于操作DRAM。用于在由第一延迟元件确定的延迟时间之后将读出放大器激活信号SE转换为高电平的时序，因为将行地址选通脉冲（/ RAS）变为低电平并激活感测的时钟脉冲CLK的前沿产生放大器序列。此外，从列位地址选通脉冲（/ CAS）转为低电平的时钟脉冲CLK的前沿开始读操作和写操作的定时，将读出放大器激活信号SE转为低电平，转动获取高电平的位线预充电信号EQPR和检测到读取和写入结束时的开始预充电操作。

9. 发明授权

US07733735B2 Semiconductor storage device incorporated into a system LSI with finer design rules 有权
标题翻译：半导体存储装置结合到具有更精细设计规则的系统LSI中
公开(公告)号：US07733735B2
公开(公告)日：2010-06-08
申请号：US12115921
申请日：2008-05-06
申请人： Kenichi Origasa
发明人： Kenichi Origasa
IPC分类号： G11C11/00
CPC分类号： G11C11/4087 , G11C8/08 , G11C8/10 , G11C11/4085
摘要： In the present invention, a row decoder circuit is made up of a transistor having a first gate oxide film thickness, a transistor having a second gate oxide film thickness, and a transistor having a third gate oxide film thickness. Thus even a control circuit at a lower voltage can drive word lines at high speeds while achieving reliability.
摘要翻译：在本发明中，行解码器电路由具有第一栅极氧化膜厚度的晶体管，具有第二栅极氧化膜厚度的晶体管和具有第三栅极氧化膜厚度的晶体管构成。因此，即使是较低电压的控制电路也可以高速驱动字线，同时实现可靠性。

10. 发明申请

US20070230262A1 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：US20070230262A1
公开(公告)日：2007-10-04
申请号：US11727910
申请日：2007-03-29
申请人： Kenichi Origasa
发明人： Kenichi Origasa
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C7/065 , G11C7/08 , G11C7/1051 , G11C7/1069 , G11C11/4074 , G11C11/4091 , G11C11/4094 , G11C2207/002 , G11C2207/065
摘要： A semiconductor memory including a memory cell, a bit line pair connected to the memory cell, a data line pair connected to the bit line pair through a switching element capable of ON/OFF switching in response to a value of a column selection signal and a precharge circuit for controlling an initial potential common between the data line pair. The semiconductor memory comprises a precharge potential control circuit which applies, in a precharge period, a low apply voltage not higher than a first predetermined potential to the data line pair when the initial potential of the data line pair is higher than the first predetermined potential, a high apply voltage not lower than a second predetermined potential to the data line pair when the potential of the data line pair is lower than the second predetermined potential or no voltage when the potential of the data line pair is not higher than the first predetermined potential and not lower than the second predetermined potential.
摘要翻译：一种半导体存储器，包括存储单元，连接到存储单元的位线对，通过能够根据列选择信号的值进行ON / OFF切换的开关元件与位线对连接的数据线对，以及用于控制数据线对之间共同的初始电位的预充电电路。半导体存储器包括预充电电位控制电路，其在数据线对的初始电位高于第一预定电位时，在预充电期间向数据线对施加不高于第一预定电位的低施加电压，当数据线对的电位低于第二预定电位时，数据线对的电压不低于第二预定电位的高施加电压，或者当数据线对的电位不高于第一预定电位时，不施加电压并且不低于第二预定电位。

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