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1. 发明授权

US5200635A Semiconductor device having a low-resistivity planar wiring structure 失效
标题翻译：具有低电阻率平面布线结构的半导体器件
公开(公告)号：US5200635A
公开(公告)日：1993-04-06
申请号：US686757
申请日：1991-04-17
申请人： Toru Kaga , Shinichiro Kimura , Katsutaka Kimura , Yoshinobu Nakagome , Digh Hisamoto , Yoshifumi Kawamoto , Eiji Takeda , Shimpei Iijima , Tokuo Kure , Takashi Nishida
发明人： Toru Kaga , Shinichiro Kimura , Katsutaka Kimura , Yoshinobu Nakagome , Digh Hisamoto , Yoshifumi Kawamoto , Eiji Takeda , Shimpei Iijima , Tokuo Kure , Takashi Nishida
IPC分类号： H01L27/108 , H01L29/417 , H01L29/45
CPC分类号： H01L29/41775 , H01L27/10817 , H01L29/456 , H01L2924/0002
摘要： The present invention concerns a semiconductor device having a low-resistivity wiring structure. Wirings formed directly on a hill and valley structure result in a thin portion and, in an extreme case, a disconnected portion. This increases the resistivity of wirings on the hill and valley structure and lowers the reliability of the connection. In a case where the wirings are data lines of a memory, with an increased effective length, the resistance and the parasitic capacitance of the data line is greater. The above mentioned problems have been solved by wirings which comprise at least two layers of conductive film including a first conductive film as a lower layer and a second conductive film as an upper layer, and the first conductive layer has a surface moderating or planarizing the hills and valleys in the underlying material.
摘要翻译：本发明涉及具有低电阻率布线结构的半导体器件。直接形成在山谷和山谷结构上的布线导致薄的部分，并且在极端情况下是断开的部分。这增加了山丘和山谷结构上的布线电阻率，降低了连接的可靠性。在布线是存储器的数据线的情况下，随着有效长度的增加，数据线的电阻和寄生电容更大。上述问题已经通过包括至少两层导电膜的布线来解决，所述导电膜包括作为下层的第一导电膜和作为上层的第二导电膜，并且第一导电层具有调节或平坦化山丘的表面和底层材料中的山谷。

2. 发明授权

US5296729A Semiconductor memory device having static random access memory 失效
标题翻译：具有静态随机存取存储器的半导体存储器件
公开(公告)号：US5296729A
公开(公告)日：1994-03-22
申请号：US782623
申请日：1991-10-25
申请人： Toshiaki Yamanaka , Norio Hasegawa , Toshihiko Tanaka , Takashi Hashimoto , Koichiro Ishibashi , Naotaka Hashimoto , Akihiro Shimizu , Yasuhiro Sugawara , Tokuo Kure , Shimpei Iijima , Takashi Nishida , Eiji Takeda
发明人： Toshiaki Yamanaka , Norio Hasegawa , Toshihiko Tanaka , Takashi Hashimoto , Koichiro Ishibashi , Naotaka Hashimoto , Akihiro Shimizu , Yasuhiro Sugawara , Tokuo Kure , Shimpei Iijima , Takashi Nishida , Eiji Takeda
IPC分类号： G03F1/29 , G03F1/30 , G03F1/68 , H01L21/027 , H01L21/8244 , H01L27/11 , H01L27/02 , H01L29/00 , H01L29/78
CPC分类号： H01L27/1108 , Y10S257/903
摘要： There is provided a technique capable of reducing the electrode resistance by widening the effective area of an electrode in a cell for a standard potential supply connected to the memory cell. There is also provided a technique capable of reducing the memory cell area by reducing the area necessary for separation between the electrode in a cell for the standard potential supply and adjacent other electrodes. Two transfer MOS transistors of a first conductivity type and two driver MOS transistors are provided. A conductive layer for fixing the source potential of the driver MOS transistors to standard potential is so disposed above the transfer and driver MOS transistors as to the wholly cover the memory cell. Separation is carried out by using a photo-mask having an optically transparent substrate provided within the same transmissive portion with a pattern of a plurality of so-called phase shifter regions for inversion of the phase of transmitting light.
摘要翻译：提供了一种能够通过扩大连接到存储单元的标准电位电源的单元中的电极的有效面积来减小电极电阻的技术。还提供了一种能够通过减小用于标准电位电极的电极中的电极与相邻的其它电极之间分离所需的面积来减小存储单元面积的技术。提供了第一导电类型的两个传输MOS晶体管和两个驱动器MOS晶体管。用于将驱动器MOS晶体管的源极电位固定为标准电位的导电层设置在传输和驱动器MOS晶体管之上，以完全覆盖存储器单元。通过使用具有设置在相同透射部分内的光学透明基板的光掩模进行分离，其具有多个所谓的移相器区域的图案，用于反转透射相位的相位。

3. 发明授权

US5594246A Method and apparatus for x-ray analyses 失效
标题翻译： x射线分析的方法和装置
公开(公告)号：US5594246A
公开(公告)日：1997-01-14
申请号：US430535
申请日：1995-04-25
申请人： Yoshimi Sudo , Tokuo Kure , Ken Ninomiya , Katsuhiro Kuroda , Takashi Nishida , Hideo Todokoro , Yasuhiro Mitsui , Hiroyasu Shichi
发明人： Yoshimi Sudo , Tokuo Kure , Ken Ninomiya , Katsuhiro Kuroda , Takashi Nishida , Hideo Todokoro , Yasuhiro Mitsui , Hiroyasu Shichi
IPC分类号： G01N23/225 , H01J37/252 , G01N23/223
CPC分类号： G01N23/2252 , H01J37/252 , H01J2237/2445
摘要： An X-ray analyzing method includes the steps of applying an irradiated electron beam, converged by a condenser lens and an objective lens into a thin beam, to the inside of a fine hole existing on the surface of a sample; observing X-rays generated from a residual substance existing inside the fine hole; and performing a qualitative and quantitative analysis of the residual substance. The X-rays are observed by an X-ray detector installed in an internal space of the condenser lens, an internal space of the objective lens, or between the condenser lens and the objective lens, by detecting only the X-rays radiated within the angular range -.theta. to +.theta., where .theta. is an angle formed with a center axis of the electron beam, and so defined that tan .theta. is substantially equal to a/d, where a and d are the radius and the depth of the fine hole, respectively.
摘要翻译： X射线分析方法包括以下步骤：将由聚光透镜和物镜会聚的照射的电子束施加到薄的光束中，使其存在于样品表面上的细孔的内部; 观察由存在于细孔内的残留物质产生的X射线; 并对剩余物质进行定性和定量分析。 X射线由安装在聚光透镜的内部空间，物镜的内部空间或者聚光透镜与物镜之间的X射线检测器观测，仅检测在该透镜内辐射的X射线角度范围-θ至+θ，其中θ是与电子束的中心轴形成的角度，并且如此定义为tanθ基本上等于a / d，其中a和d是微细的半径和深度孔。

4. 发明授权

US5877498A Method and apparatus for X-ray analyses 失效
标题翻译： X射线分析的方法和装置
公开(公告)号：US5877498A
公开(公告)日：1999-03-02
申请号：US893034
申请日：1997-07-15
申请人： Aritoshi Sugimoto , Yoshimi Sudo , Tokuo Kure , Ken Ninomiya , Katsuhiro Kuroda , Takashi Nishida , Hideo Todokoro , Yasuhiro Mitsui , Hiroyasu Shichi
发明人： Aritoshi Sugimoto , Yoshimi Sudo , Tokuo Kure , Ken Ninomiya , Katsuhiro Kuroda , Takashi Nishida , Hideo Todokoro , Yasuhiro Mitsui , Hiroyasu Shichi
IPC分类号： G01N23/225 , H01J37/256
CPC分类号： G01N23/2252 , H01J2237/2445 , H01J2237/2807
摘要： An X-ray analyzing method for inspecting opening states of fine holes comprises the steps of: irradiating a finely converged electron beam into a first fine hole, observing an X-ray emitted from the inside of said first fine hole in order to obtain an first X-ray analysis data about the residue substance existing at the bottom of said first fine hole; irradiating a finely converged electron beam into a second fine hole, observing an X-ray emitted from the inside of said second fine hole in order to obtain an second X-ray analysis data about the residue substance existing at the bottom of said second fine hole; and comparing said first X-ray analysis data with said second X-ray analysis data, forming a judgment as to whether or not a difference between said first and second analysis data is smaller than a predetermined threshold value and using an outcome of said judgment to determine the opening states of said first and second fine holes. The X-ray observations are carried out by detecting only the X-rays emitted within the angular range -.theta. to +.theta. where notation .theta. is an angle formed with a center axis of the irradiated electron beam and so defined that tan .theta. is equal to a/d whereas notations a and d are the radius and the depth of the fine holes.
摘要翻译：用于检查细孔的打开状态的X射线分析方法包括以下步骤：将精细会聚的电子束照射到第一细孔中，观察从所述第一细孔的内部发射的X射线，以获得第一细孔关于存在于所述第一细孔底部的残留物质的X射线分析数据; 将精细会聚的电子束照射到第二细孔中，观察从所述第二细孔的内部发射的X射线，以获得关于存在于所述第二细孔底部的残留物质的第二X射线分析数据 ; 以及将所述第一X射线分析数据与所述第二X射线分析数据进行比较，形成关于所述第一和第二分析数据之间的差是否小于预定阈值的判断，并且使用所述判断结果确定所述第一和第二细孔的打开状态。通过仅检测在角度范围θ至+θ内发射的X射线来进行X射线观察，其中符号θ是与照射的电子束的中心轴形成的角度，并且如此定义，tanθ等于 a / d，而符号a和d是细孔的半径和深度。

5. 发明授权

US5426326A Semiconductor device including arrangement for reducing junction degradation 失效
标题翻译：半导体器件包括用于减少结退化的装置
公开(公告)号：US5426326A
公开(公告)日：1995-06-20
申请号：US103206
申请日：1993-08-09
申请人： Kiyonori Ohyu , Kozo Watanabe , Osamu Tsuchiya , Kazuyoshi Oshima , Yoshifumi Kawamoto , Atsushi Hiraiwa , Takashi Nishida
发明人： Kiyonori Ohyu , Kozo Watanabe , Osamu Tsuchiya , Kazuyoshi Oshima , Yoshifumi Kawamoto , Atsushi Hiraiwa , Takashi Nishida
IPC分类号： H01L27/10 , H01L29/08 , H01L29/36 , H01L29/78 , H01L29/165
CPC分类号： H01L29/0847 , H01L29/08 , H01L29/36
摘要： An arrangement is provided to decrease the junction degradation caused by the leakage current at a p-n junction in semiconductor devices. This arrangement can be useful for a variety of devices, and is especially effective for reducing junction degradation at the source or drain region of a MOSFET. To achieve such a reduction, a p-n junction layer is provided at a p-n junction of a semiconductor region and a substrate. Carrier concentration distributions of a p-type layer and an n-type layer of the p-n junction layer are set so that an electric field which tends to be increased by a local electric field enhancement in a depletion layer of the p-n junction due to a precipitate introduced from a semiconductor surface will not exceed 1 MV/cm. When the depth of a depletion layer of the p-type layer or the n-type layer is referred to as Xp or Xn, and the slope of the carrier concentration, Ap or An, the following relation is provided:4.3.times.10.sup.12 (/cm.sup.2).gtoreq.An.multidot.Xn.sup.2 =Ap.multidot.Xp.sup.2Preferably, the p-n junction layer is formed under a contact hole of a source or drain region if the device in question is a MOSFET. As a result of using this arrangement, the leakage current caused by a local Zener effect decreases so that the electric field locally increased by the precipitate will not be greater than 1 MV/cm.
摘要翻译：提供了一种布置，以减少由半导体器件中的p-n结处的漏电流引起的结劣化。这种布置对于各种器件可能是有用的，并且对于降低MOSFET的源极或漏极区域处的结退化特别有效。为了实现这种减少，在半导体区域和衬底的p-n结处提供p-n结层。 pn结层的p型层和n型层的载流子浓度分布被设定为使得由于沉淀引起的在pn结的耗尽层中的局部电场增强倾向于增加的电场从半导体表面引入的电流不超过1MV / cm。当p型层或n型层的耗尽层的深度被称为Xp或Xn以及载流子浓度Ap或An的斜率时，提供以下关系：4.3×10 12（/ cm 2））> / = AnxXn2 = ApxXp2如果所讨论的器件是MOSFET，则优选地，在源极或漏极区域的接触孔下方形成pn结层。作为使用这种布置的结果，由局部齐纳效应引起的漏电流减小，使得由沉淀物局部增加的电场将不会大于1MV / cm。

6. 发明授权

US5132771A Semiconductor memory device having flip-flop circuits 失效
标题翻译：具有触发电路的半导体存储器件
公开(公告)号：US5132771A
公开(公告)日：1992-07-21
申请号：US503928
申请日：1990-04-04
申请人： Toshiaki Yamanaka , Naotaka Hashimoto , Takashi Hashimoto , Akihiro Shimizu , Koichiro Ishibashi , Katsuro Sasaki , Katsuhiro Shimohigashi , Eiji Takeda , Yoshio Sakai , Takashi Nishida , Osamu Minato , Toshiaki Masuhara , Shoji Hanamura , Shigeru Honjo , Nobuyuki Moriwaki
发明人： Toshiaki Yamanaka , Naotaka Hashimoto , Takashi Hashimoto , Akihiro Shimizu , Koichiro Ishibashi , Katsuro Sasaki , Katsuhiro Shimohigashi , Eiji Takeda , Yoshio Sakai , Takashi Nishida , Osamu Minato , Toshiaki Masuhara , Shoji Hanamura , Shigeru Honjo , Nobuyuki Moriwaki
IPC分类号： G11C11/412 , H01L27/11
CPC分类号： G11C11/4125 , H01L27/1104 , Y10S257/903
摘要： A semiconductor static random access memory having a high .alpha.-ray immunity and a high packing density is provided which is also capable of high-speed operation. A semiconductor memory device comprises static random access memory cells each including a flip-flop circuit. Storage nodes of each flip-flop circuit have respective pn-junctions formed at regions sandwiched between gate electrodes of first insulated gate field effect transistors and gate electrodes of second insulated gate field effect transistors, respectively. The pn-junction has an area smaller than that of a channel portion of the first or second insulated gate field effect transistor. The gate electrode of one of the two first insulated gate field effect transistors and the drain region of the other insulated gate field effect transistor, on one hand, and the drain region of the one insulated gate field effect transistor and the gate electrode of the other insulated gate field effect transistor, on the other hand, are electrically cross-coupled mutually through first and second electrically conductive films, respectively. Also, to increase packing density and enhance immunity to soft error, the gate electrodes of the first and second insulated gate field effect transistors extend substantially in parallel with one another and the channel regions of the first and second insulated gate field effect transistors extend substantially in parallel with one another.
摘要翻译：提供了具有高α射线抗扰度和高封装密度的半导体静态随机存取存储器，其也能够进行高速操作。半导体存储器件包括每个包括触发器电路的静态随机存取存储器单元。每个触发器电路的存储节点分别形成在夹在第一绝缘栅场效应晶体管的栅电极和第二绝缘栅场效应晶体管的栅电极之间的区域处的各pn结。 pn结的面积小于第一或第二绝缘栅场效应晶体管的沟道部分的面积。两个第一绝缘栅场效应晶体管中的一个的栅极电极和另一个绝缘栅场效应晶体管的漏极区域以及一个绝缘栅场效应晶体管的漏极区域和另一个绝缘栅极场效应晶体管的栅极电极另一方面，绝缘栅场效应晶体管分别通过第一和第二导电膜互相交叉耦合。此外，为了增加封装密度并增强对软误差的抵抗力，第一和第二绝缘栅场效应晶体管的栅极彼此基本平行地延伸，并且第一和第二绝缘栅场效应晶体管的沟道区域基本上以彼此平行。

7. 发明授权

US5034797A Semiconductor memory devices having stacked polycrystalline silicon transistors 失效
标题翻译：具有堆叠多晶硅晶体管的半导体存储器件
公开(公告)号：US5034797A
公开(公告)日：1991-07-23
申请号：US497182
申请日：1990-03-22
申请人： Toshiaki Yamanaka , Yoshio Sakai , Takashi Hashimoto , Takashi Nishida , Satoshi Meguro , Shuji Ikeda , Eiji Takeda
发明人： Toshiaki Yamanaka , Yoshio Sakai , Takashi Hashimoto , Takashi Nishida , Satoshi Meguro , Shuji Ikeda , Eiji Takeda
IPC分类号： G11C11/412 , H01L21/8244 , H01L27/11
CPC分类号： H01L27/1104 , H01L27/11 , H01L27/1108 , Y10S257/904
摘要： A semiconductor device having a CMIS structure for forming a static random access memory is disclosed which device can increase the packing density of the memory and reduce the stand-by power thereof. In this semiconductor device, a first MISFET of a first conductivity type is formed on and a substrate, a second MISFET of a second conductivity type is formed over the first MISFET with a first insulating film therebetween to form a stacked CMIS structure. The second MISFET is made up of a first conductive film, a second insulating film and a second conductive film, with the source, drain and channel regions of the second MISFET being formed in the first conductive film. A first resistive drain region is formed between the channel and drain regions of the first conductive film so that an impurity of the second conductivity type is contained in the first resistive drain region at a lower concentration than in the drain region, or the first resistive drain region is substantially undoped. The first resistive drain region is disposed over the gate electrode of the first MISFET, and the gate insulating film and gate electrode of the second MISFET are formed of the second insulating film and the second conductive film, respectively. In a case where a semiconductor memory device having a static random access memory cell which is provided with a flip-flop circuit of the stacked CMIS type, is formed, a pair of first MISFET's and a pair of third MISFET's of the first conductivity type are formed on the substrate, and the second MISFET is formed on one MISFET of the first MISFET's and the third MISFET's.
摘要翻译：公开了具有用于形成静态随机存取存储器的CMIS结构的半导体器件，其可以增加存储器的堆积密度并降低其待机功率。在该半导体器件中，在基板上形成第一导电型的第一MISFET，在第一MISFET上形成第二导电类型的第二MISFET，其间具有第一绝缘膜，以形成层叠的CMIS结构。第二MISFET由第一导电膜，第二绝缘膜和第二导电膜构成，第二MISFET的源极，漏极和沟道区形成在第一导电膜中。在第一导电膜的沟道和漏极区之间形成第一电阻漏极区，使得第一导电类型的杂质以比漏极区域低的浓度包含在第一电阻漏极区域中，或者第一电阻漏极区域基本上未掺杂。第一电阻漏极区域设置在第一MISFET的栅电极之上，并且第二MISFET的栅极绝缘膜和栅极电极分别由第二绝缘膜和第二导电膜形成。在具有设置有层叠CMIS型触发电路的静态随机存取存储单元的半导体存储器件的情况下，形成一对第一MISFET和第一导电类型的一对第三MISFET 并且第一MISFET形成在第一MISFET和第三MISFET的一个MISFET上。

8. 发明授权

US07776495B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07776495B2
公开(公告)日：2010-08-17
申请号：US11725507
申请日：2007-03-20
申请人： Masahito Hiroshima , Takashi Nishida
发明人： Masahito Hiroshima , Takashi Nishida
IPC分类号： G03F7/00
CPC分类号： H01L28/91 , G03F1/00 , H01L27/10808 , H01L27/10852
摘要： A semiconductor device and a manufacturing method thereof in which the peripheral length of an aperture and the mechanical strength of cylinders in a cell can be increased without changing the occupation rate of patterns in the cell. By forming a slit in the middle of each mask pattern so as not to expose parts of wafer, the aperture of the wafer becomes nearly cocoon-shaped with a constriction in the middle. Thereby, the peripheral length of the aperture can be increased without changing the occupation rate of the mask patterns in a cell. Further, the shape of the bottom of the aperture also becomes nearly cocoon-shaped with a constriction in the middle, and therefore it is possible to increase the mechanical strength of cylinders.
摘要翻译：一种半导体器件及其制造方法，其中可以增加孔的圆周长度和单元中气缸的机械强度，而不改变单元中图案的占用率。通过在每个掩模图案的中间形成狭缝以不暴露晶片的一部分，晶片的孔径在中间收缩而变为几乎茧形。因此，可以增加孔径的周长，而不改变单元中的掩模图案的占有率。此外，孔的底部的形状也变得几乎茧形，中间有收缩，因此可以提高气缸的机械强度。

9. 发明授权

US07208788B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07208788B2
公开(公告)日：2007-04-24
申请号：US10995134
申请日：2004-11-24
申请人： Masahito Hiroshima , Takashi Nishida
发明人： Masahito Hiroshima , Takashi Nishida
IPC分类号： H01L29/73
CPC分类号： H01L28/91 , G03F1/00 , H01L27/10808 , H01L27/10852
摘要： A semiconductor device and a manufacturing method thereof in which the peripheral length of an aperture and the mechanical strength of cylinders in a cell can be increased without changing the occupation rate of patterns in the cell. By forming a slit in the middle of each mask pattern so as not to expose parts of wafer, the aperture of the wafer becomes nearly cocoon-shaped with a constriction in the middle. Thereby, the peripheral length of the aperture can be increased without changing the occupation rate of the mask patterns in a cell. Further, the shape of the bottom of the aperture also becomes nearly cocoon-shaped with a constriction in the middle, and therefore it is possible to increase the mechanical strength of cylinders.
摘要翻译：一种半导体器件及其制造方法，其中可以增加孔的圆周长度和单元中气缸的机械强度，而不改变单元中图案的占用率。通过在每个掩模图案的中间形成狭缝以不暴露晶片的一部分，晶片的孔径在中间收缩而变为几乎茧形。因此，可以增加孔径的周长，而不改变单元中的掩模图案的占有率。此外，孔的底部的形状也变得几乎茧形，中间有收缩，因此可以提高气缸的机械强度。

10. 发明授权

US4886904A Polyprenyl composition or compounds and process for the production thereof 失效
标题翻译：聚丙烯基组合物及其制备方法
公开(公告)号：US4886904A
公开(公告)日：1989-12-12
申请号：US081735
申请日：1987-08-05
申请人： Yasuyuki Tanaka , Koichi Ibata , Masao Mizuno , Yoichi Ninagawa , Takashi Nishida
发明人： Yasuyuki Tanaka , Koichi Ibata , Masao Mizuno , Yoichi Ninagawa , Takashi Nishida
IPC分类号： C07C69/007 , C07C17/00 , C07C17/16 , C07C21/215 , C07C27/00 , C07C29/10 , C07C29/32 , C07C33/02 , C07C43/12 , C07C43/15 , C07C43/16 , C07C43/205 , C07C43/303 , C07C43/313 , C07C67/00 , C07C67/58 , C07C271/12 , C07D213/64 , C07D213/70 , C07D277/16 , C07D277/68 , C07D309/12 , C07F7/18 , C07F9/113
CPC分类号： C07D213/64 , C07C271/12 , C07C29/10 , C07C29/32 , C07C317/00 , C07C321/00 , C07C33/02 , C07C381/12 , C07C43/12 , C07C43/15 , C07C43/16 , C07C43/205 , C07C43/303 , C07C43/313 , C07D213/70 , C07D277/16 , C07D277/68 , C07D309/12 , C07F7/1852 , C07F9/113
摘要： A polyprenyl composition consisting essentially of a mixture of polyprenyl compounds represented by the following formula ##STR1## wherein A.sub.1 represents a hydroxyl or acetyloxy group, ##STR2## represents a trans-isoprene unit, ##STR3## represents a cis-isoprene unit, and n is an integer of from 11 to 19, said mixture containing substantial amounts of at least three compounds of formula (I) wherein n represents 14, 15 and 16 respectively as essential ingredients in a total amount of at least 70% by weight based on the weight of the mixture; and new compounds derived from the polyprenyl compounds of formula (I). These composition and compounds are useful for the synthesis of mammalian dolichols. The polyprenyl composition can be prepared by extracting the leaves of Ginkgo biloba or Cedrus deodara with an oil-soluble organic solvent; if required, hydrolyzing the extract; and subjecting the extract to one or more of chromatography, fractional dissolution, fractional refrigerating precipitation and molecular distillation, thereby separating and recovering a fraction having a specified Rf value in silica thin-layer chromatography.
摘要翻译：一种聚丙烯基组合物，其基本上由下式（I）表示的聚异戊二烯基化合物的混合物组成，其中A1表示羟基或乙酰氧基，IMAMA表示反异戊二烯单元，IMAGE表示顺式 - 异戊二烯单元，n为11至19的整数，所述混合物含有大量至少三种式（I）化合物，其中n表示14,15和16，作为必需成分，总量为至少70 基于混合物重量的重量％; 和衍生自式（I）的聚异戊二烯基化合物的新化合物。这些组合物和化合物可用于合成哺乳动物多烯醇。聚乙烯基组合物可以通过用油溶性有机溶剂提取银杏叶或雪松的叶子来制备; 如果需要，水解提取物; 并对提取物进行色谱法，分数溶解，分级冷冻沉淀和分子蒸馏中的一种或多种，从而在二氧化硅薄层色谱中分离和回收具有特定Rf值的级分。

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