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1. 发明授权

US5426326A Semiconductor device including arrangement for reducing junction degradation 失效
标题翻译：半导体器件包括用于减少结退化的装置
公开(公告)号：US5426326A
公开(公告)日：1995-06-20
申请号：US103206
申请日：1993-08-09
申请人： Kiyonori Ohyu , Kozo Watanabe , Osamu Tsuchiya , Kazuyoshi Oshima , Yoshifumi Kawamoto , Atsushi Hiraiwa , Takashi Nishida
发明人： Kiyonori Ohyu , Kozo Watanabe , Osamu Tsuchiya , Kazuyoshi Oshima , Yoshifumi Kawamoto , Atsushi Hiraiwa , Takashi Nishida
IPC分类号： H01L27/10 , H01L29/08 , H01L29/36 , H01L29/78 , H01L29/165
CPC分类号： H01L29/0847 , H01L29/08 , H01L29/36
摘要： An arrangement is provided to decrease the junction degradation caused by the leakage current at a p-n junction in semiconductor devices. This arrangement can be useful for a variety of devices, and is especially effective for reducing junction degradation at the source or drain region of a MOSFET. To achieve such a reduction, a p-n junction layer is provided at a p-n junction of a semiconductor region and a substrate. Carrier concentration distributions of a p-type layer and an n-type layer of the p-n junction layer are set so that an electric field which tends to be increased by a local electric field enhancement in a depletion layer of the p-n junction due to a precipitate introduced from a semiconductor surface will not exceed 1 MV/cm. When the depth of a depletion layer of the p-type layer or the n-type layer is referred to as Xp or Xn, and the slope of the carrier concentration, Ap or An, the following relation is provided:4.3.times.10.sup.12 (/cm.sup.2).gtoreq.An.multidot.Xn.sup.2 =Ap.multidot.Xp.sup.2Preferably, the p-n junction layer is formed under a contact hole of a source or drain region if the device in question is a MOSFET. As a result of using this arrangement, the leakage current caused by a local Zener effect decreases so that the electric field locally increased by the precipitate will not be greater than 1 MV/cm.
摘要翻译：提供了一种布置，以减少由半导体器件中的p-n结处的漏电流引起的结劣化。这种布置对于各种器件可能是有用的，并且对于降低MOSFET的源极或漏极区域处的结退化特别有效。为了实现这种减少，在半导体区域和衬底的p-n结处提供p-n结层。 pn结层的p型层和n型层的载流子浓度分布被设定为使得由于沉淀引起的在pn结的耗尽层中的局部电场增强倾向于增加的电场从半导体表面引入的电流不超过1MV / cm。当p型层或n型层的耗尽层的深度被称为Xp或Xn以及载流子浓度Ap或An的斜率时，提供以下关系：4.3×10 12（/ cm 2））> / = AnxXn2 = ApxXp2如果所讨论的器件是MOSFET，则优选地，在源极或漏极区域的接触孔下方形成pn结层。作为使用这种布置的结果，由局部齐纳效应引起的漏电流减小，使得由沉淀物局部增加的电场将不会大于1MV / cm。

2. 发明授权

US5200635A Semiconductor device having a low-resistivity planar wiring structure 失效
标题翻译：具有低电阻率平面布线结构的半导体器件
公开(公告)号：US5200635A
公开(公告)日：1993-04-06
申请号：US686757
申请日：1991-04-17
申请人： Toru Kaga , Shinichiro Kimura , Katsutaka Kimura , Yoshinobu Nakagome , Digh Hisamoto , Yoshifumi Kawamoto , Eiji Takeda , Shimpei Iijima , Tokuo Kure , Takashi Nishida
发明人： Toru Kaga , Shinichiro Kimura , Katsutaka Kimura , Yoshinobu Nakagome , Digh Hisamoto , Yoshifumi Kawamoto , Eiji Takeda , Shimpei Iijima , Tokuo Kure , Takashi Nishida
IPC分类号： H01L27/108 , H01L29/417 , H01L29/45
CPC分类号： H01L29/41775 , H01L27/10817 , H01L29/456 , H01L2924/0002
摘要： The present invention concerns a semiconductor device having a low-resistivity wiring structure. Wirings formed directly on a hill and valley structure result in a thin portion and, in an extreme case, a disconnected portion. This increases the resistivity of wirings on the hill and valley structure and lowers the reliability of the connection. In a case where the wirings are data lines of a memory, with an increased effective length, the resistance and the parasitic capacitance of the data line is greater. The above mentioned problems have been solved by wirings which comprise at least two layers of conductive film including a first conductive film as a lower layer and a second conductive film as an upper layer, and the first conductive layer has a surface moderating or planarizing the hills and valleys in the underlying material.
摘要翻译：本发明涉及具有低电阻率布线结构的半导体器件。直接形成在山谷和山谷结构上的布线导致薄的部分，并且在极端情况下是断开的部分。这增加了山丘和山谷结构上的布线电阻率，降低了连接的可靠性。在布线是存储器的数据线的情况下，随着有效长度的增加，数据线的电阻和寄生电容更大。上述问题已经通过包括至少两层导电膜的布线来解决，所述导电膜包括作为下层的第一导电膜和作为上层的第二导电膜，并且第一导电层具有调节或平坦化山丘的表面和底层材料中的山谷。

3. 发明授权

US07603194B2 Fabrication system and fabrication method 失效
标题翻译：制造系统及制造方法
公开(公告)号：US07603194B2
公开(公告)日：2009-10-13
申请号：US12153926
申请日：2008-05-28
申请人： Natsuki Yokoyama , Yoshifumi Kawamoto , Eiichi Murakami , Fumihiko Uchida , Kenichi Mizuishi , Yoshio Kawamura
发明人： Natsuki Yokoyama , Yoshifumi Kawamoto , Eiichi Murakami , Fumihiko Uchida , Kenichi Mizuishi , Yoshio Kawamura
IPC分类号： G06F19/00
CPC分类号： C23C14/568 , C23C16/54 , G05B19/41865 , G05B2219/45031 , H01L21/67161 , H01L21/67167 , H01L21/67173 , H01L21/67184 , H01L21/67276 , H01L21/67727 , H01L21/67745 , Y02P90/14 , Y02P90/20 , Y02P90/28 , Y10S414/135 , Y10S414/137 , Y10S438/908 , Y10T29/41
摘要： A fabricating method for a system that includes a plurality of processing apparatuses connected to each other by an inter-apparatus transporter and a computer storing managing information of processing and transporting of semiconductor wafers. The processing apparatuses have an interface for loading and unloading a plurality of the semiconductor wafers that are contained in a carrier. The semiconductor waters are processed in processing chambers of the processing apparatuses and the result of processing is monitored. In the processing, a first carrier containing the plurality of the semiconductor wafers having been processed in the first processing apparatus is transported toward the second processing apparatus by the inter-apparatus transporter prior to unloading of a second carrier containing semiconductor wafers processed in the second processing apparatus, according to the managing information.
摘要翻译：一种系统的制造方法，其包括通过机器间运输机彼此连接的多个处理装置和存储管理半导体晶片的处理和传输信息的计算机。处理装置具有用于装载和卸载容纳在载体中的多个半导体晶片的界面。在处理装置的处理室中处理半导体水，并监视处理结果。在处理中，在卸载包含在第二处理中处理的半导体晶片的第二载体之前，将包含在第一处理装置中处理的多个半导体晶片的第一载体通过装置间传送器传送到第二处理装置装置，根据管理信息。

4. 发明授权

US5858863A Fabrication system and method having inter-apparatus transporter 失效
标题翻译：具有装置间输送器的制造系统和方法
公开(公告)号：US5858863A
公开(公告)日：1999-01-12
申请号：US722944
申请日：1996-09-27
申请人： Natsuki Yokoyama , Yoshifumi Kawamoto , Eiichi Murakami , Fumihiko Uchida , Kenichi Mizuishi , Yoshio Kawamura
发明人： Natsuki Yokoyama , Yoshifumi Kawamoto , Eiichi Murakami , Fumihiko Uchida , Kenichi Mizuishi , Yoshio Kawamura
IPC分类号： B65G49/07 , B23Q41/00 , B23Q41/02 , C23C14/56 , C23C16/54 , G05B19/418 , H01L21/00 , H01L21/02 , H01L21/027 , H01L21/205 , H01L21/285 , H01L21/304 , H01L21/3065 , H01L21/3205 , H01L21/677 , H01L21/68
CPC分类号： C23C14/568 , C23C16/54 , G05B19/41865 , H01L21/67161 , H01L21/67167 , H01L21/67173 , H01L21/67184 , H01L21/67276 , H01L21/67727 , H01L21/67745 , G05B2219/45031 , Y02P90/14 , Y02P90/20 , Y02P90/28 , Y10S414/135 , Y10S414/137 , Y10S438/908 , Y10T29/41
摘要： Disclosed is a fabricating system including a plurality of processing apparatuses connected to each other by means of an inter-apparatus transporter, wherein one group of semiconductor wafers are processed in processing apparatuses and other group of wafers are transported to specified processing apparatuses for a time interval from (To+T) to a time To; and another group of wafers are processed and the remaining group of wafers are transported for a time interval from (To+T) to (To+2T). Since processing apparatuses can receive at least one of works from the inter-apparatus transporter for a time interval T min, the distribution of works from the transporter to processing apparatuses is completed for the time interval T min. The transporter is emptied for each time interval T min, and works are unloaded to the emptied transporter, which makes easy the scheduling, control and management of the transporting of a plurality of works in the fabricating system. Moreover, since the fabricating system including processing apparatuses is periodically controlled at a cycle time T min, the scheduling of a plurality of works can be made easy, to enhance the level of optimization, thus improving the productivity.
摘要翻译：公开了一种制造系统，其包括通过机构间传送器彼此连接的多个处理装置，其中一组半导体晶片在处理装置中被处理，并且其他组的晶片被传送到指定的处理装置一段时间间隔从（To + T）到一个时间To; 并且处理另一组晶片，并且剩余的晶片组从（To + T）到（To + 2T）的时间间隔被传输。由于处理装置可以从时间间隔T min接收来自装置间运送装置的作品中的至少一个，因此在时间间隔T min内完成从运送装置到处理装置的作品的分配。在每个时间间隔T min内运输运输车被清空，并且卸载到排空运输车，这使得在制造系统中运输多个作业的调度，控制和管理变得容易。此外，由于包括处理装置的制造系统在周期时间T min周期性地进行控制，因此能够容易地进行多个作业的调度，提高优化等级，提高生产率。

5. 发明授权

US5118633A Method for manufacturing a BiCMOS semiconductor device 失效
标题翻译：制造BICMOS半导体器件的方法
公开(公告)号：US5118633A
公开(公告)日：1992-06-02
申请号：US557649
申请日：1990-07-25
申请人： Kazuhiko Sagara , Kiyoo Itoh , Goro Kitsukawa , Yoshifumi Kawamoto , Yoshiki Kawajiri
发明人： Kazuhiko Sagara , Kiyoo Itoh , Goro Kitsukawa , Yoshifumi Kawamoto , Yoshiki Kawajiri
IPC分类号： H01L21/8242 , H01L21/8249 , H01L27/06 , H01L27/10 , H01L27/108
CPC分类号： H01L21/8249 , H01L27/0623 , H01L27/10817 , Y10S148/144
摘要： Sources and drains of MOS transistors are formed after the formation of an emitter of a bipolar transistor, whereby the sources and drains are made smaller in thickness than the emitter. Since the sources and drains are not subjected to a high-temperature heat treatment conducted in the formation of the emitter, there is no fear of increase in thickness of the sources and drains caused by the diffusion of impurities. There can be formed a BiCMOS having a high integration density and superior characteristics.

6. 发明授权

US5038193A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US5038193A
公开(公告)日：1991-08-06
申请号：US541751
申请日：1990-06-21
申请人： Yoshiaki Kamigaki , Shinichi Minami , Kazunori Furusawa , Yoshifumi Kawamoto , Shoji Shukuri , Masaaki Terasawa , Yasunori Ikeda , Hidefumi Mukohda
发明人： Yoshiaki Kamigaki , Shinichi Minami , Kazunori Furusawa , Yoshifumi Kawamoto , Shoji Shukuri , Masaaki Terasawa , Yasunori Ikeda , Hidefumi Mukohda
IPC分类号： H01L21/8247 , H01L21/76 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/105
摘要： In the semiconductor integrated circuit device provided with a plurality of second well regions of the same conductivity type, formed by dividing a first well region provided in the semiconductor substrate by an isolation trench, the isolation trench is substantially linear on the semiconductor substrate surface and the ends reach out of the first well region, however there is no intersection part, namely a corner part T part or cross part in the isolation trench. Therefore, no cavity occurs in the filler in the trench and stress is not concentrated on the intersection part. In addition, defects due to junction leak or mechanical damage do not occur, that is, there is no characteristic deterioration occuring. By providing the second well with memory cell, a semiconductor memory device whose characteristic defect rate and reliability defect rate are remarkably low can be formed.
摘要翻译：在具有相同导电类型的多个第二阱区的半导体集成电路器件中，隔离沟槽在半导体衬底表面上是基本上线性的，端部伸出第一阱区域，但是没有交叉部分，即隔离沟槽中的角部T部分或交叉部分。因此，沟槽中的填料不会产生空穴，应力不集中在交叉部分上。此外，不会发生由于接点泄漏或机械损伤引起的缺陷，即没有发生特性劣化。通过向存储单元提供第二阱，可以形成其特性缺陷率和可靠性缺陷率非常低的半导体存储器件。

7. 发明授权

US5012312A Semiconductor integrated circuit and a process for producing the same 失效
标题翻译：半导体集成电路及其制造方法
公开(公告)号：US5012312A
公开(公告)日：1991-04-30
申请号：US261843
申请日：1988-10-25
申请人： Yoshifumi Kawamoto
发明人： Yoshifumi Kawamoto
IPC分类号： H01L21/76 , H01L21/762 , H01L27/02 , H01L27/10 , H01L29/06 , H01L29/78
CPC分类号： H01L29/0638 , H01L21/76216 , H01L27/0203
摘要： The impurity concentration in a channel stopper in contact with a second fine active area is selected to be lower than the impurity concentration in a first active area that is wider than the second active area. This prevents the impurity concentration in the second active area from excessively rising that is caused by the diffusion of impurities when the insulating film for isolation is being formed, and helps improve characteristics and reliability of fine semiconductor device formed in the second active area.
摘要翻译：选择与第二微细活性区域接触的通道阻挡件中的杂质浓度低于第一有源区域中比第二有源区域宽的杂质浓度。由此，能够防止在形成绝缘用绝缘膜时由杂质的扩散引起的第二有源区域中的杂质浓度过度上升，有助于提高形成在第二有源区域的精细半导体器件的特性和可靠性。

8. 发明授权

US4970564A Semiconductor memory device having stacked capacitor cells 失效
标题翻译：具有层叠电容器单元的半导体存储器件
公开(公告)号：US4970564A
公开(公告)日：1990-11-13
申请号：US287881
申请日：1988-12-21
申请人： Shinichiro Kimura , Naotaka Hashimoto , Yoshio Sakai , Tokuo Kure , Yoshifumi Kawamoto
发明人： Shinichiro Kimura , Naotaka Hashimoto , Yoshio Sakai , Tokuo Kure , Yoshifumi Kawamoto
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10808
摘要： A semiconductor memory device having STC cells wherein major portions of active regions consisting of channel-forming portions are tilted at an angle of 45.degree. with respect to the word lines and the bit lines that meet at right angles with each other, enabling the storage capacity portions to be arranged very densely and sufficiently large capacities to be maintained with very small cell areas. In the semiconductor memory device, furthermore, the storage capacity portions are formed even on the bit lines. Therefore, the bit lines are shielded, the capacitance between the bit lines decreases, and the memory array noise decreases.
摘要翻译：具有STC单元的半导体存储器件，其中由沟道形成部分组成的有源区的主要部分相对于彼此成直角相交的字线和位线以45°的角度倾斜，使得存储容量部分布置得非常密集和足够大的容量保持非常小的单元格区域。此外，在半导体存储器件中，即使在位线上形成存储容量部分。因此，位线被屏蔽，位线之间的电容减小，并且存储器阵列噪声降低。

9. 发明授权

US4967247A Vertical dynamic random access memory 失效
标题翻译：垂直动态随机存取存储器
公开(公告)号：US4967247A
公开(公告)日：1990-10-30
申请号：US279350
申请日：1988-12-02
申请人： Toru Kaga , Yoshifumi Kawamoto , Hideo Sunami
发明人： Toru Kaga , Yoshifumi Kawamoto , Hideo Sunami
IPC分类号： H01L27/04 , H01L21/28 , H01L21/311 , H01L21/334 , H01L21/762 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/06 , H01L29/51 , H01L29/78
CPC分类号： H01L21/28211 , H01L21/31111 , H01L27/10841 , H01L27/10864 , H01L29/0657 , H01L29/66181 , H01L29/7827 , H01L29/51
摘要： A semiconductor memory comprises a switching device and a charge-storage device disposed at the upper and lower sides, respectively, of each of semiconductor islands. The islands are formed on a semiconductor substrate that is completely isolated from the semiconductor substrate by an insulator. The switching device and charge-storage device are substantially the same width. The memory cell structure is extremely small. The cell structure is highly resistant to alpha-particles and is formed self-aligned. During manufacture, the SiO.sub.2 island is oxidized adjacent its lower end to insulate the island from the substrate.
摘要翻译：半导体存储器包括分别设置在每个半导体岛的上侧和下侧的开关器件和电荷存储器件。这些岛形成在通过绝缘体与半导体衬底完全隔离的半导体衬底上。开关装置和充电存储装置的宽度基本相同。存储单元结构非常小。细胞结构对α粒子具有高度抗性，并形成自对准。在制造期间，SiO 2岛在其下端附近被氧化，以使岛与衬底绝缘。

10. 发明授权

US07310563B2 Fabrication system and fabrication method 失效
标题翻译：制造系统及制造方法
公开(公告)号：US07310563B2
公开(公告)日：2007-12-18
申请号：US11320778
申请日：2005-12-30
申请人： Natsuki Yokoyama , Yoshifumi Kawamoto , Eiichi Murakami , Fumihiko Uchida , Kenichi Mizuishi , Yoshio Kawamura
发明人： Natsuki Yokoyama , Yoshifumi Kawamoto , Eiichi Murakami , Fumihiko Uchida , Kenichi Mizuishi , Yoshio Kawamura
IPC分类号： G06F19/00
CPC分类号： C23C14/568 , C23C16/54 , G05B19/41865 , G05B2219/45031 , H01L21/67161 , H01L21/67167 , H01L21/67173 , H01L21/67184 , H01L21/67276 , H01L21/67727 , H01L21/67745 , Y02P90/14 , Y02P90/20 , Y02P90/28 , Y10S414/135 , Y10S414/137 , Y10S438/908 , Y10T29/41
摘要： A fabricating method for a system including a plurality of processing apparatuses connected to each other by an inter-apparatus transporter. The semiconductor waters are processed in the processing apparatuses and are transported to specified processing apparatuses in different time interval that are set to N times a unit time interval. Since the fabricating system includes processing apparatuses and an inter-apparatus transporter that are periodically controlled at time intervals related to a unit time, intervals related to a unit time, the scheduling of a plurality of works can be made efficiently to enhance the level of optimization, thus improving the productivity.
摘要翻译：一种用于系统的制造方法，包括通过机构间运送器彼此连接的多个处理装置。半导体水在处理装置中进行处理，并以不同的时间间隔被传送到规定的处理装置，时间间隔设定为单位时间间隔的N倍。由于制造系统包括以与单位时间相关的时间间隔周期性地控制的处理装置和装置间运输装置，所以与单位时间相关的间隔，可以有效地进行多个作业的调度以增强优化水平，从而提高生产率。

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