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1. 发明申请

US20130015158A1 DRY ETCHING METHOD 有权
标题翻译：干蚀刻方法
公开(公告)号：US20130015158A1
公开(公告)日：2013-01-17
申请号：US13210446
申请日：2011-08-16
申请人： Tomoyoshi Ichimaru , Kenichi Kuwabara , Go Saito
发明人： Tomoyoshi Ichimaru , Kenichi Kuwabara , Go Saito
IPC分类号： C23F1/02
CPC分类号： H01L21/28079 , H01J37/32192 , H01L21/31116 , H01L21/32137 , H01L29/66545
摘要： The present invention provides a dry etching method capable of readily providing rounded top edge portions, called top rounds, at trenches and vias formed by removal of a dummy material. The method of the present invention is a dry etching method for forming trenches or vias by removing a dummy material with its periphery surrounded by an interlayer oxide film, which method includes the steps of etching the dummy material to a predetermined depth, performing isotropic etching after the dummy material etching, and removing remaining part of the dummy material after the isotropic etching.
摘要翻译：本发明提供了一种干式蚀刻方法，其能够容易地提供在通过去除虚拟材料形成的沟槽和通孔处的称为顶部圆形的圆形顶部边缘部分。本发明的方法是通过去除其周围被层间氧化膜包围的虚拟材料形成沟槽或通孔的干蚀刻方法，该方法包括以下步骤：将虚拟材料蚀刻至预定深度，执行各向同性蚀刻虚拟材料蚀刻，并且在各向同性蚀刻之后除去虚拟材料的剩余部分。

2. 发明授权

US08580689B2 Plasma processing method 有权
标题翻译：等离子体处理方法
公开(公告)号：US08580689B2
公开(公告)日：2013-11-12
申请号：US13210446
申请日：2011-08-16
申请人： Tomoyoshi Ichimaru , Kenichi Kuwabara , Go Saito
发明人： Tomoyoshi Ichimaru , Kenichi Kuwabara , Go Saito
IPC分类号： H01L21/302
CPC分类号： H01L21/28079 , H01J37/32192 , H01L21/31116 , H01L21/32137 , H01L29/66545
摘要： The present invention provides a dry etching method capable of readily providing rounded top edge portions, called top rounds, at trenches and vias formed by removal of a dummy material. The method of the present invention is a dry etching method for forming trenches or vias by removing a dummy material with its periphery surrounded by an interlayer oxide film, which method includes the steps of etching the dummy material to a predetermined depth, performing isotropic etching after the dummy material etching, and removing remaining part of the dummy material after the isotropic etching.
摘要翻译：本发明提供了一种干式蚀刻方法，其能够容易地提供在通过去除虚拟材料形成的沟槽和通孔处的称为顶部圆形的圆形顶部边缘部分。本发明的方法是通过去除其周围被层间氧化膜包围的虚拟材料形成沟槽或通孔的干蚀刻方法，该方法包括以下步骤：将虚拟材料蚀刻至预定深度，执行各向同性蚀刻虚拟材料蚀刻，并且在各向同性蚀刻之后除去虚拟材料的剩余部分。

3. 发明授权

US08143175B2 Dry etching method 失效
标题翻译：干蚀刻法
公开(公告)号：US08143175B2
公开(公告)日：2012-03-27
申请号：US12435787
申请日：2009-05-05
申请人： Satoshi Une , Masamichi Sakaguchi , Kenichi Kuwabara , Tomoyoshi Ichimaru
发明人： Satoshi Une , Masamichi Sakaguchi , Kenichi Kuwabara , Tomoyoshi Ichimaru
IPC分类号： H01L21/31
CPC分类号： H01L21/32139 , H01L21/0338 , H01L21/28123 , H01L21/31116 , H01L21/32137
摘要： The invention provides a dry etching method for performing a wiring process on a semiconductor substrate using a plasma etching apparatus, wherein the wiring process is performed without causing disconnection or deflection of the wiring. The invention provides a dry etching method for performing a wiring process on a semiconductor substrate using a plasma etching apparatus, wherein during a step for etching a material 12 to be etched using a mask pattern composed of a photoresist 15 and inorganic films 14 and 13 made of SiN, SiON, SiO and the like formed on the material 12 to be etched, a mixed gas formed of a halogen-based gas such as chlorine-containing gas or bromine-containing gas and at least one fluorine-containing gas selected from a group of fluorine-containing gases composed of CF4, CHF3, SF6 and NF3 is used to reduce the mask pattern and the processing dimension of the material to be etched substantially equally during processing of the material 12 to be etched.
摘要翻译：本发明提供了一种用于使用等离子体蚀刻装置在半导体衬底上进行布线处理的干蚀刻方法，其中进行布线处理而不引起布线的断开或偏转。本发明提供一种使用等离子体蚀刻装置对半导体衬底进行布线处理的干式蚀刻方法，其中在使用由光致抗蚀剂15和无机膜14和13构成的掩模图案来蚀刻要蚀刻的材料12的步骤期间，在被蚀刻材料12上形成的SiN，SiON，SiO等，由含氯气体或含溴气体的卤素系气体形成的混合气体和至少一种选自使用由CF4，CHF3，SF6和NF3组成的含氟气体组，在待蚀刻材料12的加工期间，基本上相同地减少掩模图案和待蚀刻材料的加工尺寸。

4. 发明申请

US20100285669A1 DRY ETCHING METHOD 有权
标题翻译：干蚀刻方法
公开(公告)号：US20100285669A1
公开(公告)日：2010-11-11
申请号：US12512103
申请日：2009-07-30
申请人： Takeshi SHIMA , Kenichi Kuwabara , Tomoyoshi Ichimaru , Kenji Imamoto
发明人： Takeshi SHIMA , Kenichi Kuwabara , Tomoyoshi Ichimaru , Kenji Imamoto
IPC分类号： H01L21/3065
CPC分类号： H01L21/32139 , H01L21/02071 , H01L21/02115 , H01L21/02274
摘要： After etching a polysilicon film, when a protective film made of a carbon polymer is formed on a sidewall of the polysilicon film using plasma containing carbons, a metallic material as a lower film is etched using plasma containing a halogen gas under an etching condition in which volatility is improved due to the rise in a wafer temperature or the low pressure of a processing pressure, thereby preventing a side etching and unevenness of a sidewall of the polysilicon film. Further, by using the protective film made of a carbon polymer, metallic substances scattered at the time of etching the metallic material are not directly attached to the polysilicon film, but can be simply removed along with the protective film made of a carbon polymer in an asking step.
摘要翻译：在蚀刻多晶硅膜之后，当使用含有碳的等离子体在多晶硅膜的侧壁上形成由碳聚合物制成的保护膜时，在蚀刻条件下，使用含有卤素气体的等离子体蚀刻作为下部膜的金属材料，其中由于晶片温度的上升或处理压力的低压，挥发性提高，从而防止多晶硅膜的侧壁蚀刻和不均匀。此外，通过使用由碳聚合物制成的保护膜，在蚀刻金属材料时分散的金属物质不直接附着在多晶硅膜上，而是可以简单地与由碳聚合物制成的保护膜一起除去问一步

5. 发明申请

US20070218696A1 Dry etching method 审中-公开
标题翻译：干蚀刻法
公开(公告)号：US20070218696A1
公开(公告)日：2007-09-20
申请号：US11509736
申请日：2006-08-25
申请人： Kenichi Kuwabara , Satoshi Une , Tomoyoshi Ichimaru , Masamichi Sakaguchi , Naoki Yasui
发明人： Kenichi Kuwabara , Satoshi Une , Tomoyoshi Ichimaru , Masamichi Sakaguchi , Naoki Yasui
IPC分类号： H01L21/465
CPC分类号： H01L21/32137
摘要： The invention provides a method for processing vertical gate patterns while reducing the Si substrate recess dimension caused by overetching. The invention provides a dry etching method for processing a gate pattern by performing a main etching process (b) and then an overetching process on a gate pattern layer 12 of a semiconductor substrate 10, wherein the overetching process (c) is performed using a composite gas having added to an etching gas containing HBr gas a gas represented by a general formula of CxHy or at least one gas selected from CO and CO2 gases.
摘要翻译：本发明提供了一种在减少由过蚀刻引起的Si衬底凹陷尺寸的同时处理垂直栅极图案的方法。本发明提供一种通过在半导体衬底10的栅极图案层12上执行主蚀刻工艺（b）然后进行过蚀刻处理来进行栅极图案的干式蚀刻方法，其中过蚀刻工艺（c）使用复合材料已经添加到含有HBr气体的蚀刻气体的气体是由通式C x H y表示的气体或选自CO和CO 2气体的至少一种气体。

6. 发明授权

US07989330B2 Dry etching method 有权
标题翻译：干蚀刻法
公开(公告)号：US07989330B2
公开(公告)日：2011-08-02
申请号：US12512103
申请日：2009-07-30
申请人： Takeshi Shima , Kenichi Kuwabara , Tomoyoshi Ichimaru , Kenji Imamoto
发明人： Takeshi Shima , Kenichi Kuwabara , Tomoyoshi Ichimaru , Kenji Imamoto
IPC分类号： H01L21/20
CPC分类号： H01L21/32139 , H01L21/02071 , H01L21/02115 , H01L21/02274
摘要： After etching a polysilicon film, when a protective film made of a carbon polymer is formed on a sidewall of the polysilicon film using plasma containing carbons, a metallic material as a lower film is etched using plasma containing a halogen gas under an etching condition in which volatility is improved due to the rise in a wafer temperature or the low pressure of a processing pressure, thereby preventing a side etching and unevenness of a sidewall of the polysilicon film. Further, by using the protective film made of a carbon polymer, metallic substances scattered at the time of etching the metallic material are not directly attached to the polysilicon film, but can be simply removed along with the protective film made of a carbon polymer in an asking step.
摘要翻译：在蚀刻多晶硅膜之后，当使用含有碳的等离子体在多晶硅膜的侧壁上形成由碳聚合物制成的保护膜时，在蚀刻条件下，使用含有卤素气体的等离子体蚀刻作为下部膜的金属材料，其中由于晶片温度的上升或处理压力的低压，挥发性提高，从而防止多晶硅膜的侧壁蚀刻和不均匀。此外，通过使用由碳聚合物制成的保护膜，在蚀刻金属材料时分散的金属物质不直接附着于多晶硅膜，而是可以简单地与由碳聚合物制成的保护膜一起除去问一步

7. 发明申请

US20070207618A1 Dry etching method 审中-公开
标题翻译：干蚀刻法
公开(公告)号：US20070207618A1
公开(公告)日：2007-09-06
申请号：US11505292
申请日：2006-08-17
申请人： Satoshi Une , Masamichi Sakaguchi , Kenichi Kuwabara , Tomoyoshi Ichimaru
发明人： Satoshi Une , Masamichi Sakaguchi , Kenichi Kuwabara , Tomoyoshi Ichimaru
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/32139 , H01L21/0338 , H01L21/28123 , H01L21/31116 , H01L21/32137
摘要： The invention provides a dry etching method for performing a wiring process on a semiconductor substrate using a plasma etching apparatus, wherein the wiring process is performed without causing disconnection or deflection of the wiring. The invention provides a dry etching method for performing a wiring process on a semiconductor substrate using a plasma etching apparatus, wherein during a step for etching a material 12 to be etched using a mask pattern composed of a photoresist 15 and inorganic films 14 and 13 made of SiN, SiON, SiO and the like formed on the material 12 to be etched, a mixed gas formed of a halogen-based gas such as chlorine-containing gas or bromine-containing gas and at least one fluorine-containing gas selected from a group of fluorine-containing gases composed of CF4, CHF3, SF6 and NF3 is used to reduce the mask pattern and the processing dimension of the material to be etched substantially equally during processing of the material 12 to be etched.
摘要翻译：本发明提供了一种用于使用等离子体蚀刻装置在半导体衬底上进行布线处理的干蚀刻方法，其中进行布线处理而不引起布线的断开或偏转。本发明提供一种使用等离子体蚀刻装置对半导体衬底进行布线处理的干式蚀刻方法，其中在使用由光致抗蚀剂15和无机膜14和13构成的掩模图案来蚀刻要蚀刻的材料12的步骤期间，在被蚀刻材料12上形成的SiN，SiON，SiO等，由含氯气体或含溴气体的卤素系气体形成的混合气体和至少一种选自使用由CF 4，CHF 3，SF 6和NF 3 3构成的含氟气体组，在要蚀刻的材料12的处理期间，基本上相同地减小掩模图案和待蚀刻材料的加工尺寸。

8. 发明申请

US20100288195A1 PLASMA PROCESSING METHOD AND APPARATUS 审中-公开
标题翻译：等离子体处理方法和装置
公开(公告)号：US20100288195A1
公开(公告)日：2010-11-18
申请号：US12846403
申请日：2010-07-29
申请人： Eiji IKEGAMI , Shoji Ikuhara , Takeshi Shimada , Kenichi Kuwabara , Takao Arase , Tsuyoshi Matsumoto
发明人： Eiji IKEGAMI , Shoji Ikuhara , Takeshi Shimada , Kenichi Kuwabara , Takao Arase , Tsuyoshi Matsumoto
IPC分类号： C23C16/00
CPC分类号： H01J37/32963 , H01J37/32082 , H01J37/32091 , H01J37/321 , H01J37/3211 , H01J37/32192 , H01J37/32917 , H01J37/32926 , H01J37/32935 , H01J37/32981 , H01J37/3299 , H01J2237/1825 , H01J2237/327 , H01L21/67069 , H01L21/67242 , H05H1/46
摘要： Plasma processing of plural substrates is performed in a plasma processing apparatus, which is provided with a plasma processing chamber having an antenna electrode and a lower electrode for placing and retaining the plural substrates in turn within the plasma processing chamber, a gas feeder for feeding processing gas into the processing chamber, a vacuum pump for discharging gas from the processing chamber via a vacuum valve, and a solenoid coil for forming a magnetic field within the processing chamber. At least one of the plural substrates is placed on the lower electrode, and the processing gas is fed into the processing chamber. RF power is fed to the antenna electrode via a matching network to produce a plasma within the processing chamber in which a magnetic field has been formed by the solenoid coil. This placing of at least one substrate and this feeding of the processing gas are then repeated until the plasma processing of all of the plural substrates is completed. An end of seasoning is determined when a parameter including an internal pressure of the processing chamber has become stable to a steady value with plasma processing time.
摘要翻译：在具有等离子体处理室的等离子体处理装置中进行多个基板的等离子体处理，该等离子体处理室具有用于在等离子体处理室内依次放置和保持多个基板的天线电极和下部电极，供给处理用气体供给装置气体进入处理室，用于经由真空阀从处理室排出气体的真空泵和用于在处理室内形成磁场的螺线管线圈。多个基板中的至少一个被放置在下电极上，并且处理气体被馈送到处理室中。 RF功率经由匹配网络馈送到天线电极，以在处理室内产生等离子体，其中已经由螺线管线圈形成了磁场。然后重复这种至少一个基板的放置和该处理气体的进料，直至完成所有多个基板的等离子体处理。当包括处理室的内部压力的参数在具有等离子体处理时间的稳定值变得稳定时，确定调味品的结束。

9. 发明授权

US07130832B2 Energy service business method and system 有权
公开(公告)号：US07130832B2
公开(公告)日：2006-10-31
申请号：US09843736
申请日：2001-04-30
申请人： Masaaki Bannai , Junichi Chiba , Kenichi Kuwabara , Sadakazu Kamo
发明人： Masaaki Bannai , Junichi Chiba , Kenichi Kuwabara , Sadakazu Kamo
IPC分类号： G06F17/00 , G06F9/44
CPC分类号： G06Q10/06 , G06Q10/06375 , G06Q50/06 , H02J3/008 , Y02E40/76 , Y02P80/10 , Y02P80/11 , Y02P90/86 , Y04S10/545 , Y04S50/00 , Y04S50/10
摘要： If the energy service enterprise is responsible for paying costs for applying energy-saving measures to the object facilities, measures the energy consumption after taking the energy-saving measures, calculates the amount of curtailed energy cost by comparing the measured value with the energy consumption before taking the energy-saving measures previously stored in the database, and receives at least a part of the curtailed amount, the customer is not required to plan equipment investment in energy-saving measures and collection thereof. Introduction of the energy-saving measures is thus made easier.

10. 发明授权

US07112805B2 Vacuum processing apparatus and vacuum processing method 失效
标题翻译：真空加工设备和真空加工方法
公开(公告)号：US07112805B2
公开(公告)日：2006-09-26
申请号：US10875231
申请日：2004-06-25
申请人： Yoshitaka Kai , Kenichi Kuwabara , Takeo Uchino , Yasuhiro Nishimori , Takeshi Oono , Takeshi Shimada
发明人： Yoshitaka Kai , Kenichi Kuwabara , Takeo Uchino , Yasuhiro Nishimori , Takeshi Oono , Takeshi Shimada
IPC分类号： G01F23/00 , G01K5/08
CPC分类号： H01L21/67207 , H01L21/67167
摘要： The invention provides a semiconductor fabrication apparatus capable of preventing increase of carriage time of samples, deterioration of sample output, increase of footprint and increase of investment costs. The vacuum processing apparatus comprises a plurality of vacuum processing chambers for subjecting a sample to vacuum processing; a vacuum carriage for carrying the sample into and out of the vacuum processing chamber; a switchable chamber capable of being switched between atmosphere and vacuum for carrying the sample into and out of the vacuum processing chamber; a cassette support for supporting a plurality of cassettes and a controller for controlling carrying of the sample from a cassette through the switchable chambers, the vacuum carriage means into and out of the vacuum processing chamber. The vacuum processing chamber is equipped with an etching chamber and a critical dimension measurement chamber for critical dimension inspection of the sample.
摘要翻译：本发明提供一种半导体制造装置，其能够防止样品的携带时间增加，样品输出的劣化，占地面积的增加和投资成本的增加。真空处理装置包括用于对样品进行真空处理的多个真空处理室; 用于将样品进入和离开真空处理室的真空托架; 能够在大气和真空之间切换以将样品进出真空处理室的可切换室; 用于支撑多个盒的盒支撑件和控制器，用于控制样品从盒通过可切换室的携带，真空托架装置进入和离开真空处理室。真空处理室配有蚀刻室和临界尺寸测量室，用于对样品进行临界尺寸检验。

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