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1. 发明申请

US20070219660A1 Substrate transporting and processing apparatus, fault management method for substrate transport and processing apparatus, and storage medium storing fault management program 审中-公开
标题翻译：基板运输和处理装置，基板运输和处理装置的故障管理方法以及存储故障管理程序的存储介质
公开(公告)号：US20070219660A1
公开(公告)日：2007-09-20
申请号：US11600905
申请日：2006-11-17
申请人： Tomohiro Kaneko , Akira Miyata
发明人： Tomohiro Kaneko , Akira Miyata
IPC分类号： G06F19/00
CPC分类号： H01L21/67271 , H01L21/67745
摘要： Disclosed is a countermeasure to be taken when a fault occurs in one of process modules 11-17 or a transport module 20 that makes it impossible to transport substrates to a process module positioned downstream of a post-exposure baking module 15 in accordance with a predetermined transport schedule in a post-exposure substrate transport path that starts from an exposure apparatus 5 and goes through the post-exposure baking (PEB) module 15, a developing module 12, and a post-development baking module 15. In this instance, part of post-exposure processes to a post-exposure baking process are continuously performed to the exposed substrates and the wafers W having been subjected to the PEB process are loaded into a buffer module 32 and temporarily stored in the buffer module 32 until the fault is cleared. This prevents increase in the time period from an exposure process completion to the post-exposure baking process even when the fault occurs, thereby avoiding defective line width the circuit pattern of a resist, particularly a chemically amplified resist.
摘要翻译：公开了当在处理模块11-17中的一个发生故障时发生的对策或者使得不可能根据预定的方式将基板输送到位于后曝光烘焙模块15下游的处理模块的传送模块20 从曝光装置5开始并经过曝光后烘烤（PEB）模块15，显影模块12和后期显影烘烤模块15的曝光后基板传送路径中的传送时间表。在这种情况下，对暴露的基板连续地进行对曝光后烘烤处理的后曝光处理的一部分，并且已经经过PEB处理的晶片W被加载到缓冲模块32中并临时存储在缓冲模块32中直到故障清除。即使发生故障，也能够防止从曝光处理完成到曝光后烘烤处理的时间段的增加，从而避免了抗蚀剂，特别是化学放大抗蚀剂的电路图案的有缺陷的线宽。

2. 发明授权

US07599042B2 Coating and developing apparatus, substrate processing method and computer-readable recording medium 有权
标题翻译：涂布显影装置，基板处理方法和计算机可读记录介质
公开(公告)号：US07599042B2
公开(公告)日：2009-10-06
申请号：US12179014
申请日：2008-07-24
申请人： Akira Miyata , Tomohiro Kaneko
发明人： Akira Miyata , Tomohiro Kaneko
IPC分类号： G03B27/32 , G03D5/00 , G06F19/00
CPC分类号： H01L21/67276
摘要： With regard to a group of substrates preceding a substrate of which residence time is under calculation, a time t1 and a time t2 are calculated, t1 being a time interval from a time point in which a substrate B1 under the consideration has become ready from being transferred out from a wait module to a time point in which a heating module used for the substrate B1 has been ready for processing the substrate B1, t2 being a time interface from a time on in which the substrate B1 under calculation has been transferred out from the wait module to a time point of reaching the heating module used for the substrate B1, and a waiting time t of the substrate B1 in the wait module is calculated according to t=t1−t2.
摘要翻译：对于在其计算停留时间的基板之前的一组基板，计算时间t1和时间t2，t1是从考虑中的基板B1准备好的时间点开始的时间间隔从等待模块传出到用于基板B1的加热模块已经准备好处理基板B1的时间点，t2是从计算中的基板B1已被转出的时间的时间界面等待模块到达用于基板B1的加热模块的时间点，以及根据t = t1-t2计算等待模块中的基板B1的等待时间t。

3. 发明授权

US07563043B2 Coating/developing apparatus and substrate transfer method 有权
标题翻译：涂布/显影装置和底物转印方法
公开(公告)号：US07563043B2
公开(公告)日：2009-07-21
申请号：US11877324
申请日：2007-10-23
申请人： Tomohiro Kaneko , Akira Miyata
发明人： Tomohiro Kaneko , Akira Miyata
IPC分类号： G03D5/00 , B05C11/00 , G03B27/32 , G06F19/00
CPC分类号： G03F7/7075 , H01L21/67225 , H01L21/67276 , Y10S414/135
摘要： In a coating/developing apparatus, a process section includes post-exposure baking units each having a waiting position and configured to perform a baking process on a substrate. An interface section transfer mechanism includes a first transfer mechanism configured to transfer the substrate to and from the process section and to load the substrate into the post-exposure baking units, and a second transfer mechanism configured to transfer the substrate to and from the light exposure apparatus. An interface section includes a relay position configured to place thereon the substrate transferred by the second transfer mechanism, and to allow the first transfer mechanism to receive the substrate therefrom. A control section is arranged to set the substrate on standby at the relay position and the waiting position, to make a time period constant among substrates from an end of the light exposure process to a start of a post-exposure baking process.
摘要翻译：在涂布/显影装置中，处理部分包括具有等待位置并被配置为在基板上进行烘烤处理的后曝光烘焙单元。接口部分传送机构包括第一传送机构，其被配置为将基板传送到处理部分并从处理部分传送基板并将基板装载到后曝光烘烤单元中;以及第二传送机构，其被配置为将基板传送到曝光和从曝光仪器。接口部分包括被配置为放置在其上由第二传送机构传送的基板并且允许第一传送机构从其接收基板的中继位置。控制部被配置为将基板设置在继电器位置和待机位置的待机状态，使得从曝光过程结束到曝光后烘烤处理开始之间的基板之间的时间段恒定。

4. 发明申请

US20090041926A1 COATING AND DEVELOPING APPARATUS, SUBSTRATE PROCESSING METHOD AND COMPUTER-READABLE RECORDING MEDIUM 有权
标题翻译：涂层和开发设备，基板处理方法和计算机可读记录介质
公开(公告)号：US20090041926A1
公开(公告)日：2009-02-12
申请号：US12179014
申请日：2008-07-24
申请人： Akira Miyata , Tomohiro Kaneko
发明人： Akira Miyata , Tomohiro Kaneko
IPC分类号： C23C16/52 , B05C11/00
CPC分类号： H01L21/67276
摘要： With regard to a group of substrates preceding a substrate of which residence time is under calculation, a time t1 and a time t2 are calculated, t1 being a time interval from a time point in which a substrate B1 under the consideration has become ready from being transferred out from a wait module to a time point in which a heating module used for the substrate B1 has been ready for processing the substrate B1, t2 being a time interface from a time on in which the substrate B1 under calculation has been transferred out from the wait module to a time point of reaching the heating module used for the substrate B1, and a waiting time t of the substrate B1 in the wait module is calculated according to t=t1−t2.
摘要翻译：对于在其计算停留时间的基板之前的一组基板，计算时间t1和时间t2，t1是从考虑中的基板B1准备好的时间点开始的时间间隔从等待模块传出到用于基板B1的加热模块已经准备好处理基板B1的时间点，t2是从计算中的基板B1已被转出的时间的时间界面等待模块到达用于基板B1的加热模块的时间点，以及根据t = t1-t2计算等待模块中的基板B1的等待时间t。

5. 发明申请

US20070250202A1 COATING AND DEVELOPING SYSTEM, METHOD OF CONTROLLING COATING AND DEVELOPING SYSTEM AND STORAGE MEDIUM 审中-公开
标题翻译：涂料与开发系统，涂料和发展体系与储存介质的控制方法
公开(公告)号：US20070250202A1
公开(公告)日：2007-10-25
申请号：US11734088
申请日：2007-04-11
申请人： Tomohiro Kaneko , Akira Miyata
发明人： Tomohiro Kaneko , Akira Miyata
IPC分类号： G06F19/00 , B05C11/00
CPC分类号： H01L21/67745 , H01L21/67276
摘要： A coating and developing system includes a cassette station, a processing station and an inspection station interposed between the cassette station and the processing station. Time for which a substrate is held uselessly in the inspection module is reduced. A substrate carrying means disposed in the inspection module places priority to transferring a substrate between the cassette station and the processing station, and transfers a substrate to an inspection module in a part of a cycle time in which a substrate carrying means disposed in the processing station carries out one carrying cycle. It is permitted to carry out a substrate from the inspection module in a skip carrying mode, in which a substrate specified by a larger ordinal numeral is carried ahead of a substrate specified by a smaller ordinal numeral. It is inhibited to carry a substrate to the inspection module in the skip carrying mode.
摘要翻译：涂装和显影系统包括一个盒式磁带站，一个处理站和一个插入在磁带站和处理站之间的检查站。基板在检查模块中无用的时间减少了。设置在检查模块中的基板承载装置优先地将基板传送到盒站和处理站之间，并且在循环时间的一部分中将基板传送到检查模块，其中设置在处理站中的基板承载装置执行一个携带循环。允许以跳过方式从检查模块执行基板，其中由较小的数字指定的基板在由较小的数字指定的基板的前面进行。在跳过运行模式下，禁止将基板运送到检查模块。

6. 发明申请

US20060287200A1 Substrate processing system and substrate processing method 审中-公开
标题翻译：基板加工系统和基板加工方法
公开(公告)号：US20060287200A1
公开(公告)日：2006-12-21
申请号：US11436700
申请日：2006-05-19
申请人： Tomohiro Kaneko , Akira Miyata
发明人： Tomohiro Kaneko , Akira Miyata
IPC分类号： C04B35/45
CPC分类号： G03F7/7075 , G03F7/70533 , H01L21/67155 , H01L21/67173 , H01L21/67184 , H01L21/67196 , H01L21/67253 , H01L21/67276
摘要： A substrate processing system 100 and a substrate processing method process a plurality of substrates in a single-substrate processing mode by the cooperative operation of a first processing system and a second processing system. The substrate processing system 100 suppresses increase in cost and footprint and the reduction of yield and throughput. The substrate processing system 100 includes a first processing system 50 for processing substrates in a single-substrate processing mode and a second processing system 60 for processing substrates in a single-substrate processing mode. The second processing system 60 processes a substrate processed by a first process by the first processing system 50 by a second process, and the first processing system processes the substrate processed by the second process by the second processing system 60 by a third process. The first processing system 50 includes a first control means 30 for controlling a substrate carrying operation. The second processing system 60 includes a second control means 40. The first control means 30 (or the second control means 40) obtains information about processing time needed by the second processing system 60 (the first processing system 50) and controls a substrate carrying operation for carrying substrates between the first processing system 50 and the second processing system 60 on the basis of the obtained information.
摘要翻译：基板处理系统100和基板处理方法通过第一处理系统和第二处理系统的协作操作以单基板处理模式处理多个基板。基板处理系统100抑制成本和占地面积的增加以及产量和产量的降低。基板处理系统100包括用于以单基板处理模式处理基板的第一处理系统50和用于以单基板处理模式处理基板的第二处理系统60。第二处理系统60通过第二处理处理由第一处理系统50进行的第一处理的基板，第一处理系统通过第三处理由第二处理系统60处理由第二处理处理的基板。第一处理系统50包括用于控制基板承载操作的第一控制装置30。第二处理系统60包括第二控制装置40.第一控制装置30（或第二控制装置40）获得关于第二处理系统60（第一处理系统50）所需的处理时间的信息，并控制基板承载操作用于基于获得的信息在第一处理系统50和第二处理系统60之间承载基板。

7. 发明授权

US08747949B2 Coating and developing system, method of controlling coating and developing system and storage medium 有权
标题翻译：涂料和显影系统，涂料和显影系统和储存介质的控制方法
公开(公告)号：US08747949B2
公开(公告)日：2014-06-10
申请号：US12902529
申请日：2010-10-12
申请人： Tomohiro Kaneko , Akira Miyata
发明人： Tomohiro Kaneko , Akira Miyata
IPC分类号： H01L21/02 , H01L21/027 , H01L21/67 , H01L21/673 , H01L21/677
CPC分类号： H01L21/67745 , H01L21/67276
摘要： A coating and developing system includes a cassette station, a processing station and an inspection station interposed between the cassette station and the processing station. Time for which a substrate is held uselessly in the inspection module is reduced. A substrate carrying means disposed in the inspection module places priority to transferring a substrate between the cassette station and the processing station, and transfers a substrate to an inspection module in a part of a cycle time in which a substrate carrying means disposed in the processing station carries out one carrying cycle. It is permitted to carry out a substrate from the inspection module in a skip carrying mode, in which a substrate specified by a larger ordinal numeral is carried ahead of a substrate specified by a smaller ordinal numeral. It is inhibited to carry a substrate to the inspection module in the skip carrying mode.
摘要翻译：涂装和显影系统包括一个盒式磁带站，一个处理站和一个插入在磁带站和处理站之间的检查站。基板在检查模块中无用的时间减少了。设置在检查模块中的基板承载装置优先地将基板传送到盒站和处理站之间，并且在循环时间的一部分中将基板传送到检查模块，其中布置在处理站中的基板承载装置执行一个携带循环。允许以跳过方式从检查模块执行基板，其中由较小的数字指定的基板在由较小的数字指定的基板的前面进行。在跳过运行模式下，禁止将基板运送到检查模块。

8. 发明授权

US08393845B2 Substrate convey processing device, trouble countermeasure method in substrate convey processing device, and trouble countermeasures program in substrate convey processing device 有权
标题翻译：基板输送处理装置，基板输送处理装置中的故障对策方法以及基板输送处理装置中的故障对策程序
公开(公告)号：US08393845B2
公开(公告)日：2013-03-12
申请号：US11813925
申请日：2006-01-18
申请人： Tomohiro Kaneko , Yoshitaka Hara , Akira Miyata
发明人： Tomohiro Kaneko , Yoshitaka Hara , Akira Miyata
IPC分类号： B65H1/00
CPC分类号： H01L21/67745 , H01L21/67276
摘要： A plurality of process modules for conducting processes on a wafer; conveying modules for conveying the wafer, a turnout module for transferring the wafer to/from the conveying module, and a CPU for detecting a trouble occurring in the process module and centrally controlling each of the modules based on a detection signal. When the controller detects the trouble occurring in any one of the process modules, the wafer to be conveyed to the process module where the trouble occurs is conveyed to the turnout module, and conveyance of the wafer before the process module where the trouble occurs is temporarily stopped, and conveyance and processing of the other wafer are continued, and thereafter, conveyance and processing of the wafer before the process module where the trouble occurs are conducted.
摘要翻译：用于在晶片上进行处理的多个处理模块; 用于传送晶片的输送模块，用于将晶片传送到/从输送模块传送的转向模块;以及CPU，用于检测在处理模块中发生的故障，并且基于检测信号集中控制模块。当控制器检测到任何一个处理模块发生故障时，要传送到发生故障的处理模块的晶片被传送到投票模块，并且在发生故障的处理模块之前的晶片的传送是暂时的停止，继续进行其他晶片的输送和处理，然后进行在发生故障的处理模块之前的晶片的输送和处理。

9. 发明授权

US07575382B2 Coating/developing apparatus and operation method thereof 失效
标题翻译：涂布/显影装置及其操作方法
公开(公告)号：US07575382B2
公开(公告)日：2009-08-18
申请号：US12166470
申请日：2008-07-02
申请人： Tomohiro Kaneko , Akira Miyata
发明人： Tomohiro Kaneko , Akira Miyata
IPC分类号： G03D5/00 , G03B27/32 , G06F19/00
CPC分类号： G03B27/32
摘要： A coating/developing apparatus has a carrier block including a first transfer device, a process block including processing modules, an examination block including examination modules and a second transfer device, and first to forth stages. A controller executes a first operation mode preset to transfer substrates from the process block and carrier block into the examination block in parallel. The first operation mode includes transferring substrates processed by the process block to the third or fourth stage through or not through an examination module by the second transfer device, transferring substrates to be only examined from a carrier in the carrier block to the second stage by the first transfer device, and transferring these substrates from the second stage to an examination modules by the second transfer device, and transferring substrates thus examined from the examination block to the third or fourth stage by the second transfer device.
摘要翻译：涂覆/显影装置具有载体块，其包括第一转印装置，包括处理模块的处理块，包括检查模块和第二转印装置的检查块以及第一至第四级。控制器执行预设的第一操作模式以将基板从处理块和载体块并行地传送到检查块中。第一操作模式包括通过第二传送装置将通过或不通过检查模块将由处理块处理的衬底转移到第三或第四阶段，将仅被检查的衬底从载体块中的载体传送到第二级，由第一转印装置，并且通过第二转印装置将这些基板从第二阶段转印到检查模块，以及通过第二转印装置将从检查块转移到第三或第四阶段的基板。

10. 发明授权

US07844359B2 Coating and developing apparatus, operating method for same, and storage medium for the method 有权
标题翻译：涂料和显影装置，其操作方法和方法的存储介质
公开(公告)号：US07844359B2
公开(公告)日：2010-11-30
申请号：US12128437
申请日：2008-05-28
申请人： Tomonori Shin , Kouji Okamura , Tomohiro Kaneko , Akira Miyata , Syuzo Fujimaru
发明人： Tomonori Shin , Kouji Okamura , Tomohiro Kaneko , Akira Miyata , Syuzo Fujimaru
IPC分类号： G06F19/00 , H01L21/00
CPC分类号： H01L21/67225 , H01L21/67276
摘要： In a coating and developing apparatus applied to liquid-immersion light exposure, substrates without an appropriately formed protective film can be recovered without adversely affecting normal-substrate processing efficiency, and in addition, removal of protective films can be simplified. In the coating and developing apparatus of the present invention, abnormal substrates not appropriately surface-coated with a protective film during liquid-immersion light exposure are queued in a queuing module, instead of being loaded into an exposure unit, and after the immediately preceding substrate has been unloaded from the exposure unit and loaded into a designated module, for example, a pre-developing second heating module, each abnormal substrate is loaded into the designated module in order to prevent so-called “scheduled transfer” from being affected, and a protective-film removing unit is also controlled to process the abnormal substrate.
摘要翻译：在适用于液浸式曝光的涂布显影装置中，可以回收没有适当形成的保护膜的基板，而不会不利地影响正常的基板处理效率，另外可以简化保护膜的去除。在本发明的涂布和显影装置中，在液浸式曝光期间不被适当表面涂覆有保护膜的异常基板排队在排队模块中，而不是装载到曝光单元中，并且在紧接在前面的基板已经从曝光单元卸载并加载到指定的模块中，例如预先显影的第二加热模块中，每个异常基板被装载到指定模块中，以防止所谓的“计划传送”受到影响，并且还控制保护膜去除单元以处理异常衬底。

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