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1. 发明授权

US06900999B1 Ternary content addressable memory (TCAM) cells with small footprint size and efficient layout aspect ratio 有权
标题翻译：三元内容可寻址内存（TCAM）单元，占地面积小，布局纵横比高
公开(公告)号：US06900999B1
公开(公告)日：2005-05-31
申请号：US10609756
申请日：2003-06-30
申请人： Ting-Pwu Yen , Kee Park
发明人： Ting-Pwu Yen , Kee Park
IPC分类号： G11C15/04
CPC分类号： G11C15/04
摘要： Ternary CAM cells are provided that have extremely small layout footprint size and efficient layout aspect ratios that enhance scalability. The cells also have high degrees of symmetry that facilitate high yield interconnections to bit, data and match lines. A 16T ternary CAM cell includes first and second pairs of access transistors that extend adjacent a first side of the cell, and first and second pairs of cross-coupled inverters that extend adjacent a second side of the cell. First and second halves of a 4T compare circuit are also provided. The first half of the 4T compare circuit is positioned so that is extends between the first pair of access transistors and the first pair of cross-coupled inverters. Similarly, the second half of the 4T compare circuit is positioned so that it extends between the second pair of access transistors and the second pair of cross-coupled inverters.
摘要翻译：提供三进制CAM单元，其具有非常小的布局尺寸和有效的布局纵横比，从而提高可扩展性。这些单元还具有高度的对称性，可以实现位，数据和匹配线的高产出互连。 16T三元CAM单元包括在单元的第一侧附近延伸的第一和第二对存取晶体管，以及在单元的第二面附近延伸的第一和第二对交叉耦合的反相器。还提供了4T比较电路的第一和第二半。定位4T比较电路的前半部分，使其在第一对存取晶体管和第一对交叉耦合的反相器之间延伸。类似地，4T比较电路的第二半被定位成使得其在第二对存取晶体管和第二对交叉耦合的反相器之间延伸。

2. 发明申请

US20050135134A1 TERNARY CONTENT ADDRESSABLE MEMORY (TCAM) CELLS WITH SMALL FOOTPRINT SIZE AND EFFICIENT LAYOUT ASPECT RATIO 有权
标题翻译：三维内容可寻址记忆体（TCAM）细胞，具有小的尺寸和有效的布局宽度比
公开(公告)号：US20050135134A1
公开(公告)日：2005-06-23
申请号：US10609756
申请日：2003-06-30
申请人： Ting-Pwu Yen , Kee Park
发明人： Ting-Pwu Yen , Kee Park
IPC分类号： G11C15/04 , G11C15/00
CPC分类号： G11C15/04
摘要： Ternary CAM cells are provided that have extremely small layout footprint size and efficient layout aspect ratios that enhance scalability. The cells also have high degrees of symmetry that facilitate high yield interconnections to bit, data and match lines. A 16T ternary CAM cell includes first and second pairs of access transistors that extend adjacent a first side of the cell, and first and second pairs of cross-coupled inverters that extend adjacent a second side of the cell. First and second halves of a 4T compare circuit are also provided. The first half of the 4T compare circuit is positioned so that is extends between the first pair of access transistors and the first pair of cross-coupled inverters. Similarly, the second half of the 4T compare circuit is positioned so that it extends between the second pair of access transistors and the second pair of cross-coupled inverters.
摘要翻译：提供三进制CAM单元，其具有非常小的布局尺寸和有效的布局纵横比，从而提高可扩展性。这些单元还具有高度的对称性，可以实现位，数据和匹配线的高产出互连。 16T三元CAM单元包括在单元的第一侧附近延伸的第一和第二对存取晶体管，以及在单元的第二面附近延伸的第一和第二对交叉耦合的反相器。还提供了4T比较电路的第一和第二半。定位4T比较电路的前半部分，使其在第一对存取晶体管和第一对交叉耦合的反相器之间延伸。类似地，4T比较电路的第二半被定位成使得其在第二对存取晶体管和第二对交叉耦合的反相器之间延伸。

3. 发明授权

US5477074A Semiconductor structure using local planarization with self-aligned transistors 失效
标题翻译：半导体结构采用局部平面化与自对准晶体管
公开(公告)号：US5477074A
公开(公告)日：1995-12-19
申请号：US294228
申请日：1994-08-22
申请人： Ting-Pwu Yen
发明人： Ting-Pwu Yen
IPC分类号： H01L21/3205 , H01L21/768 , H01L21/8238 , H01L27/092 , H01L23/48
CPC分类号： H01L21/76895 , C03C15/00 , Y10S148/133
摘要： A CMOS integrated circuit uses self-aligned transistors combined with local planarization in the vicinity of the transistors so as allow local interconnects which are free of bridging, have good continuity over the planarized topography and are compatible with the self-alignment schemes, hence conserving chip real estate. After formation of self-aligned insulated transistor gates and active transistor regions, the integrated circuit structure is planarized by formation of an oxide layer and a reflowed overlying glass layer. The glass layer and underlying oxide layer are removed only in the area of the buried contact, while an overlying metal or polysilicon conductive layer contacts the upper surface of certain of the transistor gate structures, the topside insulating layer of which has been removed for this purpose.
摘要翻译： CMOS集成电路使用与晶体管附近的局部平坦化结合的自对准晶体管，从而允许不具有桥接的局部互连，在平坦化地形上具有良好的连续性，并且与自对准方案兼容，因此节省芯片房地产。在形成自对准绝缘晶体管栅极和有源晶体管区域之后，通过形成氧化物层和回流的上覆玻璃层来平坦化集成电路结构。玻璃层和下面的氧化物层仅在掩埋触点的区域中被去除，而上覆的金属或多晶硅导电层接触某些晶体管栅极结构的上表面，其顶面绝缘层为此目的被去除。

4. 发明授权

US5340774A Semiconductor fabrication technique using local planarization with self-aligned transistors 失效
标题翻译：使用具有自对准晶体管的局部平坦化的半导体制造技术
公开(公告)号：US5340774A
公开(公告)日：1994-08-23
申请号：US013466
申请日：1993-02-04
申请人： Ting-Pwu Yen
发明人： Ting-Pwu Yen
IPC分类号： H01L21/3205 , H01L21/768 , H01L21/8238 , H01L27/092 , H01L21/283
CPC分类号： H01L21/76895 , C03C15/00 , Y10S148/133
摘要： A CMOS integrated circuit fabrication technique for forming self-aligned transistors combined with local planarization in the vicinity of the transistors so as to allow local interconnects which are free of bridging, have good continuity over the planarized topography and are compatible with the self-alignment schemes, hence conserving chip real estate. The technique is compatible with planarization schemes using BPSG, BPTEOS, SOG or CMP. After formation of self-aligned insulated transistor gates and active transistor regions, the integrated circuit structure is planarized by formation of an oxide layer and a reflowed overlying glass layer. The glass layer is etched back to planarize the surface. Using a buried contact mask the remaining portions of the glass layer and underlying oxide layer are removed in the area of the buried contact only. In one version (prior to formation of the oxide layer and glass layer) a polysilicon "landing pad" is formed on the substrate at the buried contact location so as to allow more effective etching at the exact location of the buried contact.
摘要翻译：一种CMOS集成电路制造技术，用于形成与晶体管附近的局部平坦化结合的自对准晶体管，以便允许不具有桥接的局部互连，在平坦化地形上具有良好的连续性，并且与自对准方案兼容，因此节省了芯片的不动产。该技术与使用BPSG，BPTEOS，SOG或CMP的平面化方案兼容。在形成自对准绝缘晶体管栅极和有源晶体管区域之后，通过形成氧化物层和回流的上覆玻璃层来平坦化集成电路结构。将玻璃层回蚀刻以使表面平坦化。使用掩埋接触掩模，玻璃层和下面的氧化物层的剩余部分仅在掩埋接触区域中被去除。在一个版本中（在形成氧化物层和玻璃层之前），在掩埋接触位置处的衬底上形成多晶硅“着陆焊盘”，以便在掩埋触点的确切位置允许更有效的蚀刻。

5. 发明授权

US5172211A High resistance Polysilicon load resistor 失效
标题翻译：高电阻多晶硅负载电阻
公开(公告)号：US5172211A
公开(公告)日：1992-12-15
申请号：US464094
申请日：1990-01-12
申请人： Norman Godinho , Frank T. W. Lee , Hsiang-Wen Chen , Richard F. Motta , Juine-Kai Tsang , Joseph Tzou , Jai-man Balk , Ting-Pwu Yen
发明人： Norman Godinho , Frank T. W. Lee , Hsiang-Wen Chen , Richard F. Motta , Juine-Kai Tsang , Joseph Tzou , Jai-man Balk , Ting-Pwu Yen
IPC分类号： H01L27/04 , H01L21/82 , H01L21/822 , H01L21/8244 , H01L27/11
CPC分类号： H01L21/82 , H01L27/1112 , H01L2924/0002 , Y10S257/915
摘要： A load resistor for use in a semiconductor integrated circuit consists of two portions of conductive material, typically strips of either a silicide or a composite polycrystalline silicon layer and silicide layer formed thereon, formed on a semiconductor substrate and separated from each other by a selected distance. An electrically conductive dopant diffusion barrier is formed on the first and second portions of conductive material. A polycrystalline silicon material is then placed on the structure such that one portion of the polycrystalline silicon material is in ohmic contact through the diffusion barrier with the first portion of conductive material and the other portion of the polycrystalline silicon material is in ohmic contact through the diffusion barrier with the second portion of conductive material. Typically the polycrystalline silicon material is placed on an insulation layer formed on the semiconductor substrate in the portion of the substrate between the two portions of conductive material. The diffusion barrier prevents any dopant from the conductive material from diffusing into the polycrystalline silicon material thereby allowing the polycrystalline silicon material to function as a load resistor having a high resistance in the giga-ohms range. Subsequent high temperature processing of the structure does not change the resistance of the polycrystalline silicon because the dopant diffusion barrier prevents any dopant from the underlying conductive material from diffusing into the polycrystalline silicon material.

6. 发明授权

US5977638A Edge metal for interconnect layers 失效
标题翻译：用于互连层的边缘金属
公开(公告)号：US5977638A
公开(公告)日：1999-11-02
申请号：US754521
申请日：1996-11-21
申请人： T. J. Rodgers , Sam Geha , Chris Petti , Ting-Pwu Yen
发明人： T. J. Rodgers , Sam Geha , Chris Petti , Ting-Pwu Yen
IPC分类号： H01L21/3205 , H01L21/768 , H01L21/8244 , H01L23/528 , H01L27/11 , H01L23/48 , H01L21/44
CPC分类号： H01L27/11 , H01L21/32051 , H01L21/76838 , H01L21/76885 , H01L23/528 , H01L27/1104 , H01L2924/0002
摘要： A method of forming edge metal lines to interconnect features in a semiconductor device. One embodiment comprises the steps of: patterning a first insulating layer to form a first feature having a first sidewall; depositing a metal layer over the first feature; and etching the metal layer so that a first edge metal line is formed adjacent to the first sidewall. The edge metal line may be substantially anisotropically etched to form the edge metal line. The edge metal line may comprise a plurality of metal layers. The edge metal line may also interconnect features in a semiconductor device (e.g., contacts). The method may further comprise the step of forming a protective coating over a portion of the metal layer such that the etching step may form a metal interconnect line and the edge metal line from the same metal layer. The metal interconnect line may comprise a bus that may have more current carrying capacity than the edge metal line.
摘要翻译：一种形成边缘金属线以在半导体器件中互连特征的方法。一个实施例包括以下步骤：图案化第一绝缘层以形成具有第一侧壁的第一特征; 在第一特征上沉积金属层; 并且蚀刻所述金属层，使得与所述第一侧壁相邻地形成第一边缘金属线。边缘金属线可以被基本上各向异性地蚀刻以形成边缘金属线。边缘金属线可以包括多个金属层。边缘金属线还可以互连半导体器件（例如，触点）中的特征。该方法还可以包括在金属层的一部分上形成保护涂层的步骤，使得蚀刻步骤可以从同一金属层形成金属互连线和边缘金属线。金属互连线可以包括可以具有比边缘金属线更多的载流能力的总线。

7. 发明授权

US5656861A Self-aligning contact and interconnect structure 失效
标题翻译：自调心接触和互连结构
公开(公告)号：US5656861A
公开(公告)日：1997-08-12
申请号：US450847
申请日：1995-05-25
申请人： Norman Godinho , Tsu-Wei Frank Lee , Hsiang-Wen Chen , Richard F. Motta , Juine-Kai Tsang , Joseph Tzou , Jai-Man Baik , Ting-Pwu Yen
发明人： Norman Godinho , Tsu-Wei Frank Lee , Hsiang-Wen Chen , Richard F. Motta , Juine-Kai Tsang , Joseph Tzou , Jai-Man Baik , Ting-Pwu Yen
IPC分类号： H01L21/60 , H01L21/768 , H01L21/8238 , H01L21/8244 , H01L23/532 , H01L27/11 , H01L23/48
CPC分类号： H01L21/76897 , H01L21/76895 , H01L21/823864 , H01L21/823871 , H01L23/53257 , H01L23/53271 , H01L27/11 , H01L27/1112 , H01L27/1104 , H01L2924/0002 , H01L2924/3011 , Y10S257/90 , Y10S257/903 , Y10S257/904
摘要： An MOS transistor for use in an integrated circuit is fabricated with a self-aligning contact and interconnect structure which allows for higher packing density. Self-aligning source and drain contacts overlap the gate but are prevented from a short circuiting to the gate by oxide insulation between the source/drain contacts and the gate, and a layer of silicon nitride above the gate. Contacts to the gate are made on top of the gate over the active region of the transistor because the source and drain regions are protected by a hardened layer of photoresist during etching of insulation to expose the gate contact. Source, drain and gate contacts are protected by a layer of titanium silicide so that interconnects are not required to completely cover these areas. Low resistance interconnects are formed of doped polysilicon covered by titanium silicide encapsulated by a thin film of titanium nitride.
摘要翻译：用于集成电路的MOS晶体管是用自对准接触和互连结构制造的，其允许更高的封装密度。自对准源极和漏极触点与栅极重叠，但是通过源极/漏极接触和栅极之间的氧化物绝缘以及栅极上方的氮化硅层来防止与栅极的短路。在晶体管的有源区域上，在栅极的顶部形成与栅极的触点，因为源极和漏极区域在蚀刻绝缘体以暴露栅极接触期间被硬化的光致抗蚀剂层保护。源极，漏极和栅极触点被一层硅化钛保护，使得互连不需要完全覆盖这些区域。低电阻互连由氮化钛薄膜封装的由硅化钛覆盖的掺杂多晶硅形成。

8. 发明授权

US5483104A Self-aligning contact and interconnect structure 失效
标题翻译：自调心接触和互连结构
公开(公告)号：US5483104A
公开(公告)日：1996-01-09
申请号：US953410
申请日：1992-09-28
申请人： Norman Godinho , Tsu-Wei F. Lee , Hsiang-Wen Chen , Richard F. Motta , Juine-Kai Tsang , Joseph Tzou , Jai-Man Baik , Ting-Pwu Yen
发明人： Norman Godinho , Tsu-Wei F. Lee , Hsiang-Wen Chen , Richard F. Motta , Juine-Kai Tsang , Joseph Tzou , Jai-Man Baik , Ting-Pwu Yen
IPC分类号： H01L21/60 , H01L21/768 , H01L21/8238 , H01L21/8244 , H01L23/532 , H01L27/11 , H01L23/48 , H01L27/02
CPC分类号： H01L21/76897 , H01L21/76895 , H01L21/823864 , H01L21/823871 , H01L23/53257 , H01L23/53271 , H01L27/11 , H01L27/1112 , H01L27/1104 , H01L2924/0002 , H01L2924/3011 , Y10S257/90 , Y10S257/903 , Y10S257/904
摘要： An MOS transistor for use in an integrated circuit is fabricated with a self-aligning contact and interconnect structure which allows for higher packing density. Self-aligning source and drain contacts overlap the gate but are prevented from a short circuiting to the gate by oxide insulation between the source/drain contacts and the gate, and a layer of silicon nitride above the gate. Contacts to the gate are made on top of the gate over the active region of the transistor because the source and drain regions are protected by a hardened layer of photoresist during etching of insulation to expose the gate contact. Source, drain and gate contacts are protected by a layer of titanium silicide so that interconnects are not required to completely cover these areas. Low resistance interconnects are formed of doped polysilicon covered by titanium silicide encapsulated by a thin film of titanium nitride.
摘要翻译：用于集成电路的MOS晶体管是用自对准接触和互连结构制造的，其允许更高的封装密度。自对准源极和漏极触点与栅极重叠，但是通过源极/漏极接触和栅极之间的氧化物绝缘以及栅极上方的氮化硅层来防止与栅极的短路。在晶体管的有源区域上，在栅极的顶部形成与栅极的触点，因为源极和漏极区域在蚀刻绝缘体以暴露栅极接触期间被硬化的光致抗蚀剂层保护。源极，漏极和栅极触点被一层硅化钛保护，使得互连不需要完全覆盖这些区域。低电阻互连由氮化钛薄膜封装的由硅化钛覆盖的掺杂多晶硅形成。

9. 发明授权

US5620919A Methods for fabricating integrated circuits including openings to transistor regions 失效
标题翻译：制造包括晶体管区域开口的集成电路的方法
公开(公告)号：US5620919A
公开(公告)日：1997-04-15
申请号：US413976
申请日：1995-03-30
申请人： Norman Godinho , Frank T.W. Lee , Hsiang-Wen Chen , Richard F. Motta , Juine-Kai Tsang , Joseph Tzou , Jai-man Baik , Ting-Pwu Yen
发明人： Norman Godinho , Frank T.W. Lee , Hsiang-Wen Chen , Richard F. Motta , Juine-Kai Tsang , Joseph Tzou , Jai-man Baik , Ting-Pwu Yen
IPC分类号： H01L21/28 , H01L21/336 , H01L21/60 , H01L21/768 , H01L21/8238 , H01L21/8244 , H01L23/532 , H01L27/092 , H01L27/11 , H01L29/41 , H01L29/78
CPC分类号： H01L21/76897 , H01L21/76895 , H01L21/823864 , H01L21/823871 , H01L23/53257 , H01L23/53271 , H01L27/11 , H01L27/1104 , H01L2924/0002
摘要： An MOS transistor for use in an integrated circuit, particularly CMOS integrated circuits, is fabricated with a self-aligning contact and interconnect structure which allows for higher packing density. Self-aligning source and drain contacts overlap the gate but are prevented from short circuiting to the gate by oxide insulation between the source/drain contacts and the gate, and a layer of silicon nitride above the gate. Contacts to the gate are made on top of the gate over the active region of the transistor because the source and drain regions are protected by a hardened layer of photoresist during etching of insulation to expose the gate contact. Source, drain and gate contacts are protected by a layer of titanium silicide so that interconnects are not required to completely cover these areas. Low resistance interconnects are formed of titanium silicide encapulated by a thin film of titanium nitride.
摘要翻译：用于集成电路（特别是CMOS集成电路）的MOS晶体管被制造成具有允许更高的封装密度的自对准接触和互连结构。自对准源极和漏极触点与栅极重叠，但通过源极/漏极接触和栅极之间的氧化物绝缘以及栅极上方的氮化硅层来防止栅极与栅极短路。在晶体管的有源区域上，在栅极的顶部形成与栅极的触点，因为源极和漏极区域在蚀刻绝缘体以暴露栅极接触期间被硬化的光致抗蚀剂层保护。源极，漏极和栅极触点被一层硅化钛保护，使得互连不需要完全覆盖这些区域。低电阻互连由氮化钛薄膜包围的硅化钛形成。

10. 发明授权

US5348897A Transistor fabrication methods using overlapping masks 失效
标题翻译：使用重叠掩模的晶体管制造方法
公开(公告)号：US5348897A
公开(公告)日：1994-09-20
申请号：US984666
申请日：1992-12-01
申请人： Ting-Pwu Yen
发明人： Ting-Pwu Yen
IPC分类号： H01L21/8238 , H01L21/265 , H01L21/336 , H01L21/8244 , H01L27/092 , H01L27/11 , H01L29/78 , H01L29/786 , H01L21/266
CPC分类号： H01L29/66765 , H01L27/11 , H01L27/1108 , H01L29/78621 , H01L29/78624
摘要： Transistor fabrication methods are provided which are suitable, for example, for transistors with current carrying elements above a semiconductor substrate. Only few mask alignments define critical dimensions such as the channel length of a MOS transistor. In one embodiment in which the channel region overlies the gate, a first mask is formed over the channel region, and then an LDD implant is carried out. A second mask is then formed over the LDD portion of the drain region. The second mask is allowed to extend over the first mask. A heavy doping implant is then carried out. Thus an LDD structure can be provided on the drain side but not on the source side with only one mask--the first mask--defining the channel length. In some embodiments, both masks include photoresist. The first photoresist mask is hardened to prevent its lifting during development of the resist of the second mask. Further, after the LDD implant, the first photoresist mask is outgassed to improve the adhesion of the second photoresist mask. In another embodiment, the second mask is used to pattern the first mask. The patterning etch undercuts the second mask. After the heavy doping implant, the second mask is removed, and the LDD implant is performed with the first mask masking the channel region.
摘要翻译：提供了晶体管制造方法，其适用于例如具有在半导体衬底之上的电流承载元件的晶体管。只有少数掩模对准来定义关键尺寸，例如MOS晶体管的沟道长度。在沟道区域覆盖栅极的一个实施例中，在沟道区域上形成第一掩模，然后执行LDD注入。然后在漏极区域的LDD部分上形成第二掩模。允许第二个掩模在第一个掩模上延伸。然后进行重掺杂植入物。因此，LDD结构可以在漏极侧而不是在源极上提供，只有一个掩模 - 第一掩模 - 限定沟道长度。在一些实施例中，两个掩模包括光致抗蚀剂。第一光致抗蚀剂掩模被硬化以防止在显影第二掩模的抗蚀剂期间其提升。此外，在LDD植入之后，第一光致抗蚀剂掩模脱气以改善第二光致抗蚀剂掩模的附着力。在另一实施例中，第二掩模用于对第一掩模进行图案化。图案化蚀刻底切第二掩模。在重掺杂注入之后，去除第二掩模，并且利用第一掩模掩蔽沟道区域来执行LDD注入。

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