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1. 发明授权

US5172211A High resistance Polysilicon load resistor 失效
标题翻译：高电阻多晶硅负载电阻
公开(公告)号：US5172211A
公开(公告)日：1992-12-15
申请号：US464094
申请日：1990-01-12
申请人： Norman Godinho , Frank T. W. Lee , Hsiang-Wen Chen , Richard F. Motta , Juine-Kai Tsang , Joseph Tzou , Jai-man Balk , Ting-Pwu Yen
发明人： Norman Godinho , Frank T. W. Lee , Hsiang-Wen Chen , Richard F. Motta , Juine-Kai Tsang , Joseph Tzou , Jai-man Balk , Ting-Pwu Yen
IPC分类号： H01L27/04 , H01L21/82 , H01L21/822 , H01L21/8244 , H01L27/11
CPC分类号： H01L21/82 , H01L27/1112 , H01L2924/0002 , Y10S257/915
摘要： A load resistor for use in a semiconductor integrated circuit consists of two portions of conductive material, typically strips of either a silicide or a composite polycrystalline silicon layer and silicide layer formed thereon, formed on a semiconductor substrate and separated from each other by a selected distance. An electrically conductive dopant diffusion barrier is formed on the first and second portions of conductive material. A polycrystalline silicon material is then placed on the structure such that one portion of the polycrystalline silicon material is in ohmic contact through the diffusion barrier with the first portion of conductive material and the other portion of the polycrystalline silicon material is in ohmic contact through the diffusion barrier with the second portion of conductive material. Typically the polycrystalline silicon material is placed on an insulation layer formed on the semiconductor substrate in the portion of the substrate between the two portions of conductive material. The diffusion barrier prevents any dopant from the conductive material from diffusing into the polycrystalline silicon material thereby allowing the polycrystalline silicon material to function as a load resistor having a high resistance in the giga-ohms range. Subsequent high temperature processing of the structure does not change the resistance of the polycrystalline silicon because the dopant diffusion barrier prevents any dopant from the underlying conductive material from diffusing into the polycrystalline silicon material.

2. 发明授权

US5620919A Methods for fabricating integrated circuits including openings to transistor regions 失效
标题翻译：制造包括晶体管区域开口的集成电路的方法
公开(公告)号：US5620919A
公开(公告)日：1997-04-15
申请号：US413976
申请日：1995-03-30
申请人： Norman Godinho , Frank T.W. Lee , Hsiang-Wen Chen , Richard F. Motta , Juine-Kai Tsang , Joseph Tzou , Jai-man Baik , Ting-Pwu Yen
发明人： Norman Godinho , Frank T.W. Lee , Hsiang-Wen Chen , Richard F. Motta , Juine-Kai Tsang , Joseph Tzou , Jai-man Baik , Ting-Pwu Yen
IPC分类号： H01L21/28 , H01L21/336 , H01L21/60 , H01L21/768 , H01L21/8238 , H01L21/8244 , H01L23/532 , H01L27/092 , H01L27/11 , H01L29/41 , H01L29/78
CPC分类号： H01L21/76897 , H01L21/76895 , H01L21/823864 , H01L21/823871 , H01L23/53257 , H01L23/53271 , H01L27/11 , H01L27/1104 , H01L2924/0002
摘要： An MOS transistor for use in an integrated circuit, particularly CMOS integrated circuits, is fabricated with a self-aligning contact and interconnect structure which allows for higher packing density. Self-aligning source and drain contacts overlap the gate but are prevented from short circuiting to the gate by oxide insulation between the source/drain contacts and the gate, and a layer of silicon nitride above the gate. Contacts to the gate are made on top of the gate over the active region of the transistor because the source and drain regions are protected by a hardened layer of photoresist during etching of insulation to expose the gate contact. Source, drain and gate contacts are protected by a layer of titanium silicide so that interconnects are not required to completely cover these areas. Low resistance interconnects are formed of titanium silicide encapulated by a thin film of titanium nitride.
摘要翻译：用于集成电路（特别是CMOS集成电路）的MOS晶体管被制造成具有允许更高的封装密度的自对准接触和互连结构。自对准源极和漏极触点与栅极重叠，但通过源极/漏极接触和栅极之间的氧化物绝缘以及栅极上方的氮化硅层来防止栅极与栅极短路。在晶体管的有源区域上，在栅极的顶部形成与栅极的触点，因为源极和漏极区域在蚀刻绝缘体以暴露栅极接触期间被硬化的光致抗蚀剂层保护。源极，漏极和栅极触点被一层硅化钛保护，使得互连不需要完全覆盖这些区域。低电阻互连由氮化钛薄膜包围的硅化钛形成。

3. 发明授权

US5656861A Self-aligning contact and interconnect structure 失效
标题翻译：自调心接触和互连结构
公开(公告)号：US5656861A
公开(公告)日：1997-08-12
申请号：US450847
申请日：1995-05-25
申请人： Norman Godinho , Tsu-Wei Frank Lee , Hsiang-Wen Chen , Richard F. Motta , Juine-Kai Tsang , Joseph Tzou , Jai-Man Baik , Ting-Pwu Yen
发明人： Norman Godinho , Tsu-Wei Frank Lee , Hsiang-Wen Chen , Richard F. Motta , Juine-Kai Tsang , Joseph Tzou , Jai-Man Baik , Ting-Pwu Yen
IPC分类号： H01L21/60 , H01L21/768 , H01L21/8238 , H01L21/8244 , H01L23/532 , H01L27/11 , H01L23/48
CPC分类号： H01L21/76897 , H01L21/76895 , H01L21/823864 , H01L21/823871 , H01L23/53257 , H01L23/53271 , H01L27/11 , H01L27/1112 , H01L27/1104 , H01L2924/0002 , H01L2924/3011 , Y10S257/90 , Y10S257/903 , Y10S257/904
摘要： An MOS transistor for use in an integrated circuit is fabricated with a self-aligning contact and interconnect structure which allows for higher packing density. Self-aligning source and drain contacts overlap the gate but are prevented from a short circuiting to the gate by oxide insulation between the source/drain contacts and the gate, and a layer of silicon nitride above the gate. Contacts to the gate are made on top of the gate over the active region of the transistor because the source and drain regions are protected by a hardened layer of photoresist during etching of insulation to expose the gate contact. Source, drain and gate contacts are protected by a layer of titanium silicide so that interconnects are not required to completely cover these areas. Low resistance interconnects are formed of doped polysilicon covered by titanium silicide encapsulated by a thin film of titanium nitride.
摘要翻译：用于集成电路的MOS晶体管是用自对准接触和互连结构制造的，其允许更高的封装密度。自对准源极和漏极触点与栅极重叠，但是通过源极/漏极接触和栅极之间的氧化物绝缘以及栅极上方的氮化硅层来防止与栅极的短路。在晶体管的有源区域上，在栅极的顶部形成与栅极的触点，因为源极和漏极区域在蚀刻绝缘体以暴露栅极接触期间被硬化的光致抗蚀剂层保护。源极，漏极和栅极触点被一层硅化钛保护，使得互连不需要完全覆盖这些区域。低电阻互连由氮化钛薄膜封装的由硅化钛覆盖的掺杂多晶硅形成。

4. 发明授权

US5483104A Self-aligning contact and interconnect structure 失效
标题翻译：自调心接触和互连结构
公开(公告)号：US5483104A
公开(公告)日：1996-01-09
申请号：US953410
申请日：1992-09-28
申请人： Norman Godinho , Tsu-Wei F. Lee , Hsiang-Wen Chen , Richard F. Motta , Juine-Kai Tsang , Joseph Tzou , Jai-Man Baik , Ting-Pwu Yen
发明人： Norman Godinho , Tsu-Wei F. Lee , Hsiang-Wen Chen , Richard F. Motta , Juine-Kai Tsang , Joseph Tzou , Jai-Man Baik , Ting-Pwu Yen
IPC分类号： H01L21/60 , H01L21/768 , H01L21/8238 , H01L21/8244 , H01L23/532 , H01L27/11 , H01L23/48 , H01L27/02
CPC分类号： H01L21/76897 , H01L21/76895 , H01L21/823864 , H01L21/823871 , H01L23/53257 , H01L23/53271 , H01L27/11 , H01L27/1112 , H01L27/1104 , H01L2924/0002 , H01L2924/3011 , Y10S257/90 , Y10S257/903 , Y10S257/904
摘要： An MOS transistor for use in an integrated circuit is fabricated with a self-aligning contact and interconnect structure which allows for higher packing density. Self-aligning source and drain contacts overlap the gate but are prevented from a short circuiting to the gate by oxide insulation between the source/drain contacts and the gate, and a layer of silicon nitride above the gate. Contacts to the gate are made on top of the gate over the active region of the transistor because the source and drain regions are protected by a hardened layer of photoresist during etching of insulation to expose the gate contact. Source, drain and gate contacts are protected by a layer of titanium silicide so that interconnects are not required to completely cover these areas. Low resistance interconnects are formed of doped polysilicon covered by titanium silicide encapsulated by a thin film of titanium nitride.
摘要翻译：用于集成电路的MOS晶体管是用自对准接触和互连结构制造的，其允许更高的封装密度。自对准源极和漏极触点与栅极重叠，但是通过源极/漏极接触和栅极之间的氧化物绝缘以及栅极上方的氮化硅层来防止与栅极的短路。在晶体管的有源区域上，在栅极的顶部形成与栅极的触点，因为源极和漏极区域在蚀刻绝缘体以暴露栅极接触期间被硬化的光致抗蚀剂层保护。源极，漏极和栅极触点被一层硅化钛保护，使得互连不需要完全覆盖这些区域。低电阻互连由氮化钛薄膜封装的由硅化钛覆盖的掺杂多晶硅形成。

5. 发明授权

US5168076A Method of fabricating a high resistance polysilicon load resistor 失效
标题翻译：制造高阻多晶硅负载电阻的方法
公开(公告)号：US5168076A
公开(公告)日：1992-12-01
申请号：US724008
申请日：1991-07-01
申请人： Norman Godinho , Frank T. Lee , Hsiang-Wen Chen , Richard F. Motta , Juine-Kai Tsang , Joseph Tzou , Jai-man Baik , Ting-Pwu Yen
发明人： Norman Godinho , Frank T. Lee , Hsiang-Wen Chen , Richard F. Motta , Juine-Kai Tsang , Joseph Tzou , Jai-man Baik , Ting-Pwu Yen
IPC分类号： H01L21/82 , H01L27/11
CPC分类号： H01L27/1112 , H01L21/82 , Y10S148/136
摘要： A load resistor for use in a semiconductor integrated circuit consists of two portions of conductive material, typically strips of either a silicide or a composite polycrystalline silicon layer and silicide layer formed thereon, formed on a semiconductor substrate and separated from each other by a selected distance. An electrically conductive dopant diffusion barrier is formed on the first and second portions of conductive material. A polycrystalline silicon material is then placed on the structure such that one portion of the polycrystalline silicon material is in ohmic contact through the diffusion barrier with the first portion of conductive material and the other portion of the polycrystalline silicon material is in ohmic contact through the diffusion barrier with the second portion of conductive material. Typically the polycrystalline silicon material is placed on an insulation layer formed on the semiconductor substrate in the portion of the substrate between the two portions of conductive material. The diffusion barrier prevents any dopant from the conductive material from diffusing into the polycrystalline silicon material thereby allowing the polycrystalline silicon material to function as a load resistor having a high resistance in the giga-ohms range. Subsequent high temperature processing of the structure does not change the resistance of the polycrystalline silicon because the dopant diffusion barrier prevents any dopant from the underlying conductive material from diffusing into the polycrystalline silicon material.
摘要翻译：用于半导体集成电路的负载电阻器由导电材料的两部分组成，通常形成在半导体衬底上的硅化物或复合多晶硅层以及形成在其上的硅化物层的条带，并且彼此间隔一定距离。在导电材料的第一和第二部分上形成导电掺杂剂扩散阻挡层。然后将多晶硅材料放置在结构上，使得多晶硅材料的一部分与导电材料的第一部分通过扩散阻挡层欧姆接触，并且多晶硅材料的另一部分通过扩散而欧姆接触与导电材料的第二部分隔离。通常，多晶硅材料放置在形成在半导体衬底上的导电材料的两部分之间的衬底部分中的绝缘层上。扩散阻挡层阻止来自导电材料的任何掺杂剂扩散到多晶硅材料中，从而允许多晶硅材料用作在千兆欧范围内具有高电阻的负载电阻器。结构的随后的高温处理不会改变多晶硅的电阻，因为掺杂剂扩散势垒阻止来自下面的导电材料的任何掺杂剂扩散到多晶硅材料中。

6. 发明授权

US5166771A Self-aligning contact and interconnect structure 失效
标题翻译：自对准接触和互连结构
公开(公告)号：US5166771A
公开(公告)日：1992-11-24
申请号：US464496
申请日：1990-01-12
申请人： Norman Godinho , Frank T. Lee , Hsiang-Wen Chen , Richard F. Motta , Juine-Kai Tsang , Joseph Tzou , Jai-man Baik , Ting-Pwu Yen
发明人： Norman Godinho , Frank T. Lee , Hsiang-Wen Chen , Richard F. Motta , Juine-Kai Tsang , Joseph Tzou , Jai-man Baik , Ting-Pwu Yen
IPC分类号： H01L21/28 , H01L21/336 , H01L21/60 , H01L21/768 , H01L21/8238 , H01L21/8244 , H01L23/532 , H01L27/092 , H01L27/11 , H01L29/41 , H01L29/78
CPC分类号： H01L21/76897 , H01L21/76895 , H01L21/823864 , H01L21/823871 , H01L23/53257 , H01L23/53271 , H01L27/11 , H01L27/1104 , H01L2924/0002
摘要： An MOS transistor for use in an integrated circuit, particularly CMOS integrated circuits, is fabricated with a self-aligning contact and interconnect structure which allows for higher packing density. Self-aligning source and drain contacts overlap the gate but are prevented from short circuiting to the gate by oxide insulation between source/drain contacts and the gate, and a layer of silicon nitride above the gate. Contacts to the gate are made on top of the gate over the active region of the transistor because the source and drain regions are protected by a hardened layer of photoresist during etching of insulation to expose the gate contact. Source, drain and gate contacts are protected by a layer of titanium silicide so that interconnects are not required to completely cover these areas. Low resistance interconnects are formed of titanium silicide encapsulated by a thin film of titanium nitride.

7. 发明授权

US5124774A Compact SRAM cell layout 失效
标题翻译：紧凑的SRAM单元布局
公开(公告)号：US5124774A
公开(公告)日：1992-06-23
申请号：US555559
申请日：1990-07-19
申请人： Norman Godinho , Tsu-Wei F. Lee , Hsiang-Wen Chen , Richard F. Motta , Juine-Kai Tsang , Joseph Tzou , Jai-Man Baik , Ting-Pwu Yen
发明人： Norman Godinho , Tsu-Wei F. Lee , Hsiang-Wen Chen , Richard F. Motta , Juine-Kai Tsang , Joseph Tzou , Jai-Man Baik , Ting-Pwu Yen
IPC分类号： H01L21/60 , H01L21/768 , H01L21/8238 , H01L21/8244 , H01L23/532 , H01L27/11
CPC分类号： H01L27/11 , H01L21/768 , H01L21/76895 , H01L21/76897 , H01L21/823864 , H01L21/823871 , H01L23/53257 , H01L23/53271 , H01L27/1112 , H01L27/1104 , H01L2924/0002 , Y10S257/904
摘要： A compact cell design for a static random access memory cell is achieved. The cell has two transistors with gates substantially parallel to each other. One interconnect connects the gate of one transistor to an electrode of the other transistor. Another interconnect connects the gate of the other transistor to an electrode of the first transistor. The two gates and the two interconnects form substantially a rectangle. A power supply circiut line is disposed outside the rectangle. This line and the two interconnects are formed from one conductive layer.
摘要翻译：实现了用于静态随机存取存储单元的紧凑型单元设计。电池具有两个栅极，栅极基本上彼此平行。一个互连将一个晶体管的栅极连接到另一个晶体管的电极。另一个互连将另一晶体管的栅极连接到第一晶体管的电极。两个门和两个互连构成大致矩形。电源线环绕在矩形外面。该线和两个互连由一个导电层形成。

8. 发明授权

US5365104A Oxynitride fuse protective/passivation film for integrated circuit having resistors 失效
标题翻译：用于具有电阻器的集成电路的氧氮化物熔丝保护/钝化膜
公开(公告)号：US5365104A
公开(公告)日：1994-11-15
申请号：US36754
申请日：1993-03-25
申请人： Norman Godinho , Hai-Pyng Liaw
发明人： Norman Godinho , Hai-Pyng Liaw
IPC分类号： H01L21/314 , H01L21/316 , H01L21/318 , H01L21/82 , H01L21/822 , H01L23/525 , H01L27/04 , H01L27/10 , H01L27/11 , H01L27/02
CPC分类号： H01L23/5256 , H01L27/1112 , H01L2924/0002
摘要： An oxynitride passivation layer and/or fuse protective layer for an SRAM cell having load resistors, where the composition of the oxynitride layer minimizes the effect of hydrogen diffusion on the resistance of underlying load resistors. The index of refraction of the oxynitride is between 1.60 and 1.85. This oxynitride does not substantially diffuse hydrogen into the load resistors even when heated to temperatures over 400.degree. C., and hence, avoids altering resistance during subsequent annealing steps.
摘要翻译：用于具有负载电阻器的SRAM单元的氮氧化物钝化层和/或熔丝保护层，其中氮氧化物层的组成使氢扩散对下伏负载电阻器的电阻的影响最小化。氮氧化物的折射率在1.60和1.85之间。即使在加热到400℃以上的温度下，这种氧氮化物也不会将氢充分扩散到负载电阻中，因此避免了在随后的退火步骤期间改变电阻。

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