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1. 发明授权

US5172211A High resistance Polysilicon load resistor 失效
标题翻译：高电阻多晶硅负载电阻
公开(公告)号：US5172211A
公开(公告)日：1992-12-15
申请号：US464094
申请日：1990-01-12
申请人： Norman Godinho , Frank T. W. Lee , Hsiang-Wen Chen , Richard F. Motta , Juine-Kai Tsang , Joseph Tzou , Jai-man Balk , Ting-Pwu Yen
发明人： Norman Godinho , Frank T. W. Lee , Hsiang-Wen Chen , Richard F. Motta , Juine-Kai Tsang , Joseph Tzou , Jai-man Balk , Ting-Pwu Yen
IPC分类号： H01L27/04 , H01L21/82 , H01L21/822 , H01L21/8244 , H01L27/11
CPC分类号： H01L21/82 , H01L27/1112 , H01L2924/0002 , Y10S257/915
摘要： A load resistor for use in a semiconductor integrated circuit consists of two portions of conductive material, typically strips of either a silicide or a composite polycrystalline silicon layer and silicide layer formed thereon, formed on a semiconductor substrate and separated from each other by a selected distance. An electrically conductive dopant diffusion barrier is formed on the first and second portions of conductive material. A polycrystalline silicon material is then placed on the structure such that one portion of the polycrystalline silicon material is in ohmic contact through the diffusion barrier with the first portion of conductive material and the other portion of the polycrystalline silicon material is in ohmic contact through the diffusion barrier with the second portion of conductive material. Typically the polycrystalline silicon material is placed on an insulation layer formed on the semiconductor substrate in the portion of the substrate between the two portions of conductive material. The diffusion barrier prevents any dopant from the conductive material from diffusing into the polycrystalline silicon material thereby allowing the polycrystalline silicon material to function as a load resistor having a high resistance in the giga-ohms range. Subsequent high temperature processing of the structure does not change the resistance of the polycrystalline silicon because the dopant diffusion barrier prevents any dopant from the underlying conductive material from diffusing into the polycrystalline silicon material.

2. 发明授权

US5656861A Self-aligning contact and interconnect structure 失效
标题翻译：自调心接触和互连结构
公开(公告)号：US5656861A
公开(公告)日：1997-08-12
申请号：US450847
申请日：1995-05-25
申请人： Norman Godinho , Tsu-Wei Frank Lee , Hsiang-Wen Chen , Richard F. Motta , Juine-Kai Tsang , Joseph Tzou , Jai-Man Baik , Ting-Pwu Yen
发明人： Norman Godinho , Tsu-Wei Frank Lee , Hsiang-Wen Chen , Richard F. Motta , Juine-Kai Tsang , Joseph Tzou , Jai-Man Baik , Ting-Pwu Yen
IPC分类号： H01L21/60 , H01L21/768 , H01L21/8238 , H01L21/8244 , H01L23/532 , H01L27/11 , H01L23/48
CPC分类号： H01L21/76897 , H01L21/76895 , H01L21/823864 , H01L21/823871 , H01L23/53257 , H01L23/53271 , H01L27/11 , H01L27/1112 , H01L27/1104 , H01L2924/0002 , H01L2924/3011 , Y10S257/90 , Y10S257/903 , Y10S257/904
摘要： An MOS transistor for use in an integrated circuit is fabricated with a self-aligning contact and interconnect structure which allows for higher packing density. Self-aligning source and drain contacts overlap the gate but are prevented from a short circuiting to the gate by oxide insulation between the source/drain contacts and the gate, and a layer of silicon nitride above the gate. Contacts to the gate are made on top of the gate over the active region of the transistor because the source and drain regions are protected by a hardened layer of photoresist during etching of insulation to expose the gate contact. Source, drain and gate contacts are protected by a layer of titanium silicide so that interconnects are not required to completely cover these areas. Low resistance interconnects are formed of doped polysilicon covered by titanium silicide encapsulated by a thin film of titanium nitride.
摘要翻译：用于集成电路的MOS晶体管是用自对准接触和互连结构制造的，其允许更高的封装密度。自对准源极和漏极触点与栅极重叠，但是通过源极/漏极接触和栅极之间的氧化物绝缘以及栅极上方的氮化硅层来防止与栅极的短路。在晶体管的有源区域上，在栅极的顶部形成与栅极的触点，因为源极和漏极区域在蚀刻绝缘体以暴露栅极接触期间被硬化的光致抗蚀剂层保护。源极，漏极和栅极触点被一层硅化钛保护，使得互连不需要完全覆盖这些区域。低电阻互连由氮化钛薄膜封装的由硅化钛覆盖的掺杂多晶硅形成。

3. 发明授权

US5483104A Self-aligning contact and interconnect structure 失效
标题翻译：自调心接触和互连结构
公开(公告)号：US5483104A
公开(公告)日：1996-01-09
申请号：US953410
申请日：1992-09-28
申请人： Norman Godinho , Tsu-Wei F. Lee , Hsiang-Wen Chen , Richard F. Motta , Juine-Kai Tsang , Joseph Tzou , Jai-Man Baik , Ting-Pwu Yen
发明人： Norman Godinho , Tsu-Wei F. Lee , Hsiang-Wen Chen , Richard F. Motta , Juine-Kai Tsang , Joseph Tzou , Jai-Man Baik , Ting-Pwu Yen
IPC分类号： H01L21/60 , H01L21/768 , H01L21/8238 , H01L21/8244 , H01L23/532 , H01L27/11 , H01L23/48 , H01L27/02
CPC分类号： H01L21/76897 , H01L21/76895 , H01L21/823864 , H01L21/823871 , H01L23/53257 , H01L23/53271 , H01L27/11 , H01L27/1112 , H01L27/1104 , H01L2924/0002 , H01L2924/3011 , Y10S257/90 , Y10S257/903 , Y10S257/904
摘要： An MOS transistor for use in an integrated circuit is fabricated with a self-aligning contact and interconnect structure which allows for higher packing density. Self-aligning source and drain contacts overlap the gate but are prevented from a short circuiting to the gate by oxide insulation between the source/drain contacts and the gate, and a layer of silicon nitride above the gate. Contacts to the gate are made on top of the gate over the active region of the transistor because the source and drain regions are protected by a hardened layer of photoresist during etching of insulation to expose the gate contact. Source, drain and gate contacts are protected by a layer of titanium silicide so that interconnects are not required to completely cover these areas. Low resistance interconnects are formed of doped polysilicon covered by titanium silicide encapsulated by a thin film of titanium nitride.
摘要翻译：用于集成电路的MOS晶体管是用自对准接触和互连结构制造的，其允许更高的封装密度。自对准源极和漏极触点与栅极重叠，但是通过源极/漏极接触和栅极之间的氧化物绝缘以及栅极上方的氮化硅层来防止与栅极的短路。在晶体管的有源区域上，在栅极的顶部形成与栅极的触点，因为源极和漏极区域在蚀刻绝缘体以暴露栅极接触期间被硬化的光致抗蚀剂层保护。源极，漏极和栅极触点被一层硅化钛保护，使得互连不需要完全覆盖这些区域。低电阻互连由氮化钛薄膜封装的由硅化钛覆盖的掺杂多晶硅形成。

4. 发明授权

US5620919A Methods for fabricating integrated circuits including openings to transistor regions 失效
标题翻译：制造包括晶体管区域开口的集成电路的方法
公开(公告)号：US5620919A
公开(公告)日：1997-04-15
申请号：US413976
申请日：1995-03-30
申请人： Norman Godinho , Frank T.W. Lee , Hsiang-Wen Chen , Richard F. Motta , Juine-Kai Tsang , Joseph Tzou , Jai-man Baik , Ting-Pwu Yen
发明人： Norman Godinho , Frank T.W. Lee , Hsiang-Wen Chen , Richard F. Motta , Juine-Kai Tsang , Joseph Tzou , Jai-man Baik , Ting-Pwu Yen
IPC分类号： H01L21/28 , H01L21/336 , H01L21/60 , H01L21/768 , H01L21/8238 , H01L21/8244 , H01L23/532 , H01L27/092 , H01L27/11 , H01L29/41 , H01L29/78
CPC分类号： H01L21/76897 , H01L21/76895 , H01L21/823864 , H01L21/823871 , H01L23/53257 , H01L23/53271 , H01L27/11 , H01L27/1104 , H01L2924/0002
摘要： An MOS transistor for use in an integrated circuit, particularly CMOS integrated circuits, is fabricated with a self-aligning contact and interconnect structure which allows for higher packing density. Self-aligning source and drain contacts overlap the gate but are prevented from short circuiting to the gate by oxide insulation between the source/drain contacts and the gate, and a layer of silicon nitride above the gate. Contacts to the gate are made on top of the gate over the active region of the transistor because the source and drain regions are protected by a hardened layer of photoresist during etching of insulation to expose the gate contact. Source, drain and gate contacts are protected by a layer of titanium silicide so that interconnects are not required to completely cover these areas. Low resistance interconnects are formed of titanium silicide encapulated by a thin film of titanium nitride.
摘要翻译：用于集成电路（特别是CMOS集成电路）的MOS晶体管被制造成具有允许更高的封装密度的自对准接触和互连结构。自对准源极和漏极触点与栅极重叠，但通过源极/漏极接触和栅极之间的氧化物绝缘以及栅极上方的氮化硅层来防止栅极与栅极短路。在晶体管的有源区域上，在栅极的顶部形成与栅极的触点，因为源极和漏极区域在蚀刻绝缘体以暴露栅极接触期间被硬化的光致抗蚀剂层保护。源极，漏极和栅极触点被一层硅化钛保护，使得互连不需要完全覆盖这些区域。低电阻互连由氮化钛薄膜包围的硅化钛形成。

5. 发明授权

US5168076A Method of fabricating a high resistance polysilicon load resistor 失效
标题翻译：制造高阻多晶硅负载电阻的方法
公开(公告)号：US5168076A
公开(公告)日：1992-12-01
申请号：US724008
申请日：1991-07-01
申请人： Norman Godinho , Frank T. Lee , Hsiang-Wen Chen , Richard F. Motta , Juine-Kai Tsang , Joseph Tzou , Jai-man Baik , Ting-Pwu Yen
发明人： Norman Godinho , Frank T. Lee , Hsiang-Wen Chen , Richard F. Motta , Juine-Kai Tsang , Joseph Tzou , Jai-man Baik , Ting-Pwu Yen
IPC分类号： H01L21/82 , H01L27/11
CPC分类号： H01L27/1112 , H01L21/82 , Y10S148/136
摘要： A load resistor for use in a semiconductor integrated circuit consists of two portions of conductive material, typically strips of either a silicide or a composite polycrystalline silicon layer and silicide layer formed thereon, formed on a semiconductor substrate and separated from each other by a selected distance. An electrically conductive dopant diffusion barrier is formed on the first and second portions of conductive material. A polycrystalline silicon material is then placed on the structure such that one portion of the polycrystalline silicon material is in ohmic contact through the diffusion barrier with the first portion of conductive material and the other portion of the polycrystalline silicon material is in ohmic contact through the diffusion barrier with the second portion of conductive material. Typically the polycrystalline silicon material is placed on an insulation layer formed on the semiconductor substrate in the portion of the substrate between the two portions of conductive material. The diffusion barrier prevents any dopant from the conductive material from diffusing into the polycrystalline silicon material thereby allowing the polycrystalline silicon material to function as a load resistor having a high resistance in the giga-ohms range. Subsequent high temperature processing of the structure does not change the resistance of the polycrystalline silicon because the dopant diffusion barrier prevents any dopant from the underlying conductive material from diffusing into the polycrystalline silicon material.
摘要翻译：用于半导体集成电路的负载电阻器由导电材料的两部分组成，通常形成在半导体衬底上的硅化物或复合多晶硅层以及形成在其上的硅化物层的条带，并且彼此间隔一定距离。在导电材料的第一和第二部分上形成导电掺杂剂扩散阻挡层。然后将多晶硅材料放置在结构上，使得多晶硅材料的一部分与导电材料的第一部分通过扩散阻挡层欧姆接触，并且多晶硅材料的另一部分通过扩散而欧姆接触与导电材料的第二部分隔离。通常，多晶硅材料放置在形成在半导体衬底上的导电材料的两部分之间的衬底部分中的绝缘层上。扩散阻挡层阻止来自导电材料的任何掺杂剂扩散到多晶硅材料中，从而允许多晶硅材料用作在千兆欧范围内具有高电阻的负载电阻器。结构的随后的高温处理不会改变多晶硅的电阻，因为掺杂剂扩散势垒阻止来自下面的导电材料的任何掺杂剂扩散到多晶硅材料中。

6. 发明授权

US5166771A Self-aligning contact and interconnect structure 失效
标题翻译：自对准接触和互连结构
公开(公告)号：US5166771A
公开(公告)日：1992-11-24
申请号：US464496
申请日：1990-01-12
申请人： Norman Godinho , Frank T. Lee , Hsiang-Wen Chen , Richard F. Motta , Juine-Kai Tsang , Joseph Tzou , Jai-man Baik , Ting-Pwu Yen
发明人： Norman Godinho , Frank T. Lee , Hsiang-Wen Chen , Richard F. Motta , Juine-Kai Tsang , Joseph Tzou , Jai-man Baik , Ting-Pwu Yen
IPC分类号： H01L21/28 , H01L21/336 , H01L21/60 , H01L21/768 , H01L21/8238 , H01L21/8244 , H01L23/532 , H01L27/092 , H01L27/11 , H01L29/41 , H01L29/78
CPC分类号： H01L21/76897 , H01L21/76895 , H01L21/823864 , H01L21/823871 , H01L23/53257 , H01L23/53271 , H01L27/11 , H01L27/1104 , H01L2924/0002
摘要： An MOS transistor for use in an integrated circuit, particularly CMOS integrated circuits, is fabricated with a self-aligning contact and interconnect structure which allows for higher packing density. Self-aligning source and drain contacts overlap the gate but are prevented from short circuiting to the gate by oxide insulation between source/drain contacts and the gate, and a layer of silicon nitride above the gate. Contacts to the gate are made on top of the gate over the active region of the transistor because the source and drain regions are protected by a hardened layer of photoresist during etching of insulation to expose the gate contact. Source, drain and gate contacts are protected by a layer of titanium silicide so that interconnects are not required to completely cover these areas. Low resistance interconnects are formed of titanium silicide encapsulated by a thin film of titanium nitride.

7. 发明授权

US5124774A Compact SRAM cell layout 失效
标题翻译：紧凑的SRAM单元布局
公开(公告)号：US5124774A
公开(公告)日：1992-06-23
申请号：US555559
申请日：1990-07-19
申请人： Norman Godinho , Tsu-Wei F. Lee , Hsiang-Wen Chen , Richard F. Motta , Juine-Kai Tsang , Joseph Tzou , Jai-Man Baik , Ting-Pwu Yen
发明人： Norman Godinho , Tsu-Wei F. Lee , Hsiang-Wen Chen , Richard F. Motta , Juine-Kai Tsang , Joseph Tzou , Jai-Man Baik , Ting-Pwu Yen
IPC分类号： H01L21/60 , H01L21/768 , H01L21/8238 , H01L21/8244 , H01L23/532 , H01L27/11
CPC分类号： H01L27/11 , H01L21/768 , H01L21/76895 , H01L21/76897 , H01L21/823864 , H01L21/823871 , H01L23/53257 , H01L23/53271 , H01L27/1112 , H01L27/1104 , H01L2924/0002 , Y10S257/904
摘要： A compact cell design for a static random access memory cell is achieved. The cell has two transistors with gates substantially parallel to each other. One interconnect connects the gate of one transistor to an electrode of the other transistor. Another interconnect connects the gate of the other transistor to an electrode of the first transistor. The two gates and the two interconnects form substantially a rectangle. A power supply circiut line is disposed outside the rectangle. This line and the two interconnects are formed from one conductive layer.
摘要翻译：实现了用于静态随机存取存储单元的紧凑型单元设计。电池具有两个栅极，栅极基本上彼此平行。一个互连将一个晶体管的栅极连接到另一个晶体管的电极。另一个互连将另一晶体管的栅极连接到第一晶体管的电极。两个门和两个互连构成大致矩形。电源线环绕在矩形外面。该线和两个互连由一个导电层形成。

8. 发明授权

US4796081A Low resistance metal contact for silicon devices 失效
标题翻译：硅器件的低电阻金属接触
公开(公告)号：US4796081A
公开(公告)日：1989-01-03
申请号：US858994
申请日：1986-05-02
申请人： Robin W. Cheung , Bernard W. K. Ho , Hsiang-Wen Chen , Hugo W. K. Chan
发明人： Robin W. Cheung , Bernard W. K. Ho , Hsiang-Wen Chen , Hugo W. K. Chan
IPC分类号： H01L21/768 , H01L21/28 , H01L21/3205 , H01L23/52 , H01L23/522 , H01L23/532 , H01L29/43 , H01L23/48
CPC分类号： H01L23/53223 , H01L2924/0002 , Y10S148/019
摘要： A three-layer metal contact including aluminum is provided for silicon-based semiconductor devices to minimize the effects of formation of silicon precipitates in the aluminum layer and low contact junction leakage. The metal contact comprises a first layer of a refractory metal silicide formed on a silicon surface, an intermediate layer of aluminum formed on the refractory metal silicide and a top layer of a refractory metal silicide formed on the layer of aluminum. Where contact is made to polysilicon layers forming high resistance load resistors, the metal contact of the invention prevents reduction in resistance resulting from the interdiffusion of silicon and aluminum.
摘要翻译：为硅基半导体器件提供包括铝的三层金属接触，以最大限度地减少铝层中硅沉淀物的形成和低接触结漏电的影响。金属接触包括形成在硅表面上的难熔金属硅化物的第一层，形成在难熔金属硅化物上的铝的中间层和形成在铝层上的难熔金属硅化物的顶层。当与形成高电阻负载电阻器的多晶硅层接触时，本发明的金属接触防止由于硅和铝的相互扩散而导致的电阻降低。

9. 发明授权

US5895961A Semiconductor device with a planarized interconnect with poly-plug and self-aligned contacts 失效
标题翻译：具有多插头和自对准触点的平面互连的半导体器件
公开(公告)号：US5895961A
公开(公告)日：1999-04-20
申请号：US780070
申请日：1996-12-23
申请人： Hsiang-Wen Chen
发明人： Hsiang-Wen Chen
IPC分类号： H01L21/3105 , H01L23/532 , H01L29/76
CPC分类号： H01L21/76895 , H01L21/31053 , H01L23/5329 , H01L2924/0002
摘要： A CMOS integrated circuit structure with planarized self-aligned transistors and local planarization in the vicinity of the transistors so as to allow an interconnect, with a planar upper surface, which is free of bridging, has good continuity over the planarized topography and is compatible with self-alignment schemes, hence conserving chip real estate. The structure is compatible with planarization using BPSG, BPTEOS, SOG or CMP. After formation of self-aligned insulated transistor gates and active transistor regions, a "landing pad" is formed on the substrate at the buried contact and polyiso contact locations so as to allow more effective etching at the exact location of the buried contact and polyiso contact. Then the integrated circuit structure is locally planarized by formation of an oxide layer and a reflowed overlying glass layer. The glass layer is etched back to planarize the surface. Then using a polyiso mask, portions of the glass layer and underlying oxide, landing pad, and nitride layers are removed in the area of a gate contact. Then using a buried contact mask, portions of the glass layer and underlying oxide, landing pad, and oxide layers are removed only in the area of the buried contact. Then a combined horizontal and vertical interconnect, with a planar upper surface, is formed to electrically connect the buried contact to the gate.
摘要翻译：具有平坦化自对准晶体管和在晶体管附近的局部平坦化的CMOS集成电路结构，以允许具有不具有桥接的平坦上表面的互连在平坦化地形上具有良好的连续性，并且与自行配套方案，因此节省芯片房地产。该结构与使用BPSG，BPTEOS，SOG或CMP的平面化兼容。在形成自对准绝缘晶体管栅极和有源晶体管区域之后，在掩埋触点和多异氰酸接触位置处的衬底上形成“着陆焊盘”，以便在掩埋触点和聚异氰酸接触的确切位置允许更有效的蚀刻。然后通过形成氧化物层和回流覆盖的玻璃层来将集成电路结构局部平坦化。将玻璃层回蚀刻以使表面平坦化。然后使用多面体掩模，在栅极接触的区域中去除部分玻璃层和下面的氧化物，着陆焊盘和氮化物层。然后使用掩埋接触掩模，玻璃层和下面的氧化物，着陆焊盘和氧化物层的部分仅在埋入触点的区域中被去除。然后，形成具有平坦的上表面的组合的水平和垂直互连，以将埋入的触点电连接到栅极。

10. 发明授权

US4892844A Making a low resistance three layered contact for silicon devices 失效
标题翻译：为硅器件制造低电阻三层接触
公开(公告)号：US4892844A
公开(公告)日：1990-01-09
申请号：US285188
申请日：1988-12-16
申请人： Robin W. Cheung , Bernard W. K. Ho , Hsiang-Wen Chen , Hugo W. K. Chan
发明人： Robin W. Cheung , Bernard W. K. Ho , Hsiang-Wen Chen , Hugo W. K. Chan
IPC分类号： H01L21/768 , H01L21/28 , H01L21/3205 , H01L23/52 , H01L23/522 , H01L23/532 , H01L29/43
CPC分类号： H01L23/53223 , H01L2924/0002 , Y10S148/019
摘要： A three-layer metal contact including aluminum is provided for silicon-based semiconductor devices to minimize the effects of formation of silicon precipitates in the aluminum layer and low contact junction leakage. The metal contact comprises a first layer of a refractory metal silicide formed on a silicon surface, an intermediate layer of aluminum formed on the refractory metal silicide and a top layer of a refractory metal silicide formed on the layer of aluminum. Where contact is made to polysilicon layers forming high resistance load resistors, the metal contact of the invention prevents reduction in resistance resulting from the interdiffusion of silicon and aluminum.

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