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1. 发明授权

US5864252A Synchronous circuit with improved clock to data output access time 失效
标题翻译：同步电路具有改进的时钟到数据输出访问时间
公开(公告)号：US5864252A
公开(公告)日：1999-01-26
申请号：US800195
申请日：1997-02-13
申请人： Thinh Dinh Tran , Tsu-Wei Frank Lee
发明人： Thinh Dinh Tran , Tsu-Wei Frank Lee
IPC分类号： H03K3/289
CPC分类号： H03K5/135 , G11C7/1039 , G11C7/1051 , G11C7/106 , G11C7/1066
摘要： A synchronous circuit, such as an SRAM, a DRAM or a programmable logic device, has internal circuitry, a master input latch clocked by a master clock generator, and a slave output latch clocked by a slave clock generator. The master input latch is rendered transparent prior to the start of system setup time so that information input signals can pass through the master input latch and undergo processing in the circuitry prior to the start of a system cycle. After correct and stable information output signals are generated by the internal circuitry, these signals are latched into the slave output latch as correct and stable output information. The master latch may be clocked from the latched to the transparent state before the slave latch is clocked from the transparent to the latched state, provided that the time period between these two transitions is less than the minimum processing time of the internal circuitry. By advancing the start of the internal signal processing by a time period equal to the system setup time, the system clock to data output access time is substantially shortened.
摘要翻译：诸如SRAM，DRAM或可编程逻辑器件的同步电路具有内部电路，由主时钟发生器计时的主输入锁存器和由时钟发生器提供时钟的从输出锁存器。在系统建立时间开始之前，主输入锁存器变为透明的，以便信息输入信号可以通过主输入锁存器并在系统周期开始之前在电路中进行处理。在由内部电路产生正确和稳定的信息输出信号后，这些信号被锁存到从输出锁存器中作为正确和稳定的输出信息。如果这两个转换之间的时间间隔小于内部电路的最小处理时间，则从锁存器从透明时钟到锁存状态，主锁存器可以从锁存时钟到透明状态。通过将内部信号处理的开始推进到与系统建立时间相同的时间段，系统时钟到数据输出访问时间显着缩短。

2. 发明授权

US5656861A Self-aligning contact and interconnect structure 失效
标题翻译：自调心接触和互连结构
公开(公告)号：US5656861A
公开(公告)日：1997-08-12
申请号：US450847
申请日：1995-05-25
申请人： Norman Godinho , Tsu-Wei Frank Lee , Hsiang-Wen Chen , Richard F. Motta , Juine-Kai Tsang , Joseph Tzou , Jai-Man Baik , Ting-Pwu Yen
发明人： Norman Godinho , Tsu-Wei Frank Lee , Hsiang-Wen Chen , Richard F. Motta , Juine-Kai Tsang , Joseph Tzou , Jai-Man Baik , Ting-Pwu Yen
IPC分类号： H01L21/60 , H01L21/768 , H01L21/8238 , H01L21/8244 , H01L23/532 , H01L27/11 , H01L23/48
CPC分类号： H01L21/76897 , H01L21/76895 , H01L21/823864 , H01L21/823871 , H01L23/53257 , H01L23/53271 , H01L27/11 , H01L27/1112 , H01L27/1104 , H01L2924/0002 , H01L2924/3011 , Y10S257/90 , Y10S257/903 , Y10S257/904
摘要： An MOS transistor for use in an integrated circuit is fabricated with a self-aligning contact and interconnect structure which allows for higher packing density. Self-aligning source and drain contacts overlap the gate but are prevented from a short circuiting to the gate by oxide insulation between the source/drain contacts and the gate, and a layer of silicon nitride above the gate. Contacts to the gate are made on top of the gate over the active region of the transistor because the source and drain regions are protected by a hardened layer of photoresist during etching of insulation to expose the gate contact. Source, drain and gate contacts are protected by a layer of titanium silicide so that interconnects are not required to completely cover these areas. Low resistance interconnects are formed of doped polysilicon covered by titanium silicide encapsulated by a thin film of titanium nitride.
摘要翻译：用于集成电路的MOS晶体管是用自对准接触和互连结构制造的，其允许更高的封装密度。自对准源极和漏极触点与栅极重叠，但是通过源极/漏极接触和栅极之间的氧化物绝缘以及栅极上方的氮化硅层来防止与栅极的短路。在晶体管的有源区域上，在栅极的顶部形成与栅极的触点，因为源极和漏极区域在蚀刻绝缘体以暴露栅极接触期间被硬化的光致抗蚀剂层保护。源极，漏极和栅极触点被一层硅化钛保护，使得互连不需要完全覆盖这些区域。低电阻互连由氮化钛薄膜封装的由硅化钛覆盖的掺杂多晶硅形成。

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